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raw | patch | inline | side by side (parent: f9ab18c)
raw | patch | inline | side by side (parent: f9ab18c)
author | Govind Jeyaram <govind.j@ti.com> | |
Sat, 1 Apr 2017 00:47:54 +0000 (17:47 -0700) | ||
committer | Govind Jeyaram <govind.j@ti.com> | |
Sat, 1 Apr 2017 00:47:54 +0000 (17:47 -0700) |
pasdk/test_dsp/sap/sap_d10.c | patch | blob | history | |
psdk_cust/pdk_k2g_1_0_1_1_eng/packages/ti/platform/evmk2g/platform_lib/src/platform_audio.c | patch | blob | history |
index 5eb381dd9d54cb0f037cabd1d5e4ba16d4e9beaa..bd85fb903f6531b47f54ff763fd7e5509c9a94e5 100644 (file)
24, // precision (in bits)
D10_sapControl, // control
0x1600000F, // pinMask
- 0, // mode
+ (D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
0,0,0 // unused[3]
};
24, // precision (in bits)
D10_sapControl, // control
0x1E00000F, // pinMask
- 0, // mode
+ (D10_MCLK_OSC << D10_MCLK_SHIFT), // mode
0,0,0 // unused[3]
};
status = platformAudioInit();
if(status != Platform_EOK)
{
- System_printf("Audio Init Failed!\n");
+ Log_info0("Audio Init Failed!\n");
return status;
}
status = audioAdcConfig(ADC_DEVICE_ALL, &adcCfg);
if(status != Platform_EOK)
{
- platform_write("Audio ADC Configuration Failed!\n");
+ Log_info0("Audio ADC Configuration Failed!\n");
return status;
}
Log_info0("Audio DIR Init Failed!\n");
return status;
}
+ status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_I2S);
+ platform_delay(5000); // Without delay between these 2 calls system aborts.
+ status = setAudioDacConfig();
#if 1
/* Setup HSR41 for HDMI input operation */
}
#endif
- // This is needed because DAC configuration needs some default clocking.
- // We start with S/PDIF, because it's onboard the Audio DC & has its own crystal.
- // HDMI is an add-on board & Audio OSC would need AUX clocking - both unfit for "default".
- // ADCs default clock is not available to clock the DAC with.
- status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
-
- platform_delay(5000); // Without delay between these 2 calls system aborts.
-
- status = setAudioDacConfig();
+ Log_info1("Leaving initD10 with status = %d", status);
return status;
status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_OSC);
pClkxDiv = (unsigned char *) clkxDivADC;
}
+ Log_info1("SAP_D10: Inside clockMuxTx with sel = %d", sel);
platform_delay(20000);
@@ -859,7 +855,7 @@ static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PA
//
pStatusIn->lock = 1;
pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
- RateHdmi = PAF_SAMPLERATE_192000HZ;
+ RateHdmi = HSDIO_AudioFreq_192K;
pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
@@ -876,7 +872,7 @@ static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PA
pStatusIn->sampleRateMeasured = RateTable_hdmi[RateHdmi];
pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
PrevSampRate = pStatusIn->sampleRateMeasured;
-
+/*
switch(read_hdmi_errstatus())
{
case HSDIO_AudioErr_NO_ERROR:
@@ -914,7 +910,8 @@ static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PA
{
gNonAudio_ctr++;
pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_NONAUDIO;
- }
+ }*/
+
}
else
{
@@ -965,15 +962,15 @@ static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, f
else
rateX = 4.00;
// if asynchronous then force clock change (assumes osc master)
- if (pParams->d10tx.mode & D10_SYNC_MASK) {
+ /*if (pParams->d10tx.mode & D10_SYNC_MASK) {
int dacRate = (pParams->d10tx.mode & D10_RATE_MASK) >> D10_RATE_SHIFT;
divider = pClkxDiv[oscRateTable[dacRate]];
}
- else
+ else*/
divider = pClkxDiv[pStatusIn->sampleRateMeasured];
divider /= rateX;
- Log_info2("SAP_D10: Inside manageOutput with divider = %d, rateX = %f", divider, rateX);
+ Log_info3("SAP_D10: Inside manageOutput with divider = %d, rateX = %f & input_rate = %d", divider, rateX, pStatusIn->sampleRateMeasured);
// DIT requires 2x clock
if ((mcasp[_MCASP_AFSXCTL_OFFSET] & _MCASP_AFSXCTL_XMOD_MASK) ==
@@ -1061,9 +1058,9 @@ XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XD
// Since DAC is a slave to the chosen input, operate the clksel switch appropriately
// Also, this is a create-time (i.e, CTRL_OPEN) only call & not appropriate under
// the periodic manage_output calls.
- int sel = (pDapD10RxParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
+ int sel = (pDapD10TxParams->d10tx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
clockMuxTx (sel, -1);
- platform_delay(5000); // GJ REVISIT: Without delay between Tx McASP & DAC configs, system aborts.
+ platform_delay(50000); // GJ REVISIT: Without delay between Tx McASP & DAC configs, system aborts.
setAudioDacConfig();
dacHardUnMute ();
diff --git a/psdk_cust/pdk_k2g_1_0_1_1_eng/packages/ti/platform/evmk2g/platform_lib/src/platform_audio.c b/psdk_cust/pdk_k2g_1_0_1_1_eng/packages/ti/platform/evmk2g/platform_lib/src/platform_audio.c
index 2fa9737f6b988e237cc76fceb61abb48131cf465..5ca58b2a3155187026bf130cc46846863a147b3b 100644 (file)
/* Configure GPIO for McASP_CLK_SEL - GPIO0 132 & PADCONFIG 163 */
pinMuxSetMode(163, PADCONFIG_MUX_MODE_QUATERNARY);
gpioSetDirection(GPIO_PORT_0, PLATFORM_AUDIO_CLK_SEL_GPIO, GPIO_OUT);
- /* Slect the clock source as DIR */
- gpioSetOutput(GPIO_PORT_0, PLATFORM_AUDIO_CLK_SEL_GPIO);
+ /* Slect the clock source as I2S */
+ gpioClearOutput(GPIO_PORT_0, PLATFORM_AUDIO_CLK_SEL_GPIO);
/* Configure GPIO for McASP_CLK_SEL# - GPIO0 101 & PADCONFIG 110 */
pinMuxSetMode(110, PADCONFIG_MUX_MODE_QUATERNARY);
gpioSetDirection(GPIO_PORT_0, PLATFORM_AUDIO_CLK_SELz_GPIO, GPIO_OUT);
- /* Slect the clock source as DIR */
+ /* Slect the clock source as I2S */
//gpioClearOutput(GPIO_PORT_0, PLATFORM_AUDIO_CLK_SELz_GPIO);
gpioSetOutput(GPIO_PORT_0, PLATFORM_AUDIO_CLK_SELz_GPIO); // Default configurations are set for McASP AHCLK driven by SoC