Merge remote-tracking branch 'origin/PASDK-136-new-i-o-integration-into-pasdk-1-x...
authorFrank Livingston <frank-livingston@ti.com>
Thu, 1 Mar 2018 19:45:43 +0000 (13:45 -0600)
committerFrank Livingston <frank-livingston@ti.com>
Thu, 1 Mar 2018 19:45:43 +0000 (13:45 -0600)
15 files changed:
pasdk/test_dsp/.cproject
pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c
pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.h
pasdk/test_dsp/application/itopo/evmk2g/sap_d10.c
pasdk/test_dsp/application/itopo/evmk2g/sap_d10.h
pasdk/test_dsp/framework/audioStreamInpDec.c
pasdk/test_dsp/framework/audioStreamInpProc.c
pasdk/test_dsp/framework/audioStreamInpProc.h
pasdk/test_dsp/framework/audioStreamInpProcNewIO.c
pasdk/test_dsp/framework/audioStreamOutInit.c
pasdk/test_dsp/framework/audioStreamOutIo.c
pasdk/test_dsp/framework/audioStreamOutIo.h
pasdk/test_dsp/framework/audioStreamOutProc.c
pasdk/test_dsp/framework/itopo/params.c
pasdk/test_dsp/mib/mib.c

index edadf52d27f3da12dd88e56138023b22d9bbecc8..ef9a2468c058f20c3a923af65ac50e1fe612024a 100644 (file)
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index 96913f1559482a00ef075a748f78ec1fba5a695b..c6dba5f10de5b49ff26a3df49eb7988d269aa5f2 100644 (file)
 
 #define AUDIO_DAC0_TEST
 
-/* McASP device handles */
-Ptr hMcaspDevTx;
-Ptr hMcaspDevRx;
+/* McASP device handles - one for each McASP port. */
+Ptr mcaspDevHandles[NUM_MCASP_PORTS] = {NULL, NULL, NULL};
 
-/* McASP channel handles */
-Ptr hMcaspTxChan;
-Ptr hMcaspRxChan;
-Ptr hMcaspRxChan2;
-
-/* McASP channel parameters */
-Mcasp_Params mcaspTxParams;
-Mcasp_Params mcaspRxParams;
-
-/* McASP Callback function argument */
-//uint32_t txChanMode;
-//uint32_t rxChanMode;
+/* McASP parameters needed by mcaspBindDev */
+Mcasp_Params mcaspParams;
 
 /* Error flag */
 uint32_t gblErrFlag = 0;
@@ -66,6 +55,10 @@ Error_Block eb;
 
 void GblErr(Mcasp_errCbStatus arg);
 
+/* Handle to eDMA */
+extern EDMA3_DRV_Handle hEdma0;
+extern EDMA3_DRV_Handle hEdma1;
+
 /* External function declarations */
 extern void McaspDevice_init(void);
 extern signed char*  getGlobalAddr(signed char* addr);
@@ -76,11 +69,67 @@ extern void mcaspAppCallbackTx(void* arg, MCASP_Packet *mcasp_packet);
 #else
 extern void asipMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
 extern void asopMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
-
 #endif
 
-/* McASP HW setup for receive */
-Mcasp_HwSetupData mcaspRcvSetup = {
+/* McASP HW setup that is common for receive and transmit. It is the same for
+ * all of 3 McASP ports. */
+Mcasp_HwSetupGbl mcaspGblSetup = {
+            (Uint32)0x0,        /* pfunc   */
+            (Uint32)0x2000001,  /* pdir    */
+            (Uint32)0x0,        /* ctl     */
+            (Uint32)0x0,        /* ditCtl  */
+            (Uint32)0x0,        /* dlbMode */
+            (Uint32)0x2,        /* amute   */
+            {
+                (Uint32)0x0,  /* [0] */
+                (Uint32)0x0,  /* [1] */
+                (Uint32)0x0,  /* [2] */
+                (Uint32)0x0,  /* [3] */
+                (Uint32)0x0,  /* [4] */
+                (Uint32)0x0,  /* [5] */
+                (Uint32)0x0,  /* [6] */
+                (Uint32)0x0,  /* [7] */
+                (Uint32)0x0,  /* [8] */
+                (Uint32)0x0,  /* [9] */
+                (Uint32)0x0,  /* [10] */
+                (Uint32)0x0,  /* [11] */
+                (Uint32)0x0,  /* [12] */
+                (Uint32)0x0,  /* [13] */
+                (Uint32)0x0,  /* [14] */
+                (Uint32)0x0,  /* [15] */
+            }   /* serSetup */
+};
+
+/* McASP HW setup for receive (ADC) */
+Mcasp_HwSetupData mcaspRcvSetupADC = {
+        /* .rmask    = */ 0xFFFFFFFF, /* 16 bits are to be used     */
+        /* .rfmt     = */ 0x000180F2, /*
+                                       * 0 bit delay from framesync
+                                       * MSB first
+                                       * No extra bit padding
+                                       * Padding bit (ignore)
+                                       * slot Size is 32
+                                       * Reads from DMA port
+                                       * NO rotation
+                                       */
+        /* .afsrctl  = */ 0X00000112, /* I2S mode - 2 slot TDM
+                                       * Frame sync is one word
+                                       * Internally generated frame sync
+                                       * Rising edge is start of frame
+                                       */
+        /* .rtdm     = */ 0x00000003, /* slot 1 and 2 are active (I2S)        */
+        /* .rintctl  = */ 0x00000000, /* sync error and overrun error         */
+        /* .rstat    = */ 0x000001FF, /* reset any existing status bits       */
+        /* .revtctl  = */ 0x00000000, /* DMA request is enabled               */
+        {
+             /* .aclkrctl  = */ 0x000000A7,
+             /* .ahclkrctl = */ 0x0000C000,
+             /* .rclkchk   = */ 0x00000000
+        }
+};
+
+/* McASP HW setup for receive (S/PDIF or HDMI)*/
+Mcasp_HwSetupData mcaspRcvSetupDIR = {
        MCASP_DIR_RMASK,   /* .rmask:   0xFFFFFFFF    */
        MCASP_DIR_RFMT,    /* .rfmt:    0x000180F0    */
        MCASP_DIR_AFSRCTL, /* .afsrctl: 0x00000111    */
@@ -95,8 +144,8 @@ Mcasp_HwSetupData mcaspRcvSetup = {
         }
 };
 
-/* McASP HW setup for transmit */
-Mcasp_HwSetupData mcaspXmtSetup = {
+/* McASP HW setup for transmit (DAC) */
+Mcasp_HwSetupData mcaspXmtSetupDAC = {
         /* .xmask    = */ 0xFFFFFFFF, /* 16 bits are to be used     */
         /* .xfmt     = */ 0x000180F0, /*
                                        * 0 bit delay from framesync
@@ -121,19 +170,113 @@ Mcasp_HwSetupData mcaspXmtSetup = {
              /* .ahclkxctl = */ 0x00004000     ,
              /* .xclkchk   = */ 0x00000000
         },
+};
+
+/* McASP HW setup for transmit (DAC slave) */
+Mcasp_HwSetupData mcaspXmtSetupDACSlave = {
+        /* .xmask    = */ 0xFFFFFFFF, /* 16 bits are to be used     */
+        /* .xfmt     = */ 0x000180F6, /*
+                                       * 0 bit delay from framesync
+                                       * MSB first
+                                       * No extra bit padding
+                                       * Padding bit (ignore)
+                                       * slot Size is 32
+                                       * Reads from DMA port
+                                       * NO rotation
+                                       */
+        /* .afsxctl  = */ 0x00000112, /* I2S mode - 2 slot TDM
+                                       * Frame sync is one word
+                                       * Rising edge is start of frame
+                                       * Internally generated frame sync
+                                       */
+        /* .xtdm     = */ 0x00000003, /* slot 1 and 2 are active (I2S)        */
+        /* .xintctl  = */ 0x00000000, /* sync error,overrun error,clK error   */
+        /* .xstat    = */ 0x000001FF, /* reset any existing status bits       */
+        /* .xevtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */
+        {
+             /* .aclkxctl  = */ 0X000000A7,
+             /* .ahclkxctl = */ 0x0000C000,
+             /* .xclkchk   = */ 0x00000000
+        },
+};
 
+/* McASP channel parameters for ADC input */
+Mcasp_ChanParams  mcaspRxChanParamADC =
+{
+    0x0004,                   /* number of serializers      */
+    {Mcasp_SerializerNum_0,
+     Mcasp_SerializerNum_1,
+     Mcasp_SerializerNum_2,
+     Mcasp_SerializerNum_3 }, /* serializer index           */
+    &mcaspRcvSetupADC,
+    TRUE,                     /* isDmaDriven                */
+    Mcasp_OpMode_TDM,         /* Mode (TDM/DIT)             */
+    Mcasp_WordLength_32,      /* wordWidth                  */
+    NULL,                     /* void * userLoopJobBuffer   */
+    0,                        /* userLoopJobLength          */
+    NULL,                   /* edmaHandle                 */
+    GblErr,
+    2,                        /* number of TDM channels      */
+    Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
+    TRUE,                     /* enableHwFifo */
+    1,                        /* hwFifoEventDMARatio */
+    TRUE,                     /* isDataPacked */
+    Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
 };
 
-#ifdef INPUT_SPDIF
-/* McAsp channel parameters for receive - DIR                */
-Mcasp_ChanParams  mcaspRxChanParam =
+/* McASP channel parameters for ADC 6 channel input */
+Mcasp_ChanParams  mcaspRxChanParamADC6ch =
+{
+    0x0003,                   /* number of serializers      */
+    {Mcasp_SerializerNum_0,
+     Mcasp_SerializerNum_1,
+     Mcasp_SerializerNum_2},  /* serializer index           */
+    &mcaspRcvSetupADC,
+    TRUE,
+    Mcasp_OpMode_TDM,         /* Mode (TDM/DIT)             */
+    Mcasp_WordLength_32,
+    NULL,
+    0,
+    NULL,
+    GblErr,
+    2,                        /* number of TDM channels      */
+    Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
+    TRUE,                     /* enableHwFifo */
+    1,                        /* hwFifoEventDMARatio */
+    TRUE,                     /* isDataPacked */
+    Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
+};
+
+/* McASP channel parameters for ADC stereo input */
+Mcasp_ChanParams  mcaspRxChanParamADCStereo =
+{
+    0x0001,                   /* number of serializers      */
+    {Mcasp_SerializerNum_0},  /* serializer index           */
+    &mcaspRcvSetupADC,
+    TRUE,
+    Mcasp_OpMode_TDM,         /* Mode (TDM/DIT)             */
+    Mcasp_WordLength_32,
+    NULL,
+    0,
+    NULL,
+    GblErr,
+    2,                        /* number of TDM channels      */
+    Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
+    TRUE,                     /* enableHwFifo */
+    1,                        /* hwFifoEventDMARatio */
+    TRUE,                     /* isDataPacked */
+    Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
+};
+
+/* McAsp channel parameters for DIR input                 */
+Mcasp_ChanParams  mcaspRxChanParamDIR =
 {
        0x0001,                    /* Number of serializers      */
        {Mcasp_SerializerNum_5},   /* Serializer index           */
-       &mcaspRcvSetup,
+       &mcaspRcvSetupDIR,
        TRUE,
        Mcasp_OpMode_TDM,          /* Mode (TDM/DIT)             */
-       Mcasp_WordLength_32,
+       Mcasp_WordLength_16,       /* 16-bit by default          */
        NULL,
        0,
        NULL,
@@ -145,9 +288,8 @@ Mcasp_ChanParams  mcaspRxChanParam =
        TRUE,                     /* isDataPacked */
        Mcasp_WordBitsSelect_MSB  /* wordBitsSelect */
 };
-#endif
 
-/* McASP LLD channel parameters for HDMI input:
+/* McASP LLD channel parameters for HDMI input with 4XI2S:
  *     When slot size of McASP is configured to 32-bit, HDMI data always come to 16 MSBs of the slot
  *     and the 16 LSBs are filled with 0's. This is the nature of HDMI and I2S.
  *     For PCM data, we want all 32 bits in the slot to be transferred to the input buffer:
@@ -159,23 +301,17 @@ Mcasp_ChanParams  mcaspRxChanParam =
  *        - isDataPacked = 1,
  *        - wordBitsSelect = Mcasp_WordBitsSelect_MSB
  */
-#ifdef INPUT_HDMI_4xI2S
-/* McAsp channel parameters for receive - HDMI 4XI2S layout  */
-Mcasp_ChanParams  mcaspRxChanParam =
+Mcasp_ChanParams  mcaspRxChanParamHDMI =
 {
        0x0004,                    /* number of serializers      */
        {Mcasp_SerializerNum_12,
         Mcasp_SerializerNum_13,
         Mcasp_SerializerNum_14,
         Mcasp_SerializerNum_15 }, /* serializer index           */
-       &mcaspRcvSetup,
+       &mcaspRcvSetupDIR,
        TRUE,
        Mcasp_OpMode_TDM,          /* Mode (TDM/DIT)             */
-#ifdef INPUT_PCM_ONLY
-       Mcasp_WordLength_32,       /* 32-bit word length, whole slot (size=32) to be transfered */
-#else
     Mcasp_WordLength_16,       /* 16-bit word length, MSB or LSB of slot to be transfered, depending on wordBitsSelect */
-#endif
        NULL,
        0,
        NULL,
@@ -187,18 +323,16 @@ Mcasp_ChanParams  mcaspRxChanParam =
        TRUE,                     /* isDataPacked, only transfer the selected bits of slot, based on wordWidth and wordBitsSelect */
        Mcasp_WordBitsSelect_MSB  /* wordBitsSelect, only matters if wordWidth < slot size */
 };
-#endif
 
-#ifdef INPUT_HDMI_STEREO
-/* McAsp channel parameters for receive - HDMI   1XI2S layout             */
-Mcasp_ChanParams  mcaspRxChanParam =
+/* McAsp channel parameters for HDMI stereo input with 1XI2S  */
+Mcasp_ChanParams  mcaspRxChanParamHDMIStereo =
 {
        0x0001,                    /* Number of serializers      */
-       {Mcasp_SerializerNum_12},   /* Serializer index           */
-       &mcaspRcvSetup,
+       {Mcasp_SerializerNum_12},   /* Serializer index          */
+       &mcaspRcvSetupDIR,
        TRUE,
        Mcasp_OpMode_TDM,          /* Mode (TDM/DIT)             */
-       Mcasp_WordLength_32,
+    Mcasp_WordLength_16,       /* 16-bit by default          */
        NULL,
        0,
        NULL,
@@ -210,38 +344,16 @@ Mcasp_ChanParams  mcaspRxChanParam =
        TRUE,                     /* isDataPacked */
        Mcasp_WordBitsSelect_MSB  /* wordBitsSelect */
 };
-#endif
 
-/* McAsp channel parameters for transmit - DAC0              */
-#ifndef TX_MCASP_USE_MULT_SER
-Mcasp_ChanParams  mcaspTx0ChanParam =
-{
-       0x0001,                   /* number of serializers       */
-       {Mcasp_SerializerNum_0}, /* serializer index for DAC0    */
-       &mcaspXmtSetup,
-       TRUE,
-       Mcasp_OpMode_TDM,
-       Mcasp_WordLength_32,      /* word width                  */
-       NULL,
-       0,
-       NULL,
-       GblErr,
-       2,                        /* number of TDM channels      */
-       Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
-       TRUE,
-       1,                        /* hwFifoEventDMARatio */
-       TRUE,                     /* isDataPacked */
-       Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
-};
-#else
-Mcasp_ChanParams  mcaspTx0ChanParam =
+/* McAsp channel parameters for DAC output - DAC0            */
+Mcasp_ChanParams  mcaspTx0ChanParamDAC =
 {
        0x0004,                   /* number of serializers       */
        {Mcasp_SerializerNum_0,
         Mcasp_SerializerNum_1,
         Mcasp_SerializerNum_2,
-        Mcasp_SerializerNum_3 }, /* serializer index for DAC0    */
-       &mcaspXmtSetup,
+        Mcasp_SerializerNum_3 }, /* serializer index for DAC0   */
+       &mcaspXmtSetupDAC,
        TRUE,
        Mcasp_OpMode_TDM,
        Mcasp_WordLength_32,      /* word width                  */
@@ -256,14 +368,88 @@ Mcasp_ChanParams  mcaspTx0ChanParam =
        TRUE,                     /* isDataPacked */
        Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
 };
-#endif
+
+/* McAsp channel parameters for DAC stereo output - DAC0     */
+Mcasp_ChanParams  mcaspTx0ChanParamDACStereo =
+{
+    0x0001,                   /* number of serializers       */
+    {Mcasp_SerializerNum_0},  /* serializer index for DAC0   */
+    &mcaspXmtSetupDAC,
+    TRUE,
+    Mcasp_OpMode_TDM,
+    Mcasp_WordLength_32,      /* word width                  */
+    NULL,
+    0,
+    NULL,
+    GblErr,
+    2,                        /* number of TDM channels      */
+    Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
+    TRUE,
+    1,                        /* hwFifoEventDMARatio */
+    TRUE,                     /* isDataPacked */
+    Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
+};
+
+/* McAsp channel parameters for DAC 12 channel output        */
+Mcasp_ChanParams  mcaspTx0ChanParamDAC12ch =
+{
+    0x0006,                   /* number of serializers       */
+    {Mcasp_SerializerNum_0,
+     Mcasp_SerializerNum_1,
+     Mcasp_SerializerNum_2,
+     Mcasp_SerializerNum_3,
+     Mcasp_SerializerNum_4,
+     Mcasp_SerializerNum_5 }, /* serializer index for DAC0    */
+    &mcaspXmtSetupDAC,
+    TRUE,
+    Mcasp_OpMode_TDM,
+    Mcasp_WordLength_32,      /* word width                  */
+    NULL,
+    0,
+    NULL,
+    GblErr,
+    2,                        /* number of TDM channels      */
+    Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
+    TRUE,
+    1,                        /* hwFifoEventDMARatio */
+    TRUE,                     /* isDataPacked */
+    Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
+};
+
+/* McAsp channel parameters for DAC 16 channel output        */
+Mcasp_ChanParams  mcaspTx0ChanParamDAC16ch =
+{
+    0x0008,                   /* number of serializers       */
+    {Mcasp_SerializerNum_0,
+     Mcasp_SerializerNum_1,
+     Mcasp_SerializerNum_2,
+     Mcasp_SerializerNum_3,
+     Mcasp_SerializerNum_4,
+     Mcasp_SerializerNum_5,
+     Mcasp_SerializerNum_6,
+     Mcasp_SerializerNum_7 }, /* serializer index for DAC0    */
+    &mcaspXmtSetupDAC,
+    TRUE,
+    Mcasp_OpMode_TDM,
+    Mcasp_WordLength_32,      /* word width                  */
+    NULL,
+    0,
+    NULL,
+    GblErr,
+    2,                        /* number of TDM channels      */
+    Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
+    TRUE,
+    1,                        /* hwFifoEventDMARatio */
+    TRUE,                     /* isDataPacked */
+    Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
+};
 
 /* McAsp channel parameters for transmit - DAC1              */
 Mcasp_ChanParams  mcaspTx1ChanParam =
 {
        0x0001,                   /* number of serializers       */
        {Mcasp_SerializerNum_4},  /* serializer index for DAC0   */
-       &mcaspXmtSetup,
+       &mcaspXmtSetupDAC,
        TRUE,
        Mcasp_OpMode_TDM,
        Mcasp_WordLength_32,      /* word width                  */
@@ -279,9 +465,6 @@ Mcasp_ChanParams  mcaspTx1ChanParam =
        Mcasp_WordBitsSelect_LSB  /* wordBitsSelect */
 };
 
-/* Handle to eDMA */
-extern EDMA3_DRV_Handle hEdma0;
-extern EDMA3_DRV_Handle hEdma1;
 
 /**
  *  \brief    Function called by McASP driver in case of error
@@ -326,7 +509,7 @@ void configAudioDAC(void)
                //testRet(1);
        }
 }
-
+#if 0
 /**
  *  \brief   Configures McASP module and creates the channel
  *           for audio Tx and Rx
@@ -443,6 +626,12 @@ Audk2g_STATUS mcaspAudioConfig(void)
        return (Audk2g_EOK);
 } /* mcaspAudioConfig */
 
+
+Audk2g_STATUS mcaspRx(void)
+{
+
+}
+
 Audk2g_STATUS mcaspRxDeInit(void)
 {
        mcaspDeleteChan(hMcaspRxChan);
@@ -454,6 +643,13 @@ Audk2g_STATUS mcaspRxDeInit(void)
     return (Audk2g_EOK);
 }
 
+Audk2g_STATUS mcaspChanReset(Ptr hMcaspDev, Ptr hMcaspChan)
+{
+    if(hMcaspChan != NULL) {
+        mcaspDeleteChan(hMcaspChan);
+    }
+}
+
 Audk2g_STATUS mcaspRxReset(void)
 {
     if(hMcaspRxChan != NULL) {
@@ -518,6 +714,7 @@ Audk2g_STATUS mcaspTxCreate(void)
 
        return (Audk2g_EOK);
 }
+#endif
 
 
 Audk2g_STATUS mcaspRecfgWordWidth(Ptr hMcaspChan, uint16_t wordWidth)
@@ -549,4 +746,240 @@ int mcaspCheckOverUnderRun(Ptr mcaspChanHandle)
     return (mcaspErrStat.isRcvOvrRunOrTxUndRunErr);
 }
 
+
+/** McASP LLD configuration parameters for all input and output interfaces */
+mcaspLLDconfig LLDconfigRxDIR =     // for SAP_D10_RX_DIR
+{
+    &mcaspGblSetup,
+    &mcaspRcvSetupDIR, 
+    &mcaspRxChanParamDIR,
+    0x23,
+    0x23,
+    CSL_MCASP_2,
+    MCASP_INPUT,
+    asipMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigRxADC =     // for SAP_D10_RX_ADC_44100HZ, SAP_D10_RX_ADC_88200HZ
+{
+    &mcaspGblSetup,
+    &mcaspRcvSetupADC, 
+    &mcaspRxChanParamADC,
+    0x23,
+    0x23,
+    CSL_MCASP_1,
+    MCASP_INPUT,
+    asipMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigRxADC6ch =     // for SAP_D10_RX_ADC_6CH_44100HZ, SAP_D10_RX_ADC_6CH_88200HZ
+{
+    &mcaspGblSetup,
+    &mcaspRcvSetupADC, 
+    &mcaspRxChanParamADC6ch,
+    0x23,
+    0x23,
+    CSL_MCASP_1,
+    MCASP_INPUT,
+    asipMcaspCallback,
+    NULL,
+    NULL,
+};
+
+mcaspLLDconfig LLDconfigRxADCStereo =     // for SAP_D10_RX_ADC_STEREO_44100HZ, SAP_D10_RX_ADC_STEREO_88200HZ
+{
+    &mcaspGblSetup,
+    &mcaspRcvSetupADC, 
+    &mcaspRxChanParamADCStereo,
+    0x23,
+    0x23,
+    CSL_MCASP_1,
+    MCASP_INPUT,
+    asipMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigRxHDMIStereo =   // for SAP_D10_RX_HDMI_STEREO
+{
+    &mcaspGblSetup,
+    &mcaspRcvSetupDIR, 
+    &mcaspRxChanParamHDMIStereo,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_INPUT,
+    asipMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigRxHDMI =    // for SAP_D10_RX_HDMI
+{
+    &mcaspGblSetup,
+    &mcaspRcvSetupDIR, 
+    &mcaspRxChanParamHDMI,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_INPUT,
+    asipMcaspCallback,
+    NULL,
+    NULL
+};
+
+/*
+mcaspLLDconfig LLDconfigTxDIT =    // for SAP_D10_TX_DIT
+{
+    &mcaspGblSetup,
+    &mcaspXmtSetupDIT, 
+    &mcaspTx0ChanParamDIT,
+    NULL,
+    NULL,
+    CSL_MCASP_2
+};
+*/
+
+mcaspLLDconfig LLDconfigTxDAC =    // for SAP_D10_TX_DAC
+{
+    &mcaspGblSetup,
+    &mcaspXmtSetupDAC, 
+    &mcaspTx0ChanParamDAC,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_OUTPUT,
+    asopMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigTxDACSlave =    // for SAP_D10_TX_DAC_SLAVE
+{
+    &mcaspGblSetup,
+    &mcaspXmtSetupDACSlave, 
+    &mcaspTx0ChanParamDAC,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_OUTPUT,
+    asopMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigTxDACStereo =    // for SAP_D10_TX_STEREO_DAC
+{
+    &mcaspGblSetup,
+    &mcaspXmtSetupDAC, 
+    &mcaspTx0ChanParamDACStereo,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_OUTPUT,
+    asopMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigTxDACStereoSlave =    // for SAP_D10_TX_STEREO_DAC_SLAVE
+{
+    &mcaspGblSetup,
+    &mcaspXmtSetupDACSlave, 
+    &mcaspTx0ChanParamDACStereo,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_OUTPUT,
+    asopMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigTxDAC12ch =    // for SAP_D10_TX_DAC_12CH
+{
+    &mcaspGblSetup,
+    &mcaspXmtSetupDAC, 
+    &mcaspTx0ChanParamDAC12ch,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_OUTPUT,
+    asopMcaspCallback,
+    NULL,
+    NULL
+};
+
+mcaspLLDconfig LLDconfigTxDAC16ch =    // for SAP_D10_TX_DAC_16CH
+{
+    &mcaspGblSetup,
+    &mcaspXmtSetupDAC, 
+    &mcaspTx0ChanParamDAC16ch,
+    0x23,
+    0x63,
+    CSL_MCASP_0,
+    MCASP_OUTPUT,
+    asopMcaspCallback,
+    NULL,
+    NULL
+};
+
+
+/**
+ *  \brief Create a channel of McASP LLD and return the handle.
+ *
+ *  \return    Audk2g_EOK on Success or error code
+ */
+Audk2g_STATUS mcasplldChanCreate(mcaspLLDconfig *lldCfg, Ptr *pChanHandle)
+{
+    int32_t status;
+
+    if(mcaspDevHandles[lldCfg->mcaspPort] == NULL) {
+        /* Initialize McASP Tx and Rx parameters */
+        mcaspParams = Mcasp_PARAMS;
+
+        //mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x23;  // not used
+        //mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x23;  // not used
+        mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = lldCfg->clkSetupClkRx;
+        mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = lldCfg->clkSetupClkTx;
+
+        mcaspParams.mcaspHwSetup.glb.pdir  = lldCfg->mcaspSetupGbl->pdir;
+        mcaspParams.mcaspHwSetup.glb.amute = lldCfg->mcaspSetupGbl->amute;
+
+        status = mcaspBindDev(&mcaspDevHandles[lldCfg->mcaspPort], lldCfg->mcaspPort, &mcaspParams);
+        if((status != MCASP_COMPLETED) || (mcaspDevHandles[lldCfg->mcaspPort] == NULL)) {
+            //IFPRINT(platform_write("mcaspBindDev for Tx Failed\n"));
+            return (Audk2g_EFAIL);
+        }
+    }
+
+    lldCfg->hMcaspDev = mcaspDevHandles[lldCfg->mcaspPort];
+
+    lldCfg->mcaspChanParams->mcaspSetup = lldCfg->mcaspSetupData;
+    if(lldCfg->mcaspPort == CSL_MCASP_0) {
+        lldCfg->mcaspChanParams->edmaHandle = hEdma0;
+    }
+    else {
+        lldCfg->mcaspChanParams->edmaHandle = hEdma1;
+    }
+
+    /* Create McASP channel for Tx */
+    *pChanHandle = NULL;
+    status = mcaspCreateChan(pChanHandle, lldCfg->hMcaspDev,
+                             lldCfg->chanMode, lldCfg->mcaspChanParams,
+                             lldCfg->cbFxn, NULL);
+
+    if((status != MCASP_COMPLETED) || (*pChanHandle == NULL))
+    {
+        //IFPRINT(platform_write("mcaspCreateChan for Tx Failed\n"));
+        return (Audk2g_EFAIL);
+    }
+
+    return (Audk2g_EOK);
+}  /* mcasplldChanCreate */
+
 /* Nothing past this point */
index d42ab0ca4c28aecf33f15ad1330c81536f157fab..127bc2f0bfd0195483bffc45e2f01ebd55fb4007 100644 (file)
@@ -65,6 +65,8 @@
 #include "audio_dc_cfg.h"
 #include "edma_cfg.h"
 
+#define NUM_MCASP_PORTS 3
+
 /**
  * \brief McASP configurations for Rx - DIR
  */
 /** Receive clock check control register defult value */
 #define MCASP_DIR_RCLKCHK     (0x00000000)
 
+/** Data structure McASP LLD configuration parameters */
+typedef struct {
+     Mcasp_HwSetupGbl  * mcaspSetupGbl;      // McASP global setup.
+     Mcasp_HwSetupData * mcaspSetupData;    // McASP setup for Tx or Rx
+     Mcasp_ChanParams  * mcaspChanParams;   // LLD channel params
+     uint32_t clkSetupClkRx;
+     uint32_t clkSetupClkTx;
+     Int mcaspPort;
+     Mcasp_chanMode_e chanMode;
+     MCASP_TiomCallback cbFxn;
+     Ptr hMcaspDev;                         // McASP device handle
+     Ptr hMcaspChan;                        // McASP channel handle
+} mcaspLLDconfig;
+
+/** McASP LLD configuration parameters for all input and output interfaces */
+extern mcaspLLDconfig LLDconfigRxDIR;
+extern mcaspLLDconfig LLDconfigRxADC;
+extern mcaspLLDconfig LLDconfigRxADC6ch;
+extern mcaspLLDconfig LLDconfigRxADCStereo;
+extern mcaspLLDconfig LLDconfigRxHDMIStereo;
+extern mcaspLLDconfig LLDconfigRxHDMI;
+extern mcaspLLDconfig LLDconfigTxDAC;
+extern mcaspLLDconfig LLDconfigTxDACSlave;
+extern mcaspLLDconfig LLDconfigTxDACStereo;
+extern mcaspLLDconfig LLDconfigTxDACStereoSlave;
+extern mcaspLLDconfig LLDconfigTxDAC12ch;
+extern mcaspLLDconfig LLDconfigTxDAC16ch;
+
 /**
  *  \brief   Configures McASP module and creates the channel
  *           for audio Tx and Rx
@@ -124,5 +154,6 @@ Audk2g_STATUS mcaspRxCreate(void);
 Audk2g_STATUS mcaspRxReset(void);
 Audk2g_STATUS mcaspRecfgWordWidth(Ptr hMcaspChan, uint16_t wordWidth);
 int mcaspCheckOverUnderRun(Ptr mcaspChanHandle);
+Audk2g_STATUS mcasplldChanCreate(mcaspLLDconfig *lldCfg, Ptr *pChanHandle);
 
 #endif /* _MCASP_CONFIG_H_ */
index d76dd468b44a45009e00e5baec0101641d922d32..706ebc467a1fb6ad183947b3133c9e8acb5cd882 100644 (file)
@@ -71,7 +71,7 @@ All rights reserved.
 #include "evmc66x_gpio.h"  // in "${PDK_INSTALL_PATH}/ti/addon/audk2g/include"
 
 #include "dbgBenchmark.h" // PCM high-sampling rate + SRC + CAR benchmarking
-
+#include "mcasp_cfg.h"
 
 // -----------------------------------------------------------------------------
 // Local function declarations
@@ -252,33 +252,43 @@ static inline void dacSoftUnMute (void) {
 // -----------------------------------------------------------------------------
 // McASP Input Configuration Definitions
 
-static const MCASP_ConfigRcv rxConfigDIR =
+static const MCASP_ConfigRcv rxConfigDIR =    // This is used for both DIR and HDMI?? Yes. Same digital format.
 {
-    MCASP_RMASK_OF(0xFFFFFFFF),
-    MCASP_RFMT_RMK(
-        MCASP_RFMT_RDATDLY_1BIT,
-        MCASP_RFMT_RRVRS_MSBFIRST,
-        MCASP_RFMT_RPAD_RPBIT,
-        MCASP_RFMT_RPBIT_OF(0),
-        MCASP_RFMT_RSSZ_32BITS,
-        MCASP_RFMT_RBUSEL_DAT,
-        MCASP_RFMT_RROT_NONE),
-    MCASP_AFSRCTL_RMK(
-        MCASP_AFSRCTL_RMOD_OF(2),
-        MCASP_AFSRCTL_FRWID_WORD,
-        MCASP_AFSRCTL_FSRM_EXTERNAL,
-        MCASP_AFSRCTL_FSRP_ACTIVELOW),
-    MCASP_ACLKRCTL_RMK(
-        MCASP_ACLKRCTL_CLKRP_RISING,
-        MCASP_ACLKRCTL_CLKRM_EXTERNAL,
-        MCASP_ACLKRCTL_CLKRDIV_DEFAULT),
-    MCASP_AHCLKRCTL_RMK(
-        MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,
-        MCASP_AHCLKRCTL_HCLKRP_RISING,
-        MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
-    MCASP_RTDM_OF(3),
-    MCASP_RINTCTL_DEFAULT,
-    MCASP_RCLKCHK_DEFAULT
+    // The receive format unit bit mask register (RMASK) determines which bits 
+    // of the received data are masked off and padded with a known value before 
+    // being read by the CPU or DMA.
+    MCASP_RMASK_OF(0xFFFFFFFF),     // Don't mask any bits. 0).??
+    // The receive bit stream format register (RFMT) configures the receive data format. 
+    MCASP_RFMT_RMK(      // 0x0001C0F0
+        MCASP_RFMT_RDATDLY_1BIT,    // 17-16: Receive bit delay. Standard I2S configuraiton. MSB first, 1 bit delay.
+        MCASP_RFMT_RRVRS_MSBFIRST,  // 15:    Receive serial bitstream order.
+        MCASP_RFMT_RPAD_RPBIT,      // 14-13: Pad value for extra bits in slot not belonging to the word. N/A because RMASK is 0xFFFFFFFF and no bits need padding.
+        MCASP_RFMT_RPBIT_OF(0),     // 12-8:  RPBIT value determines which bit is used to pad the extra bits. This field only applies when RPAD = 2h. N/A same reason as above.
+        MCASP_RFMT_RSSZ_32BITS,     // 7-4:   Receive slot size. Value is 15.
+        MCASP_RFMT_RBUSEL_DAT,      // 3:     Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port.
+        MCASP_RFMT_RROT_NONE),      // 2-0:   Right-rotation value for receive rotate right format unit.
+    // The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR).
+    MCASP_AFSRCTL_RMK(   // 0x00000111
+        MCASP_AFSRCTL_RMOD_OF(2),   // 15-7:  Receive frame sync mode select bits. 2 - 2-slot TDM (I2S mode)
+        MCASP_AFSRCTL_FRWID_WORD,   // 4:     Receive frame sync width. 1 - Single word
+        MCASP_AFSRCTL_FSRM_EXTERNAL,   // 1:  Receive frame sync generation select bit. 0 - Externally-generated receive frame sync
+        MCASP_AFSRCTL_FSRP_ACTIVELOW), // 0:  Receive frame sync polarity select bit. 1 - A falling edge indicates the beginning of a frame.
+    // The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator.
+    MCASP_ACLKRCTL_RMK(  // 0x00000080
+        MCASP_ACLKRCTL_CLKRP_RISING,     // 7: Receive bitstream clock polarity select bit. 1 - rising edge. Different from PDK 1.0.1 platform audio test (falling edge)??
+        MCASP_ACLKRCTL_CLKRM_EXTERNAL,   // 5: Receive bit clock source bit.
+        MCASP_ACLKRCTL_CLKRDIV_DEFAULT), // 4-0: Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR
+    // The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator.
+    MCASP_AHCLKRCTL_RMK( // 0x00000000
+        MCASP_AHCLKRCTL_HCLKRM_EXTERNAL,   // 15:   Receive high-frequency clock source bit.
+        MCASP_AHCLKRCTL_HCLKRP_RISING,     // 14:   Receive bitstream high-frequency clock polarity select bit. 0 - Rising edge.
+        MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT), // 11-0: Receive high-frequency clock divide ratio bits. 0 - Divide by 1.
+    // The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active
+    MCASP_RTDM_OF(3),      // 0x00000003: time slots 0 and 1 are active
+    // The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT).
+    MCASP_RINTCTL_DEFAULT, // 0x00000000
+    // The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit.
+    MCASP_RCLKCHK_DEFAULT  // 0x00000000
 };
 
 static const MCASP_ConfigRcv rxConfigADC =
@@ -295,14 +305,14 @@ static const MCASP_ConfigRcv rxConfigADC =
     MCASP_AFSRCTL_RMK(
         MCASP_AFSRCTL_RMOD_OF(2),
         MCASP_AFSRCTL_FRWID_WORD,
-        MCASP_AFSRCTL_FSRM_INTERNAL,
-               MCASP_AFSRCTL_FSRP_ACTIVEHIGH),
+        MCASP_AFSRCTL_FSRM_INTERNAL,        // internal
+               MCASP_AFSRCTL_FSRP_ACTIVEHIGH),     // active high
     MCASP_ACLKRCTL_RMK(
         MCASP_ACLKRCTL_CLKRP_RISING,
-        MCASP_ACLKRCTL_CLKRM_INTERNAL,
-               MCASP_ACLKXCTL_CLKXDIV_OF(7)),
+        MCASP_ACLKRCTL_CLKRM_INTERNAL,      //
+               MCASP_ACLKXCTL_CLKXDIV_OF(7)),      //
     MCASP_AHCLKRCTL_RMK(
-        MCASP_AHCLKRCTL_HCLKRM_INTERNAL,
+        MCASP_AHCLKRCTL_HCLKRM_INTERNAL,    //
         MCASP_AHCLKRCTL_HCLKRP_RISING,
                MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT),
     MCASP_RTDM_OF(3),
@@ -548,13 +558,14 @@ const SAP_D10_Rx_Params SAP_D10_RX_HDMI_STEREO =
     sizeof (SAP_D10_Rx_Params),                 // size
     "SAP",                                      // name
     MCASP_DEV0,                                 // moduleNum --> mcasp #
-    (Void *)&rxConfigDIR,                       // pConfig
-    4,                                         // wordSize (unused)
+    //(Void *)&rxConfigDIR,                     // pConfig
+    (Void *)&LLDconfigRxHDMIStereo,             // pConfig
+    4,                                          // wordSize (unused)
     -1,                                         // precision (unused)
     D10_sapControl,                             // control
-    0x00001000,                                // pinMask
+    0x00001000,                                 // pinMask
     (D10_MODE_HDMI << D10_MODE_SHIFT) |
-    (D10_MCLK_HDMI << D10_MCLK_SHIFT),           // mode
+    (D10_MCLK_HDMI << D10_MCLK_SHIFT),          // mode
     0,0                                         // unused[2]
 };
 
@@ -563,7 +574,8 @@ const SAP_D10_Rx_Params SAP_D10_RX_HDMI =
     sizeof (SAP_D10_Rx_Params),                 // size
     "SAP",                                      // name
     MCASP_DEV0,                                 // moduleNum --> mcasp #
-    (Void *)&rxConfigDIR,                       // pConfig
+//    (Void *)&rxConfigDIR,                       // pConfig
+    (Void *)&LLDconfigRxHDMI,
      4,                                         // wordSize (unused)
     -1,                                         // precision (unused)
     D10_sapControl,                             // control
@@ -581,7 +593,8 @@ const SAP_D10_Tx_Params SAP_D10_TX_DAC =
     sizeof (SAP_D10_Tx_Params),                 // size
     "SAP",                                      // name
     MCASP_DEV0,                                 // moduleNum --> mcasp #
-    (Void *)&txConfigDAC,                       // pConfig
+    //(Void *)&txConfigDAC,                       // pConfig
+    (Void *)&LLDconfigTxDAC,
     4,                                          // wordSize (in bytes)
     24,                                         // precision (in bits)
     D10_sapControl,                             // control
@@ -805,8 +818,6 @@ static inline XDAS_Int32 initD10 (DEV2_Handle device)
 // speed clocks (DIR/HDMI) or the internal AUXCLK (Audio_OSC). This is divided down
 // output via ACLKX0 which is connected to the high speed input
 // of TX0 (DAC) and TX2 (DIT).
-#define AUDK2G_AUDIO_CLK_SRC_OSC (AUDK2G_AUDIO_CLK_SRC_I2S+1)  //temporary, to add AUDK2G_AUDIO_CLK_SRC_OSC to audk2g_audio.h
-
 static XDAS_Int32 clockMuxTx (int sel, int force)
 {
        Audk2g_STATUS status = 0;
@@ -1217,9 +1228,18 @@ unsigned int HDMIGpioGetState (void) {
        return(audk2g_gpioReadInput(AUDK2G_GPIO_PORT_0, AUDK2G_AUDIO_HSR_HMINTz_GPIO));
 }
 
-XDAS_Int32 D10_init()
+void setD10ClkMux(UInt16 mode)
+{
+    int sel = (mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT;
+
+    // select appropriate master clock
+    clockMuxTx (sel, 0);
+}
+
+XDAS_Int32 D10_init(void *pD10Params)
 {
     XDAS_Int32 result = 0;
+    SAP_D10_Rx_Params *pD10RxParams;
 
     // perform one time hardware initialization
     if (!initDone) {
@@ -1230,7 +1250,10 @@ XDAS_Int32 D10_init()
         initDone = 1;
     }
 
-    return 0;
+    pD10RxParams = (SAP_D10_Rx_Params *)pD10Params;
+    setD10ClkMux(pD10RxParams->d10rx.mode);
+
+    return result;
 }
 
 XDAS_Int32 D10_RxControl(const void *pD10RxParams,
index 355e987d43c597b181e3eae600b6d9ba08f5bae2..cdf9383e2674da93c325ec5de9df207086665704 100644 (file)
@@ -80,6 +80,8 @@ All rights reserved.
 #define D10_MODE_STD    0
 #define D10_MODE_HDMI   1
 
+#define AUDK2G_AUDIO_CLK_SRC_OSC (AUDK2G_AUDIO_CLK_SRC_I2S+1)  //temporary, to add AUDK2G_AUDIO_CLK_SRC_OSC to audk2g_audio.h
+
 //
 // Device parameter data types, recieve
 //
index e3fc0751d09941eb3f3c3b0a28664f87d745ebf8..0e65ea2673842506c11d1e74d60fd56a6d7b2d30 100644 (file)
@@ -236,7 +236,7 @@ Int decDecodeFsm(
                             pDec->decodeAckDelayed = FALSE;
 
                             // Need to prepare and send INFO to decoder immediately.
-                            // Becuase INPUT_DATA message is already received, 
+                            // Because INPUT_DATA message is already received,
                             // we're just spoofing the message with INPDATA to 
                             // run the FSM one more time. 
                             decMsg |= DEC_MSGMSK_INPDATA;
index 48af2d0ae107d09f9149c66ae34a3ab813df0458..680dd79bd303c102926d242b625954e930b7c1c0 100644 (file)
@@ -383,6 +383,7 @@ Void taskAsipFxnInit(
 {
     PAF_ASIT_Config *pAsitCfg;          // ASIT configuration pointer
     PAF_AST_Config *pAstCfg;            // AST Common (shared) configuration pointer
+    PAF_AST_IoInp *pInp;            /* Input I/O components */
     AspMsgMaster_Handle hAspMsgMaster;  // ASIT message master handle    
     Int as;                             // Audio Stream Number (1, 2, etc.)
     Int z;                              // input/encode/stream/decode/output counter
@@ -644,6 +645,12 @@ Void taskAsipFxnInit(
     Cache_inv(&gPAF_AST_config.xDec[0], DECODEN*sizeof(PAF_AST_Decode), Cache_Type_ALLD, 0);
     Cache_wait();
 
+    pInp = &pAsitCfg->pIoInp[zMI];        // pointer to input I/O components
+    pInp->asipState = ASIT_RESET;
+    pInp->firstTimeInit = TRUE;
+    pInp->numAsitRestart = 0;
+    pInp->hMcaspChan = NULL;
+
 } /* taskAsipFxnInit */
 
 /*
index cff888510a22a72dda6971f39d9543109f7f7d6d..1a6e373fd1d0713fba53a23a8eec861a09eaeab2 100644 (file)
@@ -192,6 +192,14 @@ enum {
     ASIP_ERR_ABORT
 };
 
+
+enum {
+    ASIT_RESET,
+    ASIT_SOURCE_DETECTION,
+    ASIT_PCM_TRANSITION,
+    ASIT_DECODE_PROCESSING
+};
+
 enum {
     ASIT_NO_ERR,
     ASIT_ERR_IOBUFF_INIT,
@@ -246,12 +254,13 @@ typedef struct PAF_AST_InpIO {
     ioPhyHandle_t        hIoPhy;     /* handle to I/O physical layer */
     ioBuffHandle_t       hIoBuff;    /* handle to I/O buffer management */
     ioDataHandle_t       hIoData;    /* handle to I/O data processing */
-    Ptr                  hMcaspChan;
+    Ptr                  hMcaspChan; /* handle to McASP LLD channel */
     const void           *pRxParams; /* pointer to D10 Rx Params */
 
     Int sourceSelect;
     Int sourceProgram;
 
+    Int stride;
     Int       preSyncState;
     Int       numPrimeXfers;
     Int       mcaspXferErr;
index 65278a73dbc908b13ca3812f22da83c7ebea5c7b..1ad72dd65d4a0ca9ed0612347ef7ad730d0ea2bd 100644 (file)
@@ -109,7 +109,8 @@ extern Void taskAsipFxnInit(const PAF_ASIT_Params *pP,const PAF_ASIT_Patchs *pQ)
 
 // avoid including sap_d10.h, which would cause symbol redefinition
 // warning (MCASP_PFUNC_XXX)
-extern XDAS_Int32 D10_init();
+extern XDAS_Int32 D10_init(void * pD10Params);
+
 extern XDAS_Int32 D10_RxControl(const void *pD10RxParams,
                                 XDAS_Int32 code, XDAS_Int32 arg);
 
@@ -123,7 +124,7 @@ void asitIoPhyPrime(PAF_AST_IoInp *pInpIo);
 void asitPhyTransferComplete(PAF_AST_IoInp * pInpIo);
 void asitPhyTransferStart(PAF_AST_IoInp *pInpIo);
 Int asitRecfgPhyXfer(PAF_AST_IoInp *pInp, size_t xferSize);
-Int asitSelectDevices(const PAF_ASIT_Patchs *pQ, PAF_AST_IoInp *pInp);
+Int asitSelectDevices(const PAF_ASIT_Patchs *pQ, PAF_AST_Config *pAstCfg, PAF_AST_IoInp *pInp);
 Int asitUpdateInputStatus(const void *pRxParams, PAF_InpBufStatus *pStatus,
                           PAF_InpBufConfig *pInpBuf);
 
@@ -155,13 +156,6 @@ extern PAF_ASIT_Config gPAF_ASIT_config;
 extern const MdUns iecFrameLength[23];
 extern Ptr hMcaspRxChan;
 
-enum {
-    ASIT_RESET,
-    ASIT_SOURCE_DETECTION,
-    ASIT_PCM_TRANSITION,
-    ASIT_DECODE_PROCESSING
-};
-
 // temp for simulation
 //#define ASIT_ALL_EVENTS (  ASIT_EVTMSK_INPDATA \
 //                         + ASIT_EVTMSK_INFOACK \
@@ -257,9 +251,6 @@ Int inputReadyForProcessing;
     asipLoopCount1 = 0;
     asipLoopCount2 = 0;
     asitErr = ASIT_NO_ERR;
-    pInp->asipState = ASIT_RESET;
-    pInp->firstTimeInit = TRUE;
-    pInp->numAsitRestart = 0;
 
     // The events_on flag will be removed if the RESTART state is changed to
     // event-based scheduling instead of polling
@@ -386,7 +377,7 @@ Int asitPrepareProcessing(const PAF_ASIT_Params *pP,
     *asipErrno = 0;
 
     // Select source and initialize physical layer / HW interface
-    *asipErrno = asitSelectDevices(pQ, pInp);
+    *asipErrno = asitSelectDevices(pQ, pAstCfg, pInp);
     if (*asipErrno) {
         TRACE_TERSE2("asitSelectDevices returned asipErrno = 0x%04x at line %d. AS%d",
                      *asipErrno, as+zMS);
@@ -634,7 +625,7 @@ Int asitBypassIoData(PAF_AST_IoInp *pInp)
         ioBuffReadComplete(pInp->hIoBuff, buff2, size2);
     }
 
-    return ASIP_NO_ERR;
+    return ASIT_NO_ERR;
 } /* asitBypassIoData */
 
 
@@ -879,7 +870,8 @@ int asitIoCompsInit(PAF_AST_InpBuf * pInpBuf, PAF_AST_IoInp * pInpIo)
     ioDataParam_t  ioDataCfg;
     ioPhyCtl_t     ioPhyCtl;
 
-    pInpIo->phyXferSize = INPUT_FRAME_SIZE_DEF;
+    //pInpIo->phyXferSize = INPUT_FRAME_SIZE_DEF;
+    pInpIo->phyXferSize = pInpIo->stride * NUM_CYCLE_PER_FRAME_DEF * WORD_SIZE_BITSTREAM;
 
     if(pInpIo->firstTimeInit) {
         TRACE_VERBOSE0("Initialize I/O BUFF and I/O PHY.");
@@ -932,7 +924,7 @@ int asitIoCompsInit(PAF_AST_InpBuf * pInpBuf, PAF_AST_IoInp * pInpIo)
         ioPhyCtl.code = IOPHY_CTL_FRAME_SIZE;
         ioPhyCtl.params.xferFrameSize = pInpIo->phyXferSize;
         ioPhyControl(pInpIo->hIoPhy, &ioPhyCtl);
-
+#if 0
         // If previous stream before reset was PCM, reconfigure McASP LLD to receive 16-bit packed bits
         if(!pInpIo->swapData) {
             Int mcaspErr;
@@ -945,7 +937,7 @@ int asitIoCompsInit(PAF_AST_InpBuf * pInpBuf, PAF_AST_IoInp * pInpIo)
             pInpIo->swapData = TRUE;
             TRACE_VERBOSE0("Reconfigure McASP word length and start swapping data.");
         }
-
+#endif
         // Start PHY transfer
         TRACE_VERBOSE0("Start I/O PHY transfer.");
         asitPhyTransferStart(pInpIo);
@@ -959,7 +951,7 @@ int asitIoCompsInit(PAF_AST_InpBuf * pInpBuf, PAF_AST_IoInp * pInpIo)
  *====================================================================================*/
 void asitProcInit(PAF_AST_IoInp  *pInp, asipDecProc_t *pDec)
 {
-    pInp->swapData = TRUE;
+//    pInp->swapData = TRUE;
     pInp->pcmSwitchHangOver = INPUT_SWITCH_HANGOVER;
     pDec->initDone = FALSE;
     pInp->numFrameReceived = 0;
@@ -991,6 +983,7 @@ void asitPhyTransferComplete(PAF_AST_IoInp * pInpIo)
     ioPhyXferComplete(pInpIo->hIoPhy, pInpIo->swapData);
 } /* asitPhyTransferComplete */
 
+#if 0
 Int asitRecfgPhyXfer(PAF_AST_IoInp *pInp, size_t xferSize)
 {
     ioPhyCtl_t ioPhyCtl;
@@ -1016,6 +1009,7 @@ Int asitRecfgPhyXfer(PAF_AST_IoInp *pInp, size_t xferSize)
     return ASIT_NO_ERR;
 
 } /* asitRecfgPhyXfer */
+#endif
 
 /*======================================================================================
  *  McASP LLD call back function
@@ -1043,14 +1037,16 @@ int asipCheckMcaspRxOverrun(Ptr mcaspChanHandle)
     return (mcaspErrStat.isRcvOvrRunOrTxUndRunErr);
 }
 
+#if 0
 /*======================================================================================
  *  This function restarts McASP LLD channel for input
  *====================================================================================*/
-void asipMcaspRxRestart(void)
+void asipMcaspRxRestart(PAF_AST_IoInp *pInpIo)
 {
     mcaspRxReset();
     mcaspRxCreate();
 }
+#endif
 
 /*======================================================================================
  *  This function starts an I/O PHY transfer
@@ -1063,7 +1059,8 @@ void asitPhyTransferStart(PAF_AST_IoInp *pInpIo)
 #ifdef ASIP_DEBUG
         pInpIo->numInputOverrun++;
 #endif
-        asipMcaspRxRestart();
+        //asipMcaspRxRestart(pInpIo);
+        System_abort("\nMcASP for input overruns! %d!\n");
     }
     else {
         ioPhyErr = ioPhyXferSubmit(pInpIo->hIoPhy);
@@ -1091,50 +1088,69 @@ extern void McaspDevice_init(void);
 /*======================================================================================
  *  This function initializes HW interface and selects the right device for input
  *====================================================================================*/
-Int asitSelectDevices(const PAF_ASIT_Patchs *pQ, PAF_AST_IoInp *pInp)
+Int asitSelectDevices(const PAF_ASIT_Patchs *pQ, PAF_AST_Config *pAstCfg, PAF_AST_IoInp *pInp)
 {
     Audk2g_STATUS status;
+    mcaspLLDconfig *lldCfg;
+    Ptr mcaspChanHandle;
+    Int zMD, interface;
 
-    //more configuration is needed to abstract out D10
+    zMD = pAstCfg->masterDec;
+
+    interface = pAstCfg->xInp[zMD].inpBufStatus.sioSelect; // obtain SIO select for input
+
+    if (interface <= 0) {
+        pInp->pRxParams = NULL;
+
+        return ASIT_NO_ERR;
+    }
+
+    // Initialize D10
     if(!d10Initialized) {
+        void * pD10Params = (void *)pQ->devinp->x[interface];
+
         /* Initialize McASP HW details */
         McaspDevice_init();
 
-        D10_init();
+        D10_init(pD10Params);
 
-#ifdef INPUT_SPDIF
-        // Input is DIR
-        status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_DIR);
-#else
-        // Input is HDMI
-        status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_I2S);
-#endif
-        if(status != Audk2g_EOK) {
-            Log_info0("audk2g_AudioSelectClkSrc Failed!\n");
-            return ASIT_ERR_D10_CFG;
-        }
-        audk2g_delay(50000); // Without delay between these 2 calls system aborts.
+        d10Initialized = 1;
+    }
 
-        /* Initialize McASP module */
-        status = mcaspAudioConfig(); //defined in newio\fw\mcasp_cfg.c
+    /* Get the McASP LLD channel for this interface. Create one if not yet created. */
+    lldCfg = (mcaspLLDconfig *)pQ->devinp->x[interface]->sio.pConfig;
+    if(lldCfg->hMcaspChan == NULL) {
+        mcaspChanHandle = NULL;
+        status = mcasplldChanCreate(lldCfg, &mcaspChanHandle);
         if(status != Audk2g_EOK) {
-            Log_info0("McASP Configuration Failed!\n");
+            Log_info0("McASP channel creation failed!\n");
             return ASIT_ERR_MCASP_CFG;
         }
 
-        pInp->hMcaspChan = hMcaspRxChan;
-        d10Initialized = 1;
+        lldCfg->hMcaspChan = mcaspChanHandle;
     }
 
-    /////////////// TODO: HW interface selection and initialization //////////////
-    ////// to add what PAF_ASIT_selectDevices() does /////////
-#ifdef IO_HW_INTERFACE
-    pInp->pRxParams = pQ->devinp->x[IO_HW_INTERFACE];
-#else
-    pInp->pRxParams = NULL;
-#endif
+    pInp->pRxParams = pQ->devinp->x[interface];
+    pInp->hMcaspChan = lldCfg->hMcaspChan;
+    pInp->stride     = lldCfg->mcaspChanParams->noOfSerRequested * 2;  // 2 for stereo
 
-    return 0;
+    /* Set flag to swap HDMI data if it is 4xI2S and word length is 16 */
+    if(   (lldCfg->mcaspChanParams->wordWidth == Mcasp_WordLength_16)
+        &&(lldCfg->mcaspChanParams->noOfSerRequested == 4)
+      ) {
+        Int mcaspErr;
+        mcaspErr = mcaspRecfgWordWidth(pInp->hMcaspChan, Mcasp_WordLength_16);
+        if(mcaspErr != Audk2g_EOK) {
+            return ASIT_ERR_MCASP_CFG;
+        }
+
+        pInp->swapData = TRUE;
+    }
+    else {
+        pInp->swapData = FALSE;
+    }
+
+    return ASIT_NO_ERR;
 }  /* asitSelectDevices */
 
 /*======================================================================================
@@ -1407,7 +1423,7 @@ Int asitUpdateIoComps(const PAF_ASIT_Params *pP, PAF_AST_Config *pAstCfg,
     // Decide frame length for I/O DATA and I/O PHY
     if(autoDetStatus->syncState == IODATA_SYNC_PCM) {
         // For PCM, I/O frame length is decode frame length multiplied by stride
-        ioFrameLength = decFrameLength * INPUT_STRIDE;
+        ioFrameLength = decFrameLength * pInp->stride;
 
         pBufConfig->sizeofElement = WORD_SIZE_PCM;
         pBufConfig->frameLength   = pBufConfig->lengthofData = ioFrameLength;
@@ -1454,7 +1470,7 @@ Int asitUpdateIoComps(const PAF_ASIT_Params *pP, PAF_AST_Config *pAstCfg,
         pInp->phyXferSize = ioFrameLength*WORD_SIZE_BITSTREAM;
     }
 
-    pBufConfig->stride = INPUT_STRIDE;   // common for PCM and bitstream
+    pBufConfig->stride = pInp->stride;   // common for PCM and bitstream
 
     // Configure I/O PHY transfer size
     ioPhyCtl.code = IOPHY_CTL_FRAME_SIZE;
index 008334b83c654a432d9ddeb78c39cd0daf17d1e1..9c7463b776211ce43612d71aa6397eac16779ed7 100644 (file)
@@ -144,6 +144,7 @@ Void taskAsopFxnInit(
 {
     PAF_ASOT_Config *pAsotCfg;      /* ASOT configuration pointer */
     PAF_AST_Config *pAstCfg;        /* Common (shared) configuration pointer */
+    PAF_AST_IoOut *pOut;
     Int as;                         /* Audio Stream Number (1, 2, etc.) */
     Int z;                          /* input/encode/stream/decode/output counter */
     Int i;                          /* phase */
@@ -244,6 +245,9 @@ Void taskAsopFxnInit(
             HEAP_INTERNAL, HEAP_INTERNAL1, HEAP_EXTERNAL,
             HEAP_INTERNAL1_SHM, HEAP_EXTERNAL_SHM, HEAP_EXTERNAL_NONCACHED_SHM);
     }
+
+    pOut = &pAsotCfg->pIoOut[zMS];
+    pOut->hMcaspChan = NULL;
 } /* taskAsopFxnInit */
 
 #if 0
index a936b0ecbf8f74933651a696c5ff3c6dfbf32634..c70438c9c7860528d7599f8726f7054bdb733e1d 100644 (file)
@@ -67,13 +67,25 @@ extern Int d10Initialized;
 // FL, New IO: this function is currently a stub
 // FL, New IO: need to McASP/EDMA configuration using SAP configuration from Output shortcut
 // Select Output devices
-Int asopSelectDevices(PAF_AST_IoOut *pOut)
+Int asopSelectDevices(void *pConfig, PAF_AST_IoOut *pOut)
 {
     if((pOut->hIoBuff == NULL) || (pOut->hIoPhy == NULL) || (!d10Initialized)) {
         return -1;
     }
 
-    pOut->hMcaspChan = hMcaspTxChan;
+    if(pOut->hMcaspChan == NULL) {
+        Audk2g_STATUS status;
+        mcaspLLDconfig * lldCfg;
+        Ptr mcaspChanHandle;
+
+        lldCfg = (mcaspLLDconfig *)pConfig;
+        status = mcasplldChanCreate(lldCfg, &mcaspChanHandle);
+        if(status != Audk2g_EOK) {
+            return -1;
+        }
+
+        pOut->hMcaspChan = mcaspChanHandle;
+    }
 
     return 0;
 }
@@ -526,7 +538,7 @@ Int asopIoCompsInit(
 
     ioPhyParams.ioBuffHandle    = pOutIo->hIoBuff;
     ioPhyParams.xferFrameSize   = OUTPUT_FRAME_SIZE;
-    ioPhyParams.mcaspChanHandle = hMcaspTxChan;
+    ioPhyParams.mcaspChanHandle = pOutIo->hMcaspChan;
     ioPhyParams.ioBuffOp        = IOPHY_IOBUFFOP_READ;
     if(ioPhyInit(pOutIo->hIoPhy, &ioPhyParams) != IOPHY_NOERR) 
     {
@@ -695,9 +707,10 @@ Void asopPhyTransferStart(
 {
     if(mcaspCheckOverUnderRun(pOut->hMcaspChan)) 
     {
-        mcaspTxReset();
-        mcaspTxCreate();
-        pOut->hMcaspChan = hMcaspTxChan;
+        //mcaspTxReset();
+        //mcaspTxCreate();
+        //pOut->hMcaspChan = hMcaspTxChan;
+        System_abort("\nMcASP for output underruns! %d!\n");
     }
     else 
     {
index 7e33e96cd3f5cbe2626e640085efa0d51dc3e1d2..cbebe02f8d80be5ca02848f599d5547ee959d412 100644 (file)
@@ -47,6 +47,7 @@ All rights reserved.
 
 // Select Output devices
 Int asopSelectDevices(
+    void *pConfig,
     PAF_AST_IoOut *pOut
 );
 
index d5b6c2246d7ae4301bf905911b244e5a8200f042..3515ac05cf05839ee40e2d62e2dd65c17db0daac 100644 (file)
@@ -921,7 +921,7 @@ static Int PAF_ASOT_selectDevices(
     if ((ioPhyInit == TRUE) && (device >= 0))
     {
         // check for valid index into device array
-        if (device >= pQ->devout->n)
+        if (device >= pQ->devout->n)    // DEVOUT_N
         {
             device = 0; // treat as device None
         }
@@ -932,7 +932,7 @@ static Int PAF_ASOT_selectDevices(
             //  FL, New IO: Placeholder function, this will be reorganized moving forward.
             //  FL, New IO: API for single Output.
             //  FL, New IO: Doesn't (re-)configure Output driver.
-            status = asopSelectDevices(&pAsotCfg->pIoOut[zO]);
+            status = asopSelectDevices(pQ->devout->x[device]->sio.pConfig, &pAsotCfg->pIoOut[zO]);
             if (status < 0)
             {
                 pAstCfg->xOut[zO].outBufStatus.sioSelect = 0x80;
index aad3afcbfdf1b636746f314ca8686eae6d50e6fe..0938e75a2efebbd8f6a28f249345fd92e82240bb 100644 (file)
@@ -512,7 +512,7 @@ const IALG_MemRec inpMemTabPrimary[] =
     // SDRAM circular buffer
     // 2 buffers * 256 samples/buffer * 8 words/sample * 3 bytes/word
     {
-        (4 * 60 * 1024) + 2,                                    // size 184320 + 1 16-bit word for EDMA padding
+        (6 * 60 * 1024) + 2,                                    // size 184320 + 1 16-bit word for EDMA padding
         //180 * 1024,                                           // size
         //6 * 60 * 1024,                                        // size
         128,                                                    // alignment
index 504cef8ce70bf33a8c304ffe531125b4377f03f9..2fd92e19968bbc7eb8765b3cc57167ff23be6b54 100644 (file)
@@ -224,19 +224,25 @@ const MdUns iecFrameLength[23] =
 {
     0,
     1536*2,
-    0, 0, 0,
+    0,
+    0,
+    0,
     1152*2,
     0,
     1024*2,
-    0, 0, 0,
+    0,
+    0,
+    0,
     512*2,
     1024*2,
     2048*2,
-    0, 0,
+    0,
+    0,
     15*1024*2, //THD
     1*1024, // DTSHD, actual framelength is adjusted by DTSsubType
     4096*2,
-    0,0,
+    0,
+    0,
     1536*2*4,
     15*1024*2 //THD
 };