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raw | patch | inline | side by side (from parent 1: eccd467)
raw | patch | inline | side by side (from parent 1: eccd467)
author | Jianzhong Xu <a0869574@ti.com> | |
Mon, 26 Mar 2018 15:48:03 +0000 (11:48 -0400) | ||
committer | Jianzhong Xu <a0869574@ti.com> | |
Mon, 26 Mar 2018 15:48:03 +0000 (11:48 -0400) |
index 38a5c7ecf845d7f752754c2119d86e1d47bebf4e..017d655c36f9b6aa1b9d75ce507261b836fd4ddb 100644 (file)
--- a/pasdk/common/dbgCapAf.h
+++ b/pasdk/common/dbgCapAf.h
#define CAP_AF_SOK ( 0 )
#define CAP_AF_INV_CHNUM ( -1 )
-//#define DBG_CAP_AF
+#define DBG_CAP_AF
#ifdef DBG_CAP_AF
// buffer capture parameters
#define CAP_AF_MAX_NUM_FRAME ( 5625 ) //( 100 )
diff --git a/pasdk/test_arm/framework/audioStreamDecodeProc.c b/pasdk/test_arm/framework/audioStreamDecodeProc.c
index c6bc8526428406c5d1c3f876a6043ab083c25957..59d39bd49ebe5ce7c4f784cb6f936a5ec3789a60 100644 (file)
//
pfpBegin(PFP_ID_ASDT_2, pAsdtCfg->taskHandle);
errno = dec->fxns->decode(dec, NULL, &pAstCfg->xDec[z].decodeInStruct, &pAstCfg->xDec[z].decodeOutStruct);
+ //decode is done
pfpEnd(PFP_ID_ASDT_2, PFP_FINISH_MEAS);
if (errno < 0)
{
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/atboot.c b/pasdk/test_dsp/application/itopo/evmk2g/atboot.c
index b20d170c3cccef8db5b2d9b88b604d3b72ce46b5..9c5ae4029212f1e4cb693fafb630736c936282d6 100644 (file)
writeSYSRecreationModeDirect, \
writeSYSChannelConfigurationRequestSurround4_1, \
execPAIOutAnalog, \
- execPAIInHDMI
+ execPAIInHDMIStereo
#else
// Performing PCM high-sampling rate + SRC + CAR benchmarking
// 4XI2S HDMI input for multi-ch PCM
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c b/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c
index c6dba5f10de5b49ff26a3df49eb7988d269aa5f2..ac16b5adfea1fc65b158b96dc24dcc9e25919a87 100644 (file)
extern void asopMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
#endif
-/* McASP HW setup that is common for receive and transmit. It is the same for
- * all of 3 McASP ports. */
-Mcasp_HwSetupGbl mcaspGblSetup = {
- (Uint32)0x0, /* pfunc */
- (Uint32)0x2000001, /* pdir */
- (Uint32)0x0, /* ctl */
- (Uint32)0x0, /* ditCtl */
- (Uint32)0x0, /* dlbMode */
- (Uint32)0x2, /* amute */
- {
- (Uint32)0x0, /* [0] */
- (Uint32)0x0, /* [1] */
- (Uint32)0x0, /* [2] */
- (Uint32)0x0, /* [3] */
- (Uint32)0x0, /* [4] */
- (Uint32)0x0, /* [5] */
- (Uint32)0x0, /* [6] */
- (Uint32)0x0, /* [7] */
- (Uint32)0x0, /* [8] */
- (Uint32)0x0, /* [9] */
- (Uint32)0x0, /* [10] */
- (Uint32)0x0, /* [11] */
- (Uint32)0x0, /* [12] */
- (Uint32)0x0, /* [13] */
- (Uint32)0x0, /* [14] */
- (Uint32)0x0, /* [15] */
- } /* serSetup */
-};
/* McASP HW setup for receive (ADC) */
Mcasp_HwSetupData mcaspRcvSetupADC = {
/* .rmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
- /* .rfmt = */ 0x000180F2, /*
+ /* .rfmt = */ 0x0001C0F0, /*
* 0 bit delay from framesync
* MSB first
* No extra bit padding
/* .rstat = */ 0x000001FF, /* reset any existing status bits */
/* .revtctl = */ 0x00000000, /* DMA request is enabled */
{
- /* .aclkrctl = */ 0x000000A7,
- /* .ahclkrctl = */ 0x0000C000,
+ /* .aclkrctl = */ 0x000000A7, // Receiver samples data on the rising edge of the serial clock
+ // Internal receive clock source from output of programmable bit clock divider
+ // Receive bit clock divide ratio = 8
+ /* .ahclkrctl = */ 0x00008000, // Internal receive high-frequency clock source from output of programmable high clock divider.
+ // Falling edge. AHCLKR is inverted before programmable bit clock divider.
/* .rclkchk = */ 0x00000000
}
};
MCASP_DIR_RSTAT, /* .rstat: 0x000001FF */
MCASP_DIR_REVTCTL, /* .revtctl */
{
- MCASP_DIR_ACLKRCTL, /* .aclkrctl: 0x00000080 */
+ MCASP_DIR_ACLKRCTL, /* .aclkrctl: 0x00000080 */ // Receiver samples data on the rising edge of the serial clock
+ // External receive clock source from ACLKR pin.
+ // Receive bit clock divide ratio = 1
MCASP_DIR_AHCLKRCTL, /* .ahclkrctl: 0x00000000 */
MCASP_DIR_RCLKCHK /* .rclkchk: 0x00000000 */
}
/* .xstat = */ 0x000001FF, /* reset any existing status bits */
/* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
{
- /* .aclkxctl = */ 0X000000E1,
- /* .ahclkxctl = */ 0x00004000 ,
+// /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2
+ /* .aclkxctl = */ 0X000000E7, // Transmit bit clock divide ratio = 8
+ /* .ahclkxctl = */ 0x00004000,
/* .xclkchk = */ 0x00000000
},
};
/* McASP HW setup for transmit (DAC slave) */
Mcasp_HwSetupData mcaspXmtSetupDACSlave = {
/* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
- /* .xfmt = */ 0x000180F6, /*
+ /* .xfmt = */ 0x000180F0, /*
* 0 bit delay from framesync
* MSB first
* No extra bit padding
* Reads from DMA port
* NO rotation
*/
- /* .afsxctl = */ 0x00000112, /* I2S mode - 2 slot TDM
+ /* .afsxctl = */ 0x00000113, /* I2S mode - 2 slot TDM
* Frame sync is one word
* Rising edge is start of frame
* Internally generated frame sync
mcaspRxParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x63; // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
#ifndef INPUT_SPDIF
- mcaspRxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Special case, since for HDMI input - mcasp0 is both Rx & Tx
- mcaspRxParams.mcaspHwSetup.glb.amute = 0x2; // this to ensure one doesn't overwrite the other (rx/tx)
- mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
- mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
+ mcaspRxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Special case, since for HDMI input - mcasp0 is both Rx & Tx
+ mcaspRxParams.mcaspHwSetup.glb.amute = 0x2; // this to ensure one doesn't overwrite the other (rx/tx)
+ mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
+ mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
#else
- mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
- mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
+ mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
+ mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
#endif
/* Set the HW interrupt number */
/** McASP LLD configuration parameters for all input and output interfaces */
mcaspLLDconfig LLDconfigRxDIR = // for SAP_D10_RX_DIR
{
- &mcaspGblSetup,
&mcaspRcvSetupDIR,
&mcaspRxChanParamDIR,
0x23,
- 0x23,
+ 0x63, // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
+ 0x0,
+ 0x2,
CSL_MCASP_2,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxADC = // for SAP_D10_RX_ADC_44100HZ, SAP_D10_RX_ADC_88200HZ
{
- &mcaspGblSetup,
&mcaspRcvSetupADC,
&mcaspRxChanParamADC,
0x23,
- 0x23,
+ 0x63,
+ 0x0,
+ 0x2,
CSL_MCASP_1,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxADC6ch = // for SAP_D10_RX_ADC_6CH_44100HZ, SAP_D10_RX_ADC_6CH_88200HZ
{
- &mcaspGblSetup,
&mcaspRcvSetupADC,
&mcaspRxChanParamADC6ch,
0x23,
- 0x23,
+ 0x63,
+ 0x0,
+ 0x2,
CSL_MCASP_1,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxADCStereo = // for SAP_D10_RX_ADC_STEREO_44100HZ, SAP_D10_RX_ADC_STEREO_88200HZ
{
- &mcaspGblSetup,
&mcaspRcvSetupADC,
&mcaspRxChanParamADCStereo,
0x23,
- 0x23,
+ 0x63,
+ 0x0,
+ 0x2,
CSL_MCASP_1,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxHDMIStereo = // for SAP_D10_RX_HDMI_STEREO
{
- &mcaspGblSetup,
&mcaspRcvSetupDIR,
&mcaspRxChanParamHDMIStereo,
0x23,
0x63,
+ 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
+ 0x2,
CSL_MCASP_0,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxHDMI = // for SAP_D10_RX_HDMI
{
- &mcaspGblSetup,
&mcaspRcvSetupDIR,
&mcaspRxChanParamHDMI,
0x23,
0x63,
+ 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
+ 0x2,
CSL_MCASP_0,
MCASP_INPUT,
asipMcaspCallback,
/*
mcaspLLDconfig LLDconfigTxDIT = // for SAP_D10_TX_DIT
{
- &mcaspGblSetup,
&mcaspXmtSetupDIT,
&mcaspTx0ChanParamDIT,
NULL,
mcaspLLDconfig LLDconfigTxDAC = // for SAP_D10_TX_DAC
{
- &mcaspGblSetup,
- &mcaspXmtSetupDAC,
+ &mcaspXmtSetupDAC,
&mcaspTx0ChanParamDAC,
0x23,
0x63,
+ 0x02000000, // Set Amute pin as output for Tx channel
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDACSlave = // for SAP_D10_TX_DAC_SLAVE
{
- &mcaspGblSetup,
&mcaspXmtSetupDACSlave,
&mcaspTx0ChanParamDAC,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDACStereo = // for SAP_D10_TX_STEREO_DAC
{
- &mcaspGblSetup,
&mcaspXmtSetupDAC,
&mcaspTx0ChanParamDACStereo,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDACStereoSlave = // for SAP_D10_TX_STEREO_DAC_SLAVE
{
- &mcaspGblSetup,
&mcaspXmtSetupDACSlave,
&mcaspTx0ChanParamDACStereo,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDAC12ch = // for SAP_D10_TX_DAC_12CH
{
- &mcaspGblSetup,
&mcaspXmtSetupDAC,
&mcaspTx0ChanParamDAC12ch,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDAC16ch = // for SAP_D10_TX_DAC_16CH
{
- &mcaspGblSetup,
&mcaspXmtSetupDAC,
&mcaspTx0ChanParamDAC16ch,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
int32_t status;
if(mcaspDevHandles[lldCfg->mcaspPort] == NULL) {
- /* Initialize McASP Tx and Rx parameters */
- mcaspParams = Mcasp_PARAMS;
+ /* Initialize McASP parameters */
+ mcaspParams = Mcasp_PARAMS; // Mcasp_PARAMS defined in McASP LLD
- //mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x23; // not used
- //mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x23; // not used
mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = lldCfg->clkSetupClkRx;
mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = lldCfg->clkSetupClkTx;
-
- mcaspParams.mcaspHwSetup.glb.pdir = lldCfg->mcaspSetupGbl->pdir;
- mcaspParams.mcaspHwSetup.glb.amute = lldCfg->mcaspSetupGbl->amute;
+ mcaspParams.mcaspHwSetup.glb.pdir |= lldCfg->pdirAmute;
+ mcaspParams.mcaspHwSetup.glb.amute = lldCfg->amute;
status = mcaspBindDev(&mcaspDevHandles[lldCfg->mcaspPort], lldCfg->mcaspPort, &mcaspParams);
if((status != MCASP_COMPLETED) || (mcaspDevHandles[lldCfg->mcaspPort] == NULL)) {
- //IFPRINT(platform_write("mcaspBindDev for Tx Failed\n"));
return (Audk2g_EFAIL);
}
}
lldCfg->mcaspChanParams->edmaHandle = hEdma1;
}
- /* Create McASP channel for Tx */
+ /* Create McASP channel */
*pChanHandle = NULL;
status = mcaspCreateChan(pChanHandle, lldCfg->hMcaspDev,
lldCfg->chanMode, lldCfg->mcaspChanParams,
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.h b/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.h
index 127bc2f0bfd0195483bffc45e2f01ebd55fb4007..fb9d8f684477b73434489edbab6672c529040e83 100644 (file)
/** Data structure McASP LLD configuration parameters */
typedef struct {
- Mcasp_HwSetupGbl * mcaspSetupGbl; // McASP global setup.
Mcasp_HwSetupData * mcaspSetupData; // McASP setup for Tx or Rx
Mcasp_ChanParams * mcaspChanParams; // LLD channel params
- uint32_t clkSetupClkRx;
- uint32_t clkSetupClkTx;
- Int mcaspPort;
- Mcasp_chanMode_e chanMode;
- MCASP_TiomCallback cbFxn;
+ uint32_t clkSetupClkRx; // set ACLKRCTL during mcaspBindDev
+ uint32_t clkSetupClkTx; // set ACLKXCTL during mcaspBindDev
+ uint32_t pdirAmute; // set the AMUTE bit in Pin Direction Register (PDIR)
+ uint32_t amute; // set the Audio Mute Control Register (AMUTE)
+ Int mcaspPort; // McASP port number
+ Mcasp_chanMode_e chanMode; // MCASP_INPUT or MCASP_OUTPUT
+ MCASP_TiomCallback cbFxn; // call back function for transfer completion
Ptr hMcaspDev; // McASP device handle
Ptr hMcaspChan; // McASP channel handle
} mcaspLLDconfig;
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/sap_d10.c b/pasdk/test_dsp/application/itopo/evmk2g/sap_d10.c
index 706ebc467a1fb6ad183947b3133c9e8acb5cd882..a23cbee9dbb4b0514d90f45227358e0f95ec3c2d 100644 (file)
// -----------------------------------------------------------------------------
// McASP Input Configuration Definitions
-static const MCASP_ConfigRcv rxConfigDIR = // This is used for both DIR and HDMI?? Yes. Same digital format.
+const MCASP_ConfigRcv rxConfigDIR = // This is used for both DIR and HDMI?? Yes. Same digital format.
{
// The receive format unit bit mask register (RMASK) determines which bits
// of the received data are masked off and padded with a known value before
MCASP_RCLKCHK_DEFAULT // 0x00000000
};
-static const MCASP_ConfigRcv rxConfigADC =
+const MCASP_ConfigRcv rxConfigADC =
{
MCASP_RMASK_OF(0xFFFFFFFF),
MCASP_RFMT_RMK(
// -----------------------------------------------------------------------------
// McASP Output Configuration Definitions
-static const MCASP_ConfigXmt txConfigDAC =
+const MCASP_ConfigXmt txConfigDAC =
{
MCASP_XMASK_OF(0xFFFFFFFF),
MCASP_XFMT_RMK(
MCASP_XCLKCHK_DEFAULT
};
-static const MCASP_ConfigXmt txConfigDACSlave =
+const MCASP_ConfigXmt txConfigDACSlave =
{
MCASP_XMASK_OF(0xFFFFFFFF),
MCASP_XFMT_RMK(
sizeof (SAP_D10_Rx_Params), // size
"SAP", // name
MCASP_DEV2, // moduleNum --> mcasp #
- (Void *)&rxConfigDIR, // pConfig
+ //(Void *)&rxConfigDIR, // pConfig
+ (Void *)&LLDconfigRxDIR,
4, // wordSize (unused)
24, // precision (unused)
D10_sapControl, // control
sizeof (SAP_D10_Rx_Params), // size
"SAP", // name
MCASP_DEV1, // moduleNum --> mcasp #
- (Void *)&rxConfigADC, // pConfig
+ //(Void *)&rxConfigADC, // pConfig
+ (Void *)&LLDconfigRxADC,
4, // wordSize (unused)
24, // precision (unused)
D10_sapControl, // control
sizeof (SAP_D10_Rx_Params), // size
"SAP", // name
MCASP_DEV1, // moduleNum --> mcasp #
- (Void *)&rxConfigADC, // pConfig
+ //(Void *)&rxConfigADC, // pConfig
+ (Void *)&LLDconfigRxADC6ch,
-1, // wordSize (unused)
-1, // precision (unused)
D10_sapControl, // control
sizeof (SAP_D10_Rx_Params), // size
"SAP", // name
MCASP_DEV1, // moduleNum --> mcasp #
- (Void *)&rxConfigADC, // pConfig
+ //(Void *)&rxConfigADC, // pConfig
+ (Void *)&LLDconfigRxADCStereo,
-1, // wordSize (unused)
-1, // precision (unused)
D10_sapControl, // control
(D10_MCLK_HDMI << D10_MCLK_SHIFT), // mode
0,0,0 // unused[3]
};
-
+/* - SAP_D10_TX_STEREO_DAC is not used
const SAP_D10_Tx_Params SAP_D10_TX_STEREO_DAC =
{
sizeof (SAP_D10_Tx_Params), // size
0, // mode
0,0,0 // unused[3]
};
-
+*/
const SAP_D10_Tx_Params SAP_D10_TX_DIT =
{
sizeof (SAP_D10_Tx_Params), // size
sizeof (SAP_D10_Tx_Params), // size
"SAP", // name
MCASP_DEV0, // moduleNum --> mcasp #
- (Void *)&txConfigDACSlave, // pConfig
+ //(Void *)&txConfigDACSlave, // pConfig
+ (Void *)&LLDconfigTxDACSlave,
4, // wordSize (in bytes)
24, // precision (in bits)
D10_sapControl, // control
sizeof (SAP_D10_Tx_Params), // size
"SAP", // name
MCASP_DEV0, // moduleNum --> mcasp #
- (Void *)&txConfigDAC, // pConfig
+ //(Void *)&txConfigDAC, // pConfig
+ (Void *)&LLDconfigTxDACStereoSlave,
4, // wordSize (in bytes)
24, // precision (in bits)
D10_sapControl, // control
sizeof (SAP_D10_Tx_Params), // size
"SAP", // name
MCASP_DEV0, // moduleNum --> mcasp #
- (Void *)&txConfigDAC, // pConfig
+ //(Void *)&txConfigDAC, // pConfig
+ (Void *)&LLDconfigTxDAC12ch,
4, // wordSize (in bytes)
24, // precision (in bits)
D10_sapControl, // control
sizeof (SAP_D10_Tx_Params), // size
"SAP", // name
MCASP_DEV0, // moduleNum --> mcasp #
- (Void *)&txConfigDAC, // pConfig
+ //(Void *)&txConfigDAC, // pConfig
+ (Void *)&LLDconfigTxDAC16ch,
4, // wordSize (in bytes)
24, // precision (in bits)
D10_sapControl, // control
index 421477fae02357c2c722b0ffb9c6ee7b2095b14b..e96055ca8978e1bd4fb0d4e0a9ae7da32bbc881f 100644 (file)
#define DEC_MINSAMGEN PCM_MINSAMGEN
#define DEC_MAXSAMGEN PCM_MAXSAMGEN
#endif
-
+#if 0
Int
PAF_DEC_computeFrameLength(
Int decIdx,
return m;
} /* PAF_DEC_computeFrameLength */
+#endif
//
// Audio Stream Task / Decode Processing - Input Status Update
diff --git a/pasdk/test_dsp/framework/audioStreamOutDec.c b/pasdk/test_dsp/framework/audioStreamOutDec.c
index cbab851de909de9f6ab7f1015d584a56538eef6d..eba3872e82601f371f590b5f479413edc530efdb 100644 (file)
// debug
cbLog(pCbCtl, z, 1, "asopDecOutProcStream:cbReadAf()");
-#if 0 // debug, capture audio frame
+#if 1 // debug, capture audio frame
if (capAfWrite(pAfRd, PAF_LEFT) != CAP_AF_SOK)
+// if (capAfWrite(pAfRd, PAF_RIGHT) != CAP_AF_SOK)
{
Log_info0("asopDecOutProcStream:capAfWrite() error");
}
index 27a67d12af0dadb25f1a018bf7ed4b88ef882bd5..e43bcfb14760b4e3862d6d462a438a08a38b1e55 100644 (file)
//#define IO_LOOPBACK_TEST // define this to run a DSP-only standalone loopback test without PASDK framework
//#define PCM_LOOPBACK_TEST // define this to run DSP-only PCM loopback test in PASDK framework
-#define INPUT_HDMI_4xI2S // HDMI, 4 Rx serializers
-//#define INPUT_HDMI_STEREO // HDMI, 1 Rx serializer
+//#define INPUT_HDMI_4xI2S // HDMI, 4 Rx serializers
+#define INPUT_HDMI_STEREO // HDMI, 1 Rx serializer
//#define INPUT_SPDIF // S/PDIF, 1 Rx serializer
//#define INPUT_PCM_ONLY // debugging, input fixed to PCM