Pyalpha tools for performance audio demo in PRSDK.
[processor-sdk/performance-audio-tools.git] / alpha / src_a.h
1 /*
2 *  Copyright {C} 2016 Texas Instruments Incorporated - http://www.ti.com/ 
3 *  ALL RIGHTS RESERVED 
4 *
5 *  Redistribution and use in source and binary forms, with or without
6 *  modification, are permitted provided that the following conditions
7 *  are met:
8 *
9 *    Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 *
12 *    Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the
15 *    distribution.
16 *
17 *    Neither the name of Texas Instruments Incorporated nor the names of
18 *    its contributors may be used to endorse or promote products derived
19 *    from this software without specific prior written permission.
20 *
21 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
22 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
35 //
36 // Synchronous Rate Conversion alpha codes
37 //
39 #ifndef _SRC_A
40 #define _SRC_A
42 #include <paftyp_a.h>
43 #include <acpbeta.h>
45 #define  readSRCMode 0xc200+STD_BETA_SRC,0x0400
46 #define writeSRCModeDisable 0xca00+STD_BETA_SRC,0x0400
47 #define writeSRCModeEnable 0xca00+STD_BETA_SRC,0x0401
49 #define  readSRCRateRequest 0xc200+STD_BETA_SRC,0x0500
50 #define writeSRCRateRequestFull 0xca00+STD_BETA_SRC,0x0500
51 #define writeSRCRateRequestHalf 0xca00+STD_BETA_SRC,0x0501
52 #define writeSRCRateRequestQuarter 0xca00+STD_BETA_SRC,0x0502
53 #define writeSRCRateRequestDouble 0xca00+STD_BETA_SRC,0x0503
54 #define writeSRCRateRequestQuadruple 0xca00+STD_BETA_SRC,0x0504
55 #define writeSRCRateRequestMax192 0xca00+STD_BETA_SRC,0x0580
56 #define writeSRCRateRequestMin32 0xca00+STD_BETA_SRC,0x0580
57 #define writeSRCRateRequestMax96 0xca00+STD_BETA_SRC,0x0581
58 #define writeSRCRateRequestMax48 0xca00+STD_BETA_SRC,0x0582
59 #define writeSRCRateRequestMin64 0xca00+STD_BETA_SRC,0x0583
60 #define writeSRCRateRequestMin128 0xca00+STD_BETA_SRC,0x0584
62 #define  readSRCRateStream 0xc200+STD_BETA_SRC,0x0600
63 #define wroteSRCRateStreamFull 0xca00+STD_BETA_SRC,0x0600
64 #define wroteSRCRateStreamHalf 0xca00+STD_BETA_SRC,0x0601
65 #define wroteSRCRateStreamQuarter 0xca00+STD_BETA_SRC,0x0602
66 #define wroteSRCRateStreamDouble 0xca00+STD_BETA_SRC,0x0603
67 #define wroteSRCRateStreamQuadruple 0xca00+STD_BETA_SRC,0x0604
69 #define  readSRCSampleRate 0xc200+STD_BETA_SRC,0x0700
70 #define wroteSRCSampleRateUnknown 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_UNKNOWN
71 #define wroteSRCSampleRateNone 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_NONE
72 #define wroteSRCSampleRate11025Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_11025HZ
73 #define wroteSRCSampleRate12000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_12000HZ
74 #define wroteSRCSampleRate16000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_16000HZ
75 #define wroteSRCSampleRate22050Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_22050HZ
76 #define wroteSRCSampleRate24000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_24000HZ
77 #define wroteSRCSampleRate32000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_32000HZ
78 #define wroteSRCSampleRate44100Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_44100HZ
79 #define wroteSRCSampleRate48000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_48000HZ
80 #define wroteSRCSampleRate64000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_64000HZ
81 #define wroteSRCSampleRate88200Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_88200HZ
82 #define wroteSRCSampleRate96000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_96000HZ
83 #define wroteSRCSampleRate128000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_128000HZ
84 #define wroteSRCSampleRate176400Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_176400HZ
85 #define wroteSRCSampleRate192000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_192000HZ
87 #define  readSRCStatus 0xc508,STD_BETA_SRC
88 #define  readSRCControl \
89          readSRCMode, \
90          readSRCRateRequest
92 #define  readSRC_A_Mode 0xc200+STD_BETA_SRC,0x0400
93 #define writeSRC_A_ModeDisable 0xca00+STD_BETA_SRC,0x0400
94 #define writeSRC_A_ModeEnable 0xca00+STD_BETA_SRC,0x0401
96 #define  readSRC_A_RateRequest 0xc200+STD_BETA_SRC,0x0500
97 #define writeSRC_A_RateRequestFull 0xca00+STD_BETA_SRC,0x0500
98 #define writeSRC_A_RateRequestHalf 0xca00+STD_BETA_SRC,0x0501
99 #define writeSRC_A_RateRequestQuarter 0xca00+STD_BETA_SRC,0x0502
100 #define writeSRC_A_RateRequestDouble 0xca00+STD_BETA_SRC,0x0503
101 #define writeSRC_A_RateRequestQuadruple 0xca00+STD_BETA_SRC,0x0504
102 #define writeSRC_A_RateRequestMax192 0xca00+STD_BETA_SRC,0x0580
103 #define writeSRC_A_RateRequestMin32 0xca00+STD_BETA_SRC,0x0580
104 #define writeSRC_A_RateRequestMax96 0xca00+STD_BETA_SRC,0x0581
105 #define writeSRC_A_RateRequestMax48 0xca00+STD_BETA_SRC,0x0582
106 #define writeSRC_A_RateRequestMin64 0xca00+STD_BETA_SRC,0x0583
107 #define writeSRC_A_RateRequestMin128 0xca00+STD_BETA_SRC,0x0584
109 #define  readSRC_A_RateStream 0xc200+STD_BETA_SRC,0x0600
110 #define wroteSRC_A_RateStreamFull 0xca00+STD_BETA_SRC,0x0600
111 #define wroteSRC_A_RateStreamHalf 0xca00+STD_BETA_SRC,0x0601
112 #define wroteSRC_A_RateStreamQuarter 0xca00+STD_BETA_SRC,0x0602
113 #define wroteSRC_A_RateStreamDouble 0xca00+STD_BETA_SRC,0x0603
114 #define wroteSRC_A_RateStreamQuadruple 0xca00+STD_BETA_SRC,0x0604
116 #define  readSRC_A_SampleRate 0xc200+STD_BETA_SRC,0x0700
117 #define wroteSRC_A_SampleRateUnknown 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_UNKNOWN
118 #define wroteSRC_A_SampleRateNone 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_NONE
119 #define wroteSRC_A_SampleRate11025Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_11025HZ
120 #define wroteSRC_A_SampleRate12000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_12000HZ
121 #define wroteSRC_A_SampleRate16000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_16000HZ
122 #define wroteSRC_A_SampleRate22050Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_22050HZ
123 #define wroteSRC_A_SampleRate24000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_24000HZ
124 #define wroteSRC_A_SampleRate32000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_32000HZ
125 #define wroteSRC_A_SampleRate44100Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_44100HZ
126 #define wroteSRC_A_SampleRate48000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_48000HZ
127 #define wroteSRC_A_SampleRate64000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_64000HZ
128 #define wroteSRC_A_SampleRate88200Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_88200HZ
129 #define wroteSRC_A_SampleRate96000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_96000HZ
130 #define wroteSRC_A_SampleRate128000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_128000HZ
131 #define wroteSRC_A_SampleRate176400Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_176400HZ
132 #define wroteSRC_A_SampleRate192000Hz 0xca00+STD_BETA_SRC,0x0700+PAF_SAMPLERATE_192000HZ
134 #define  readSRC_A_Status 0xc508,STD_BETA_SRC
135 #define  readSRC_A_Control \
136          readSRC_A_Mode, \
137          readSRC_A_RateRequest
139 #define  readSRC_B_Mode 0xc200+STD_BETA_SUC,0x0400
140 #define writeSRC_B_ModeDisable 0xca00+STD_BETA_SUC,0x0400
141 #define writeSRC_B_ModeEnable 0xca00+STD_BETA_SUC,0x0401
143 #define  readSRC_B_RateRequest 0xc200+STD_BETA_SUC,0x0500
144 #define writeSRC_B_RateRequestFull 0xca00+STD_BETA_SUC,0x0500
145 #define writeSRC_B_RateRequestHalf 0xca00+STD_BETA_SUC,0x0501
146 #define writeSRC_B_RateRequestQuarter 0xca00+STD_BETA_SUC,0x0502
147 #define writeSRC_B_RateRequestDouble 0xca00+STD_BETA_SUC,0x0503
148 #define writeSRC_B_RateRequestQuadruple 0xca00+STD_BETA_SUC,0x0504
149 #define writeSRC_B_RateRequestMax192 0xca00+STD_BETA_SUC,0x0580
150 #define writeSRC_B_RateRequestMin32 0xca00+STD_BETA_SUC,0x0580
151 #define writeSRC_B_RateRequestMax96 0xca00+STD_BETA_SUC,0x0581
152 #define writeSRC_B_RateRequestMax48 0xca00+STD_BETA_SUC,0x0582
153 #define writeSRC_B_RateRequestMin64 0xca00+STD_BETA_SUC,0x0583
154 #define writeSRC_B_RateRequestMin128 0xca00+STD_BETA_SUC,0x0584
156 #define  readSRC_B_RateStream 0xc200+STD_BETA_SUC,0x0600
157 #define wroteSRC_B_RateStreamFull 0xca00+STD_BETA_SUC,0x0600
158 #define wroteSRC_B_RateStreamHalf 0xca00+STD_BETA_SUC,0x0601
159 #define wroteSRC_B_RateStreamQuarter 0xca00+STD_BETA_SUC,0x0602
160 #define wroteSRC_B_RateStreamDouble 0xca00+STD_BETA_SUC,0x0603
161 #define wroteSRC_B_RateStreamQuadruple 0xca00+STD_BETA_SUC,0x0604
163 #define  readSRC_B_SampleRate 0xc200+STD_BETA_SUC,0x0700
164 #define wroteSRC_B_SampleRateUnknown 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_UNKNOWN
165 #define wroteSRC_B_SampleRateNone 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_NONE
166 #define wroteSRC_B_SampleRate11025Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_11025HZ
167 #define wroteSRC_B_SampleRate12000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_12000HZ
168 #define wroteSRC_B_SampleRate16000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_16000HZ
169 #define wroteSRC_B_SampleRate22050Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_22050HZ
170 #define wroteSRC_B_SampleRate24000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_24000HZ
171 #define wroteSRC_B_SampleRate32000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_32000HZ
172 #define wroteSRC_B_SampleRate44100Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_44100HZ
173 #define wroteSRC_B_SampleRate48000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_48000HZ
174 #define wroteSRC_B_SampleRate64000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_64000HZ
175 #define wroteSRC_B_SampleRate88200Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_88200HZ
176 #define wroteSRC_B_SampleRate96000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_96000HZ
177 #define wroteSRC_B_SampleRate128000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_128000HZ
178 #define wroteSRC_B_SampleRate176400Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_176400HZ
179 #define wroteSRC_B_SampleRate192000Hz 0xca00+STD_BETA_SUC,0x0700+PAF_SAMPLERATE_192000HZ
181 #define  readSRC_B_Status 0xc508,STD_BETA_SUC
182 #define  readSRC_B_Control \
183          readSRC_B_Mode, \
184          readSRC_B_RateRequest
186 #endif /* _SRC_A */