author | Suman Anna <s-anna@ti.com> | |
Fri, 6 Sep 2019 02:51:27 +0000 (21:51 -0500) | ||
committer | Suman Anna <s-anna@ti.com> | |
Fri, 6 Sep 2019 21:52:50 +0000 (16:52 -0500) | ||
commit | d56b850eaa45e71fe19e782266561237e8c11c24 | |
tree | 2e2f41697c6a6ffd3cb012b4ea54c997f79708cb | tree | snapshot (tar.xz tar.gz zip) |
parent | 91f4f1861b287f73e487d8f391bf67cecd815340 | commit | diff |
Examples: J721E: Add RPMsg examples for J721E SoCs
Add the RPMsg echo examples for the latest K3 J721E SoC family. The
J721E SoCs uses the next version of the AM65x ICSSG IP and contains
two instances of this newer ICSSG IP. Each ICSSG instance contains 2
PRU cores, 2 RTU cores, and 2 new additional auxiliary cores called
Transmit PRU (Tx_PRU) cores that are normally used to control the
TX L2 FIFO if enabled in Ethernet applications.
Examples are added for each of the PRU and RTU cores (Tx_PRUs are
left out for the moment) within a single ICSSG IP instance. The same
source files are used to rebuild the project for all the two different
ICSSG instances - ICSSG0 and ICSSG1. The output ELF firmware images
and map files are generated under "gen/icssg<#inst>/" folder in each
of the respective core example folder.
The following are the notable differences w.r.t AM65x:
- The Tx_PRUs uses the same interrupt sources as the regular PRU
cores, so the resource tables can use the Version 0 interrupt
resource type (Version 1 still recommended for all PRU, RTU and
Tx_PRU cores).
- J721E-specific Linker command files, the Constants are identical
to AM65x, but the addition of the Tx_PRU cores required additional
partitioning of the Data RAMs. The second 4 KB in each Data RAM
is equally partitioned between the RTU and Tx_PRU cores, while
the size for PRU core is left unchanged.
- Use a separate copy of the interrupt header file using a J721E
specific folder. The INTC is identical to that of AM65x, so the
same register definitions are used. See commit 91f4f1861b28
("J721E: Add header file for ICSSG INTC"). The same limitations
around CREGISTER #6 exists as on AM65x.
Please see commit df1d9da20473 ("Examples: AM65x: Add RPMsg examples
for AM65x SoCs") for differences w.r.t AM572x.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the RPMsg echo examples for the latest K3 J721E SoC family. The
J721E SoCs uses the next version of the AM65x ICSSG IP and contains
two instances of this newer ICSSG IP. Each ICSSG instance contains 2
PRU cores, 2 RTU cores, and 2 new additional auxiliary cores called
Transmit PRU (Tx_PRU) cores that are normally used to control the
TX L2 FIFO if enabled in Ethernet applications.
Examples are added for each of the PRU and RTU cores (Tx_PRUs are
left out for the moment) within a single ICSSG IP instance. The same
source files are used to rebuild the project for all the two different
ICSSG instances - ICSSG0 and ICSSG1. The output ELF firmware images
and map files are generated under "gen/icssg<#inst>/" folder in each
of the respective core example folder.
The following are the notable differences w.r.t AM65x:
- The Tx_PRUs uses the same interrupt sources as the regular PRU
cores, so the resource tables can use the Version 0 interrupt
resource type (Version 1 still recommended for all PRU, RTU and
Tx_PRU cores).
- J721E-specific Linker command files, the Constants are identical
to AM65x, but the addition of the Tx_PRU cores required additional
partitioning of the Data RAMs. The second 4 KB in each Data RAM
is equally partitioned between the RTU and Tx_PRU cores, while
the size for PRU core is left unchanged.
- Use a separate copy of the interrupt header file using a J721E
specific folder. The INTC is identical to that of AM65x, so the
same register definitions are used. See commit 91f4f1861b28
("J721E: Add header file for ICSSG INTC"). The same limitations
around CREGISTER #6 exists as on AM65x.
Please see commit df1d9da20473 ("Examples: AM65x: Add RPMsg examples
for AM65x SoCs") for differences w.r.t AM572x.
Signed-off-by: Suman Anna <s-anna@ti.com>
18 files changed: