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raw | patch | inline | side by side (parent: 00a5efa)
raw | patch | inline | side by side (parent: 00a5efa)
author | Thomas Mauer <t-mauer@ti.com> | |
Wed, 6 Dec 2023 16:31:44 +0000 (17:31 +0100) | ||
committer | Thomas Mauer <t-mauer@ti.com> | |
Tue, 12 Dec 2023 15:29:48 +0000 (16:29 +0100) |
SORTE_G device:
- extended transmitting input data (device to controller) to 200 Bytes per device
- calculating time triggered send (TTS) based on input data size
- bug fix in time synchronization mechanism
SORTE_G controller:
- changed cycle time from 4us to 10us to showcase 200 bytes per device (tested with 3 devices)
- use of MDIO PHY address from shared memory
SORTE_G ARM application:
- Configuration of 200 Bytes input data_cycle
- Configuration of controller MDIO PHY address via shared memory
- several bug fixes in parameter array, and writing array data.
Signed-off-by: Thomas Mauer <t-mauer@ti.com>
- extended transmitting input data (device to controller) to 200 Bytes per device
- calculating time triggered send (TTS) based on input data size
- bug fix in time synchronization mechanism
SORTE_G controller:
- changed cycle time from 4us to 10us to showcase 200 bytes per device (tested with 3 devices)
- use of MDIO PHY address from shared memory
SORTE_G ARM application:
- Configuration of 200 Bytes input data_cycle
- Configuration of controller MDIO PHY address via shared memory
- several bug fixes in parameter array, and writing array data.
Signed-off-by: Thomas Mauer <t-mauer@ti.com>
19 files changed:
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/.cproject b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/.cproject
index 413e7ac5134e27cc607ffc99d17d1eada6b9ea8b..267e2e3034d065bc4976aa56d058c94f5ef2c1b8 100644 (file)
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=6.1.3"/>\r
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY="/>\r
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>\r
- <listOptionValue builtIn="false" value="PRODUCTS=sysconfig:1.14.0;com.ti.MCU_PLUS_SDK_AM243X:8.6.0.45;"/>\r
+ <listOptionValue builtIn="false" value="PRODUCTS=sysconfig:1.14.0;com.ti.MCU_PLUS_SDK_AM243X:8.6.0.48;"/>\r
<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={"sysconfig":["${SYSCONFIG_TOOL_INCLUDE_PATH}","${SYSCONFIG_TOOL_LIBRARY_PATH}","${SYSCONFIG_TOOL_LIBRARIES}","${SYSCONFIG_TOOL_SYMBOLS}","${SYSCONFIG_TOOL_SYSCONFIG_MANIFEST}"],"com.ti.MCU_PLUS_SDK_AM243X":["${COM_TI_MCU_PLUS_SDK_AM243X_INCLUDE_PATH}","${COM_TI_MCU_PLUS_SDK_AM243X_LIBRARY_PATH}","${COM_TI_MCU_PLUS_SDK_AM243X_LIBRARIES}","${COM_TI_MCU_PLUS_SDK_AM243X_SYMBOLS}","${COM_TI_MCU_PLUS_SDK_AM243X_SYSCONFIG_MANIFEST}"]}"/>\r
</option>\r
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1511697655" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="TICLANG_2.1.3.LTS" valueType="string"/>\r
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_AM243x_arm.rprc b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_AM243x_arm.rprc
index bf0951e00e7d573216243f74692815c3b4a23ee6..3f1ff0a78de5e5061249d182c4c9be101b861020 100644 (file)
Binary files a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_AM243x_arm.rprc and b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_AM243x_arm.rprc differ
Binary files a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_AM243x_arm.rprc and b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_AM243x_arm.rprc differ
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_am243x-lp_r5fss0-0_freertos_ti-arm-clang.rprc b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_am243x-lp_r5fss0-0_freertos_ti-arm-clang.rprc
index bf0951e00e7d573216243f74692815c3b4a23ee6..7a917dc0e60bc5cd77cfe980ac09a15c4125bc62 100644 (file)
Binary files a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_am243x-lp_r5fss0-0_freertos_ti-arm-clang.rprc and b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_am243x-lp_r5fss0-0_freertos_ti-arm-clang.rprc differ
Binary files a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_am243x-lp_r5fss0-0_freertos_ti-arm-clang.rprc and b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_G_am243x-lp_r5fss0-0_freertos_ti-arm-clang.rprc differ
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_g_device_PRU0.h b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_g_device_PRU0.h
index bccbfc68e9375fb50751db4c7b53e0afc0ef2262..747c01fa69b58fab4c92076f03e9a51d134e2637 100644 (file)
0x2400008e,\r
0x2402048f,\r
0x808f208e,\r
-0x2303b39d,\r
+0x2303cd9d,\r
0x10e0e0e0,\r
0x2e8a2002,\r
0x2e8aa002,\r
0xd101d403,\r
0x69031402,\r
-0x2304639d,\r
+0x23047d9d,\r
0xc901d403,\r
0x69041402,\r
-0x2302f19d,\r
+0x23030b9d,\r
0xc901d403,\r
0x69051402,\r
-0x2302f19d,\r
+0x23030b9d,\r
0xcf0fd4f3,\r
0x2300ce9d,\r
0x5700e2f1,\r
0x240403d0,\r
0x24020190,\r
0xe1382f90,\r
-0x24041d90,\r
+0x24043790,\r
0xe1080f90,\r
-0x24042f90,\r
+0x24044990,\r
0xe10c0f90,\r
-0x24042f90,\r
+0x24044990,\r
0xe1100f90,\r
-0x24043b90,\r
+0x24045590,\r
0xe1140f90,\r
0x2400030e,\r
0x81701a0e,\r
0x81103b8e,\r
0x2400022e,\r
0x81143b8e,\r
-0xcb00d417,\r
+0xcb00d41c,\r
0x9100298e,\r
0x1f01eeee,\r
0x8100298e,\r
0x81103b8e,\r
0x2400012e,\r
0x81143b8e,\r
-0x7b00000b,\r
+0x7b000010,\r
0xd100d404,\r
0x916c1b10,\r
0x6f0010fe,\r
0x240403d0,\r
0x24020190,\r
0xe1382f90,\r
-0x24033c90,\r
+0x24035590,\r
0xe1080f90,\r
-0x24037690,\r
+0x24039090,\r
0xe10c0f90,\r
-0x24037590,\r
+0x24038f90,\r
0xe1100f90,\r
-0x24038990,\r
+0x2403a390,\r
0xe1140f90,\r
0x9100298e,\r
0x1f01eeee,\r
0x81103b8e,\r
0x2400002e,\r
0x81143b8e,\r
-0xc900d4e8,\r
+0xc900d4ed,\r
0x241f178e,\r
0x81001b0e,\r
0x81041b2e,\r
0x81103b8e,\r
0x2400012e,\r
0x81143b8e,\r
-0x790000df,\r
+0x790000e4,\r
0xd100d404,\r
0x916c1b10,\r
0x6f0010fe,\r
0x240004d0,\r
0x24020190,\r
0xe1382f90,\r
-0x2404a390,\r
+0x2404bd90,\r
0xe1080f90,\r
-0x2404b090,\r
+0x2404ca90,\r
0xe10c0f90,\r
-0x2404b790,\r
+0x2404d190,\r
0xe1100f90,\r
0x9100298e,\r
0x1d01eeee,\r
0x2400022e,\r
0x81143b8e,\r
0x91241c17,\r
-0xc900d4bd,\r
+0xc900d4c2,\r
0x241f178e,\r
0x81001b0e,\r
0x81041b2e,\r
0x81143b8e,\r
0x2400022e,\r
0x81103b8e,\r
-0x790000b4,\r
+0x790000b9,\r
0xd100d404,\r
0x916c1b10,\r
0x6f0010fe,\r
0x240000d0,\r
0x24000490,\r
0xe1382f90,\r
-0x24049190,\r
+0x2404ab90,\r
0xe1080f90,\r
0x2eff0184,\r
0x2eff8185,\r
0x2403c0e6,\r
0x8170bc84,\r
-0xd101d491,\r
+0xd101d496,\r
0x9100298e,\r
0x1d01eeee,\r
0x8100298e,\r
0x240033ce,\r
0x2408018e,\r
0x81103b8e,\r
-0xc900d483,\r
+0xc900d488,\r
0x241f178e,\r
0x81001b0e,\r
0x81041b2e,\r
0x81143b8e,\r
0x2400022e,\r
0x81103b8e,\r
-0x7900007a,\r
+0x7900007f,\r
0x91203a90,\r
0x91483a90,\r
0x91303a90,\r
0x240014ce,\r
0x2402038e,\r
0x81143b8e,\r
-0x79000061,\r
+0x79000066,\r
0x240000d0,\r
0x24000090,\r
0xe1382f90,\r
-0x2402c190,\r
+0x2402db90,\r
0xe1080f90,\r
0x241f178e,\r
0x81001b0e,\r
0x240014ce,\r
0x2408038e,\r
0x81143b8e,\r
-0xc900d456,\r
+0xc900d45b,\r
0x91141b0e,\r
0x1d000e0e,\r
0x81141b0e,\r
-0x79000052,\r
+0x79000057,\r
0xc901d40e,\r
0x2400018e,\r
0x240803ce,\r
0x916c1b10,\r
0x6f0010fb,\r
0x2eff00de,\r
-0xd101d427,\r
+0xd101d42c,\r
0x240000ee,\r
0x24018090,\r
0x80903a8e,\r
0x240000d0,\r
0x24141090,\r
0xe1382f90,\r
-0x24027090,\r
+0x24027590,\r
0xe1080f90,\r
-0x24029a90,\r
+0x2402a290,\r
0xe10c0f90,\r
0x91741a0e,\r
0xcf000eff,\r
0x240100ce,\r
0x90ce3c8e,\r
0x81783a8e,\r
-0x240000ce,\r
-0x2401f48e,\r
+0x91341c8f,\r
+0x2401f4ee,\r
+0x71288f05,\r
+0x05288f8f,\r
+0x09038fef,\r
+0x00efeeee,\r
+0x01a0eeee,\r
0x81983a8e,\r
0x24007dce,\r
0x2401908f,\r
0x240000d0,\r
0x24000490,\r
0xe13c2f90,\r
-0x24022c90,\r
+0x24023190,\r
0xe1080f90,\r
-0x24022c90,\r
+0x24023190,\r
0xe10c0f90,\r
-0x24022c90,\r
+0x24023190,\r
0xe1100f90,\r
-0x24022590,\r
+0x24022a90,\r
0xe1140f90,\r
-0x24023f90,\r
+0x24024490,\r
0xe1180f90,\r
0x241f178e,\r
0x81001b0e,\r
0x2455559e,\r
0x24d5559e,\r
0x1017171e,\r
-0x24000080,\r
-0x91621c00,\r
-0x611a8002,\r
-0x24001a80,\r
+0x10d4d43e,\r
+0x91621c80,\r
+0x108080c0,\r
+0x61188002,\r
+0x24001880,\r
0x2400608e,\r
0x908e1c8e,\r
0x9e8ed902,\r
0x24000801,\r
-0x30000003,\r
+0xc9000002,\r
0x2c40011e,\r
-0x10e0e0e0,\r
-0x491a8002,\r
+0x0b010000,\r
+0x30000002,\r
+0x2c41019e,\r
+0x4918c002,\r
0x242c00df,\r
-0x7f0000a1,\r
+0x7f00009e,\r
0x2f052780,\r
-0x2400ff2e,\r
-0x24000081,\r
-0x91621c00,\r
-0x24001ac1,\r
-0x916c1b0e,\r
-0x502e0e17,\r
-0x100e0e2e,\r
-0x591a8103,\r
-0x6f000efc,\r
-0x79000016,\r
-0x5f140efa,\r
-0x04c18100,\r
-0x59100002,\r
-0x24001080,\r
-0x68c18103,\r
-0x6f000ef5,\r
-0x7900000f,\r
+0x91621c80,\r
+0x7118802c,\r
+0x05188080,\r
+0x108080c0,\r
+0x61208012,\r
0x2400608e,\r
0x908e1c8e,\r
+0x01188e8e,\r
+0x0b058000,\r
+0x5100000d,\r
+0x05010000,\r
+0x928ef982,\r
+0x01208e8e,\r
+0x24000801,\r
+0x2400ff2f,\r
+0x916c1b0f,\r
+0x502f0f21,\r
+0x100f0f2f,\r
+0x5f100ffd,\r
+0x31070002,\r
+0x2c4201fe,\r
+0x6f0000f4,\r
+0x2400ff2f,\r
+0x111fc000,\r
+0x5100000f,\r
0x9e8ed902,\r
0x24000801,\r
-0x30000003,\r
+0xc9000002,\r
0x2c40011e,\r
-0x10e0e0e0,\r
-0x00008181,\r
-0x6ec181eb,\r
+0xc9010002,\r
+0x2c41019e,\r
+0x0b020000,\r
+0x51000007,\r
+0x916c1b0f,\r
+0x502f0f0f,\r
+0x100f0f2f,\r
+0x5f180ffd,\r
+0x30000002,\r
+0x2c4201fe,\r
+0x2400ff2f,\r
+0x916c1b0f,\r
+0x502f0f08,\r
+0x100f0f2f,\r
+0x5f460ffd,\r
0x242c00df,\r
-0x7f0000e9,\r
-0x918c1c8e,\r
-0x01018e8e,\r
-0x818c1c8e,\r
+0x916c1b0f,\r
+0x502f0f03,\r
+0x100f0f2f,\r
+0x6f000ffd,\r
0x241f178e,\r
0x81001b0e,\r
0x240014ce,\r
0x2402038e,\r
0x81143b8e,\r
0x244084df,\r
-0x7f00007a,\r
+0x7f000065,\r
0x2400ff1e,\r
0x2f052780,\r
0x910c1c8e,\r
0x24000534,\r
0x1f0fd4d4,\r
0x7f0000f5,\r
-0xc904d449,\r
+0xc904d448,\r
0x1d04d4d4,\r
0x69005820,\r
0x91103c8e,\r
0x24e3138e,\r
0x2400000f,\r
0xe1000e0f,\r
-0x79000028,\r
+0x79000027,\r
0x5105140d,\r
0x242710f0,\r
0x91803a91,\r
0x0101efef,\r
0x2400030e,\r
0x10efeff1,\r
-0x710bef04,\r
-0x2400038f,\r
+0x7103ef03,\r
0x81011a0e,\r
0x81081a8f,\r
0x912c1c89,\r
0x10e0e0e0,\r
0x2f052780,\r
0x2e8a2002,\r
-0x69ff0225,\r
-0x69014224,\r
+0x69ff0226,\r
+0x69014225,\r
0xc9036202,\r
0x1f0ed4d4,\r
0x240000d6,\r
0x1f01d4d4,\r
0xc9006202,\r
0x1d01d4d4,\r
-0xc901d41e,\r
+0xc901d41f,\r
0xc900d403,\r
0x1f006262,\r
0x1f01d4d4,\r
0x81241c17,\r
0x91621c8f,\r
0x91661ccf,\r
+0x81341cc3,\r
0x008fc3c3,\r
0x10c3c3d7,\r
0x10848498,\r
0x5129f325,\r
0x5128f31a,\r
0x5134f319,\r
-0x5127f318,\r
-0x5133f317,\r
+0x5127f31d,\r
+0x5133f31c,\r
0x511af310,\r
0x511bf309,\r
0x91b41c8e,\r
0x2eff818e,\r
0x230000c3,\r
0x240001ee,\r
-0x2304d5c3,\r
-0x2304d7c3,\r
-0x2104d600,\r
+0x2304efc3,\r
+0x2304f1c3,\r
+0x2104f000,\r
0x10000000,\r
0x20c30000};\r
\r
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_g_device_PRU1.h b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_g_device_PRU1.h
index 67b9410e412bbdbf8b29abb95bc0f6da2e7d80f0..1c0747b0ec8297d7e1e82e0523df0000a773a2d8 100644 (file)
0x2402008e,\r
0x2402048f,\r
0x808f208e,\r
-0x23039e9d,\r
+0x2303b89d,\r
0x10e0e0e0,\r
0x2e8a2002,\r
0x2e8aa002,\r
0xd101d403,\r
0x69031402,\r
-0x23044e9d,\r
+0x2304689d,\r
0xc901d403,\r
0x69041402,\r
-0x2302dc9d,\r
+0x2302f69d,\r
0xc901d403,\r
0x69051402,\r
-0x2302dc9d,\r
+0x2302f69d,\r
0xcf0fd4f3,\r
0x2300ce9d,\r
0x5700e2f1,\r
0x240403d0,\r
0x24020190,\r
0xe1382f90,\r
-0x24040890,\r
+0x24042290,\r
0xe1080f90,\r
-0x24041a90,\r
+0x24043490,\r
0xe10c0f90,\r
-0x24041a90,\r
+0x24043490,\r
0xe1100f90,\r
-0x24042690,\r
+0x24044090,\r
0xe1140f90,\r
0x2400030e,\r
0x81701a0e,\r
0x81103b8e,\r
0x2400022e,\r
0x81143b8e,\r
-0xcb00d417,\r
+0xcb00d41c,\r
0x9100298e,\r
0x1f01eeee,\r
0x8100298e,\r
0x81103b8e,\r
0x2400012e,\r
0x81143b8e,\r
-0x7b00000b,\r
+0x7b000010,\r
0xd100d404,\r
0x91681b10,\r
0x6f0010fe,\r
0x240403d0,\r
0x24020190,\r
0xe1382f90,\r
-0x24032790,\r
+0x24034090,\r
0xe1080f90,\r
-0x24036190,\r
+0x24037b90,\r
0xe10c0f90,\r
-0x24036090,\r
+0x24037a90,\r
0xe1100f90,\r
-0x24037490,\r
+0x24038e90,\r
0xe1140f90,\r
0x9100298e,\r
0x1f01eeee,\r
0x81103b8e,\r
0x2400002e,\r
0x81143b8e,\r
-0xc900d4e8,\r
+0xc900d4ed,\r
0x241f178e,\r
0x81001b0e,\r
0x81041b2e,\r
0x81103b8e,\r
0x2400012e,\r
0x81143b8e,\r
-0x790000df,\r
+0x790000e4,\r
0xd100d404,\r
0x91681b10,\r
0x6f0010fe,\r
0x240004d0,\r
0x24020190,\r
0xe1382f90,\r
-0x24048e90,\r
+0x2404a890,\r
0xe1080f90,\r
-0x24049b90,\r
+0x2404b590,\r
0xe10c0f90,\r
-0x2404a290,\r
+0x2404bc90,\r
0xe1100f90,\r
0x9100298e,\r
0x1d01eeee,\r
0x2400022e,\r
0x81143b8e,\r
0x91241c17,\r
-0xc900d4bd,\r
+0xc900d4c2,\r
0x241f178e,\r
0x81001b0e,\r
0x81041b2e,\r
0x81143b8e,\r
0x2400022e,\r
0x81103b8e,\r
-0x790000b4,\r
+0x790000b9,\r
0xd100d404,\r
0x91681b10,\r
0x6f0010fe,\r
0x240000d0,\r
0x24000490,\r
0xe1382f90,\r
-0x24047c90,\r
+0x24049690,\r
0xe1080f90,\r
0x2eff0184,\r
0x2eff8185,\r
0x2403c0e6,\r
0x8170bc84,\r
-0xd101d491,\r
+0xd101d496,\r
0x9100298e,\r
0x1d01eeee,\r
0x8100298e,\r
0x240033ce,\r
0x2409018e,\r
0x81143b8e,\r
-0xc900d483,\r
+0xc900d488,\r
0x241f178e,\r
0x81001b0e,\r
0x81041b2e,\r
0x81143b8e,\r
0x2400022e,\r
0x81103b8e,\r
-0x7900007a,\r
+0x7900007f,\r
0x91203a90,\r
0x91483a90,\r
0x91303a90,\r
0x240014ce,\r
0x2403038e,\r
0x81103b8e,\r
-0x79000061,\r
+0x79000066,\r
0x240000d0,\r
0x24000090,\r
0xe1382f90,\r
-0x2402ac90,\r
+0x2402c690,\r
0xe1080f90,\r
0x241f178e,\r
0x81041b2e,\r
0x240014ce,\r
0x2409038e,\r
0x81103b8e,\r
-0xc900d456,\r
+0xc900d45b,\r
0x91101b0e,\r
0x1d000e0e,\r
0x81101b0e,\r
-0x79000052,\r
+0x79000057,\r
0xc901d40e,\r
0x2401008e,\r
0x240803ce,\r
0x916c1b10,\r
0x6f0010fb,\r
0x2eff00de,\r
-0xd101d427,\r
+0xd101d42c,\r
0x240000ee,\r
0x24018090,\r
0x80903a8e,\r
0x240000d0,\r
0x24131090,\r
0xe1382f90,\r
-0x24025b90,\r
+0x24026090,\r
0xe1080f90,\r
-0x24028590,\r
+0x24028d90,\r
0xe10c0f90,\r
0x91741a0e,\r
0xcf000eff,\r
0x240100ce,\r
0x90ce3c8e,\r
0x81783a8e,\r
-0x240000ce,\r
-0x2401f48e,\r
+0x91341c8f,\r
+0x2401f4ee,\r
+0x71288f05,\r
+0x05288f8f,\r
+0x09038fef,\r
+0x00efeeee,\r
+0x01a0eeee,\r
0x81903a8e,\r
0x24007dce,\r
0x2401908f,\r
0x240000d0,\r
0x24000490,\r
0xe13c2f90,\r
-0x24021790,\r
+0x24021c90,\r
0xe1080f90,\r
-0x24021790,\r
+0x24021c90,\r
0xe10c0f90,\r
-0x24021790,\r
+0x24021c90,\r
0xe1100f90,\r
-0x24021090,\r
+0x24021590,\r
0xe1140f90,\r
-0x24022a90,\r
+0x24022f90,\r
0xe1180f90,\r
0x241f178e,\r
0x81041b2e,\r
0x2455559e,\r
0x24d5559e,\r
0x1017171e,\r
-0x24000080,\r
-0x91621c00,\r
-0x611a8002,\r
-0x24001a80,\r
+0x10d4d43e,\r
+0x91621c80,\r
+0x108080c0,\r
+0x61188002,\r
+0x24001880,\r
0x2400608e,\r
0x908e1c8e,\r
0x9e8ed802,\r
0x24000801,\r
-0x30000003,\r
+0xc9000002,\r
0x2c40011e,\r
-0x10e0e0e0,\r
-0x491a8002,\r
+0x0b010000,\r
+0x30000002,\r
+0x2c41019e,\r
+0x4918c002,\r
0x242c00df,\r
-0x7f0000a1,\r
+0x7f00009e,\r
0x2f05a780,\r
-0x2400ff2e,\r
-0x24000081,\r
-0x91621c00,\r
-0x24001ac1,\r
-0x91681b0e,\r
-0x502e0e17,\r
-0x100e0e2e,\r
-0x591a8103,\r
-0x6f000efc,\r
-0x79000016,\r
-0x5f140efa,\r
-0x04c18100,\r
-0x59100002,\r
-0x24001080,\r
-0x68c18103,\r
-0x6f000ef5,\r
-0x7900000f,\r
+0x91621c80,\r
+0x7118802c,\r
+0x05188080,\r
+0x108080c0,\r
+0x61208012,\r
0x2400608e,\r
0x908e1c8e,\r
+0x01188e8e,\r
+0x0b058000,\r
+0x5100000d,\r
+0x05010000,\r
+0x928ef882,\r
+0x01208e8e,\r
+0x24000801,\r
+0x2400ff2f,\r
+0x91681b0f,\r
+0x502f0f21,\r
+0x100f0f2f,\r
+0x5f100ffd,\r
+0x31070002,\r
+0x2c4201fe,\r
+0x6f0000f4,\r
+0x2400ff2f,\r
+0x111fc000,\r
+0x5100000f,\r
0x9e8ed802,\r
0x24000801,\r
-0x30000003,\r
+0xc9000002,\r
0x2c40011e,\r
-0x10e0e0e0,\r
-0x00008181,\r
-0x6ec181eb,\r
+0xc9010002,\r
+0x2c41019e,\r
+0x0b020000,\r
+0x51000007,\r
+0x91681b0f,\r
+0x502f0f0f,\r
+0x100f0f2f,\r
+0x5f180ffd,\r
+0x30000002,\r
+0x2c4201fe,\r
+0x2400ff2f,\r
+0x91681b0f,\r
+0x502f0f08,\r
+0x100f0f2f,\r
+0x5f460ffd,\r
0x242c00df,\r
-0x7f0000e9,\r
-0x918c1c8e,\r
-0x01018e8e,\r
-0x818c1c8e,\r
+0x91681b0f,\r
+0x502f0f03,\r
+0x100f0f2f,\r
+0x6f000ffd,\r
0x241f178e,\r
0x81041b2e,\r
0x240014ce,\r
0x2403038e,\r
0x81103b8e,\r
0x244084df,\r
-0x7f00007a,\r
+0x7f000065,\r
0x2400ff1e,\r
0x2f05a780,\r
0x910c1c8e,\r
0x24000534,\r
0x1f0fd4d4,\r
0x7f0000f5,\r
-0xc904d449,\r
+0xc904d448,\r
0x1d04d4d4,\r
0x69005820,\r
0x91103c8e,\r
0x24e3138e,\r
0x2400000f,\r
0xe1000e0f,\r
-0x79000028,\r
+0x79000027,\r
0x5105140d,\r
0x242710f0,\r
0x91803a91,\r
0x0101efef,\r
0x2400030e,\r
0x10efeff1,\r
-0x710bef04,\r
-0x2400038f,\r
+0x7103ef03,\r
0x81011a0e,\r
0x81081a8f,\r
0x912c1c89,\r
0x10e0e0e0,\r
0x2f05a780,\r
0x2e8a2002,\r
-0x69ff0225,\r
-0x69014224,\r
+0x69ff0226,\r
+0x69014225,\r
0xc9036202,\r
0x1f0ed4d4,\r
0x240000d6,\r
0x1f01d4d4,\r
0xc9006202,\r
0x1d01d4d4,\r
-0xc901d41e,\r
+0xc901d41f,\r
0xc900d403,\r
0x1f006262,\r
0x1f01d4d4,\r
0x81241c17,\r
0x91621c8f,\r
0x91661ccf,\r
+0x81341cc3,\r
0x008fc3c3,\r
0x10c3c3d7,\r
0x10848498,\r
0x5129f325,\r
0x5128f31a,\r
0x5134f319,\r
-0x5127f318,\r
-0x5133f317,\r
+0x5127f31d,\r
+0x5133f31c,\r
0x511af310,\r
0x511bf309,\r
0x91b41c8e,\r
0x2eff818e,\r
0x230000c3,\r
0x240001ee,\r
-0x2304c0c3,\r
-0x2304c2c3,\r
-0x2104c100,\r
+0x2304dac3,\r
+0x2304dcc3,\r
+0x2104db00,\r
0x10000000,\r
0x20c30000};\r
\r
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_g_master_PRU0.h b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/SORTE_g_master_PRU0.h
index 7a5e81b1a175620ec85f5e3bd711000a5408ee8e..b8468acd46eba7c389136d13ed955929916796d7 100644 (file)
0x24a00082,\r
0x240079e3,\r
0xe1000283,\r
-0x24024383,\r
+0x24024583,\r
0xe10c0283,\r
-0x24024d83,\r
+0x24024f83,\r
0xe1100283,\r
-0x24025983,\r
+0x24025b83,\r
0xe1140283,\r
-0x24026a83,\r
+0x24026c83,\r
0xe1180283,\r
0x247fffe3,\r
0xe1300283,\r
0x01008181,\r
0x80811841,\r
0x240000ce,\r
-0x240f9c8e,\r
+0x24270c8e,\r
0x2400008f,\r
0x01208f8f,\r
0x808f388e,\r
0xe1002e8f,\r
0x240080ef,\r
0xe1042e8f,\r
-0x910c150e,\r
-0xcf030eff,\r
+0x2400048f,\r
+0x908f1c8f,\r
+0x910c158e,\r
+0xce2f8efd,\r
0x9100180e,\r
-0xcf000efd,\r
+0xcf000efb,\r
0x24000a19,\r
0x244084df,\r
0x240002da,\r
0x24a00082,\r
0x240041e3,\r
0xe1000283,\r
-0x24027c83,\r
+0x24027e83,\r
0xe10c0283,\r
-0x24028983,\r
+0x24028b83,\r
0xe1100283,\r
-0x24029583,\r
+0x24029783,\r
0xe1140283,\r
-0x2402a683,\r
+0x2402a883,\r
0xe1180283,\r
0x247feae3,\r
0xe1300283,\r
0x2efe0060,\r
0x10000000,\r
0x2e853580,\r
-0x2a000000,\r
-0x050ee2e2,\r
-0xe100c2c3,\r
-0x240000c5,\r
-0x24000085,\r
-0x240000c0,\r
-0x24000080,\r
-0x50e5e018,\r
-0x240000c0,\r
-0x24000080,\r
-0x240000c4,\r
-0x24000084,\r
-0x50e4e013,\r
-0x04e4e0e0,\r
-0x0b03e0e6,\r
-0xc91ce605,\r
-0x24ffffc0,\r
-0x24ffff80,\r
-0x091de0e0,\r
-0x12e0e6e6,\r
-0xf100248e,\r
-0xf1000e00,\r
-0x090100e0,\r
-0xf0e00580,\r
-0x0101eeee,\r
-0x0104e4e4,\r
-0xf100248f,\r
-0x228000c3,\r
-0x0104e4e4,\r
-0x0501e6e6,\r
-0x6f00e6f6,\r
-0x230300c3,\r
-0xf100c2c3,\r
-0x010ee2e2,\r
-0x20c30000,\r
-0x0502e2e2,\r
-0xe10002c3,\r
-0x24ffffc0,\r
-0x24ffff80,\r
-0x24ffffc1,\r
-0x24ffff81,\r
-0x68e1e004,\r
-0x2eff818e,\r
-0x10eeeeef,\r
-0x2102e900,\r
-0x24ffffc0,\r
-0x24ffff80,\r
-0xf100208e,\r
-0x0104e0ef,\r
-0x230000c3,\r
-0xf10002c3,\r
-0x0102e2e2,\r
-0x20c30000,\r
-0x240000c0,\r
-0x24000480,\r
-0x0504e0e2,\r
-0x2302b9c3,\r
-0x2eff818e,\r
-0x230000c3,\r
-0x240001ee,\r
-0x2302fcc3,\r
-0x240000c0,\r
-0x24000480,\r
-0x0504e0e2,\r
-0x2eff818e,\r
-0x230000c3,\r
-0x240001ee,\r
-0x2302fcc3,\r
-0x2302fec3,\r
-0x2102fd00,\r
-0x10000000,\r
-0x20c30000,\r
-0x20c30000};\r
+0x2a000000};\r
\r
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/example.syscfg b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/example.syscfg
index 9bde5608446e8239c9390ed55869e5dad21883e9..03af73f8933b013c8b7153c770408a7a62fbc7e1 100644 (file)
enet_icss2.QoS = 3;
enet_icss2.LargePoolPktCount = 16;
enet_icss2.mdioMdcEnable = false;
+enet_icss2.PktPoolEnable = false;
enet_icss2.txDmaChannel[0].$name = "ENET_DMA_TX_CH1";
enet_icss2.txDmaChannel[0].PacketsCount = 8;
enet_icss2.rxDmaChannel[0].$name = "ENET_DMA_RX_CH1";
diff --git a/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/sorte_g_app.c b/examples/am243x/SORTE_G/SORTE_G_AM243x_arm/sorte_g_app.c
index bfd00452a8258f142d164535c992f1ab1ed46c34..05c347cc9441d4950138f8522093521b3c7e0cd6 100644 (file)
#define Inter_packet_gap 0x10 // 16-bit
#define T_in 0x12 // 16-bit
#define T_out 0x14 // 16-bit
-#define Topology 0x15 // 8-bit
-#define Diagnostics 0x16 // 8-bit
-#define Alarm 0x17 // 8-bit
-#define Crc_mode 0x18 // 8-bit
+#define Topology 0x16 // 8-bit
+#define Diagnostics 0x17 // 8-bit
+#define Alarm 0x18 // 8-bit
+#define Crc_mode 0x19 // 8-bit
#define OVERSAMPLING_1 (1+1) // 4us
#define OVERSAMPLING_10 (10+1) // 40us
#define SMA_WRAP_AROUND_64 0xFF // 64 SMA values
#define SMA_MULTIPLIER_64 6 // /64 SMA values
+// PHY address
+#define MDIO_PHY_CONFIG_OFFSET (0x04U)
+
+// MDIO on AM64GPEVM
+#define PHY1_ADDRESS 15
+#define PHY2_ADDRESS 3
+/*********************************************************
+ * Version 0.1 of the SORTE G test software from 18 Oct 23
+ *
+ *********************************************************/
+
+uint32_t SORTEG_VERSION_MAIN = 0;
+uint32_t SORTEG_VERSION_SUB = 001;
void generic_pruss_init()
{
HwiP_Params hwiPrms;
// set jumper J6-60 to J6-59 -> device
ModeStatus = HW_RD_REG32(0x00601048);
if((ModeStatus & (1<<(35-32))) == (1<<(35-32)))
+ {
ModeStatus = 1; // controller
+ DebugP_log("\tCONTROLLER\r\n");
+ }
else
+ {
ModeStatus = 0; // device
-
-
+ DebugP_log("\tDEVICE\r\n");
+ }
// enable/configure MDIO
// ToDo - use SDK command for this
HW_WR_REG32(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE + 0x04, 0x400000ff);
HW_WR_REG32(gPru_ctrl, CTR_EN);
// PHYs are configured for RGMII TX clock delay (register 0x0032, bit 1)
- MDIO_phyRegRead(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, 3, 0x01, &temp16);
- MDIO_phyRegRead(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, 15, 0x01, &temp16);
- MDIO_phyExtRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, 3, 0x32, 0xD2);
- MDIO_phyRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, 3, 0x1F, 0x4000);
- MDIO_phyExtRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, 15, 0x32, 0xD2);
- MDIO_phyRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, 15, 0x1F, 0x4000);
+ MDIO_phyRegRead(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, PHY1_ADDRESS, 0x01, &temp16);
+ MDIO_phyRegRead(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, PHY2_ADDRESS, 0x01, &temp16);
+ MDIO_phyExtRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, PHY1_ADDRESS, 0x32, 0xD2);
+ MDIO_phyRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, PHY1_ADDRESS, 0x1F, 0x4000);
+ MDIO_phyExtRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, PHY2_ADDRESS, 0x32, 0xD2);
+ MDIO_phyRegWrite(icssgBaseAddr + CSL_ICSS_G_PR1_MDIO_V1P7_MDIO_REGS_BASE, NULL, PHY2_ADDRESS, 0x1F, 0x4000);
if(enhancedlink_enable == 0)
{
HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_DRAM0_SLV_RAM_REGS_BASE + PARAM_DATA_OFFSET + Diagnostics, 0);
HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_DRAM0_SLV_RAM_REGS_BASE + PARAM_DATA_OFFSET + Alarm, 0);
HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_DRAM0_SLV_RAM_REGS_BASE + PARAM_DATA_OFFSET + Crc_mode, 1);
+
+ // Configure share RAM
+ HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + MDIO_PHY_CONFIG_OFFSET, (PHY2_ADDRESS<<8) | (PHY1_ADDRESS<<0)); // set MDIO address: 0x0000.0880
}
else // device
{
-#define MDIO_PHY_CONFIG_OFFSET (0x04U)
+
// Configure share RAM
- HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + MDIO_PHY_CONFIG_OFFSET, (3<<0) | (15<<8)); // set MDIO address: 0x0000.8008
- HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_INDATA_FRAME_BUFFER_PTR, DEVICE_INDATA_FRAME_BUFFER_LOCATION);
- HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_INDATA_FRAME_BUFFER_SIZE, 12); // 12 Bytes payload
- HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_OUTDATA_FRAME_BUFFER_PTR, DEVICE_OUTDATA_FRAME_BUFFER_LOCATION);
- HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_OUTDATA_FRAME_BUFFER_SIZE, 12); // 12 Bytes payload
- HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_MASTER_FRAME_BUFFER_PTR, DEVICE_MASTER_FRAME_BUFFER_LOCATION);
+ HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + MDIO_PHY_CONFIG_OFFSET, (PHY1_ADDRESS<<8) | (PHY2_ADDRESS<<0)); // set MDIO address: 0x0000.0880
+ HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_INDATA_FRAME_BUFFER_PTR, DEVICE_INDATA_FRAME_BUFFER_LOCATION);
+ HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_INDATA_FRAME_BUFFER_SIZE, 200); // 12 Bytes payload
+ HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_OUTDATA_FRAME_BUFFER_PTR, DEVICE_OUTDATA_FRAME_BUFFER_LOCATION);
+ HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_OUTDATA_FRAME_BUFFER_SIZE, 12); // 12 Bytes payload
+ HW_WR_REG16(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE + DEVICE_MASTER_FRAME_BUFFER_PTR, DEVICE_MASTER_FRAME_BUFFER_LOCATION);
}
if(ModeStatus == 1) //controller
{
/*Run firmware*/
PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU0);
// DebugP_log("PRESS 1 to start Controller\r\n");
+
+ uint8_t SORTE_G_PRU_CONTROLLER_MAIN = 0; // HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE, CONTROLLER_SW_VERSION_MAIN);
+ uint8_t SORTE_G_PRU_CONTROLLER_SUB = 001; // HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE, CONTROLLER_SW_VERSION_SUB);
+
+ DebugP_log("\r\nSORTE_G Demo application for Controller PRU0 software\r\n");
+ DebugP_log("Version %d.%03d \n\r", SORTE_G_PRU_CONTROLLER_MAIN, SORTE_G_PRU_CONTROLLER_SUB);
+
}
else {
/* load sorte_controller firmware */
/*Run firmware*/
PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU0);
PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU1);
+
+ uint8_t SORTE_G_PRU0_DEVICE_MAIN = 0 ;//HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE, DEVICE_SW_VERSION_MAIN);
+ uint8_t SORTE_G_PRU0_DEVICE_SUB = 001 ;//HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE, DEVICE_SW_VERSION_SUB);
+
+ uint8_t SORTE_G_PRU1_DEVICE_MAIN = 0 ;//HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE, DEVICE_SW_VERSION_MAIN);
+ uint8_t SORTE_G_PRU1_DEVICE_SUB = 001 ;//HW_WR_REG8(icssgBaseAddr + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE, DEVICE_SW_VERSION_SUB);
+
+ DebugP_log("\r\nSORTE_G Demo application for Device PRU0 software\r\n");
+ DebugP_log("Version %d.%03d \n\r", SORTE_G_PRU0_DEVICE_MAIN, SORTE_G_PRU0_DEVICE_SUB);
+ DebugP_log("\r\nSORTE_G Demo application for Device PRU1 software\r\n");
+ DebugP_log("Version %d.%03d \n\r", SORTE_G_PRU1_DEVICE_MAIN, SORTE_G_PRU1_DEVICE_SUB);
}
}
static void PRU_IsrFxn()
{
- PRUICSS_clearEvent(gPruIcss0Handle, 16); // 16 is PRU0 intr[0]
+ int status;
+ status = PRUICSS_clearEvent(gPruIcss0Handle, 16); // 16 is PRU0 intr[0]
}
diff --git a/examples/am243x/SORTE_G/SORTE_g_device/discovery_g.asm b/examples/am243x/SORTE_G/SORTE_g_device/discovery_g.asm
index 310b9bb4de0f2dd2e910ec05d24af580cba32626..242feb92ec43768f37117134330d371396b58d61 100644 (file)
lbco &TEMP_REG_2.w2, ICSS_SHARED_RAM_CONST, DEVICE_OUTDATA_FRAME_BUFFER_SIZE, 2\r
\r
; OFFSET_IN_PTR (7,8)\r
+ sbco &L2_OFFSET_IN_PTR, ICSS_SHARED_RAM_CONST, TTS_BSPD, 2 ;store number of bytes send by previous devices. This is used by TTS in IOEX\r
;add L2_OFFSET_IN_PTR, L2_OFFSET_IN_PTR, INPUT_BYTES_COUNT\r
add L2_OFFSET_IN_PTR, L2_OFFSET_IN_PTR, TEMP_REG_2.w0\r
mov OFFSET_IN_PTR, L2_OFFSET_IN_PTR\r
diff --git a/examples/am243x/SORTE_G/SORTE_g_device/event_handler_g.asm b/examples/am243x/SORTE_G/SORTE_g_device/event_handler_g.asm
index 53c86b91a04bb1d46e8d965ded5cf00b84d8f792..85e0646fa21e6657bd7a5066e3af2389fb701127 100644 (file)
qbeq EVH_MDIO_EVENT_PEND, TEMP_REG_6, SYS_EVT_MDIO_MII_LINK0\r
qbeq EVH_TX_FIFO_OVERFLOW, TEMP_REG_6, SYS_EVT_PORT0_TX_OVERFLOW\r
qbeq EVH_TX_FIFO_OVERFLOW, TEMP_REG_6, SYS_EVT_PORT1_TX_OVERFLOW\r
- qbeq EVH_TX_FIFO_OVERFLOW, TEMP_REG_6, SYS_EVT_PORT0_TX_UNDERFLOW\r
- qbeq EVH_TX_FIFO_OVERFLOW, TEMP_REG_6, SYS_EVT_PORT1_TX_UNDERFLOW\r
+ qbeq EVH_TX_FIFO_UNDERFLOW, TEMP_REG_6, SYS_EVT_PORT0_TX_UNDERFLOW\r
+ qbeq EVH_TX_FIFO_UNDERFLOW, TEMP_REG_6, SYS_EVT_PORT1_TX_UNDERFLOW\r
qbeq EVH_PRU2PRU_EVT1_PEND, TEMP_REG_6, PRU2PRU_EVT1\r
qbeq EVH_PRU2PRU_EVT2_PEND, TEMP_REG_6, PRU2PRU_EVT2\r
\r
diff --git a/examples/am243x/SORTE_G/SORTE_g_device/ioex_g.asm b/examples/am243x/SORTE_G/SORTE_g_device/ioex_g.asm
index f253daa8a29515a1b1a8154b7674250b1a36ae03..31a1e75e8c493eb7bbe8f705e537b3fd3b9cd2d5 100644 (file)
.global TSK_IOEX_STATE_FWD_BKN
.global TSK_IOEX_STATE_CMP0_EVENT
- .global TSK_IOEX_STATE_TTS_COMPLETE_EVENT
+ .global TSK_IOEX_STATE_TTS_START_EVENT
.global TSK_IOEX_STATE_FWD_SOF
.global TSK_IOEX_STATE_FWD_EOF
ldi R30.w0, 0x5555
ldi R30.w0, 0xd555
mov R30.b0, DEVICE_ADDR ; This adds 1 additional byte to INPUT_BYTES_COUNT
+ mov R30.b1, DEVICE_STATUS
; Load the device input byte from memory
-; Check if length is >26 byte
+; Check if length is >24 byte
;ldi R0.w0, INPUT_BYTES_COUNT
- ldi R0.w0, 0
- lbco &R0.b0, ICSS_SHARED_RAM_CONST, DEVICE_INDATA_FRAME_BUFFER_SIZE, 1
- qbgt IOEX_CMP0_LOAD_DATA, R0.w0, 26
+ lbco &R0.w0, ICSS_SHARED_RAM_CONST, DEVICE_INDATA_FRAME_BUFFER_SIZE, 2
+ mov R0.w2, R0.w0 ; copy byte count to second register
+ qbgt IOEX_CMP0_LOAD_DATA, R0.w0, IOEX_TTS_PACKET_SIZE-8 ;
;IOEX_CMP0_MULTI_PAKET:
- ldi R0.w0, 26 ; if INPUT_BYTES_COUNT length >26, we push data to TX FIFO multiple times
+ ldi R0.w0, IOEX_TTS_PACKET_SIZE-8 ; if INPUT_BYTES_COUNT length >IOEX_TTS_PACKET_SIZE (24), we push data to TX FIFO multiple times
IOEX_CMP0_LOAD_DATA:
; load payload from PRU data memory
ldi TEMP_REG_1.w0, DEVICE_INDATA_FRAME_BUFFER_PTR
lbco &TEMP_REG_1.w0, ICSS_SHARED_RAM_CONST, TEMP_REG_1.w0, 2
lbco &R2.b0, PRU1_DMEM_CONST, TEMP_REG_1.w0, b0
ldi R1.b0, &R2.b0
- loop IOEX_CMP0_SEND, R0.b0
+ qbbc IOEX_SEND_WORDS, R0.b0, 0 ;check if byte count is odd
mvib TX_DATA_BYTE, *R1.b0++
- nop ; DevNote: NOP?
+; nop
+IOEX_SEND_WORDS:
+ lsr R0.b0, R0.b0, 1 ; divide byte count by 2
+ loop IOEX_CMP0_SEND, R0.b0
+ mviw TX_DATA_WORD, *R1.b0++
+; nop ; DevNote: NOP?
IOEX_CMP0_SEND:
- ; generate CRC and TX_EOF if INPUT_BYTES_COUNT <=26
- qblt IOEX_CMP0_NO_CRC, R0.w0, 26
+ ; generate CRC and TX_EOF if INPUT_BYTES_COUNT <=24
+ qblt IOEX_CMP0_NO_CRC, R0.w2, IOEX_TTS_PACKET_SIZE-8
; push CRC32
M_CMD16 (D_PUSH_CRC_MSWORD_CMD | D_PUSH_CRC_LSWORD_CMD | D_TX_EOF)
IOEX_CMP0_NO_CRC:
; TSK_IOEX_STATE_TTS_COMPLETE_EVENT
;****************************
; triggered by CMP3/4 (TTS) event
-TSK_IOEX_STATE_TTS_COMPLETE_EVENT:
+TSK_IOEX_STATE_TTS_START_EVENT:
.if $defined(PRU0)
xout BANK0_ID, &r0, RANGE_R0_R19 ; save r0 - r19
.else
xout BANK1_ID, &r0, RANGE_R0_R19 ; save r0 - r19
.endif
- ; init previous FIFO level to -1
- ldi TEMP_REG_1.b1, 0xff
- ; init TX byte counter
- ;ldi R1.w0, INPUT_BYTES_COUNT
- ldi R1.w0, 0
- lbco &R0.b0, ICSS_SHARED_RAM_CONST, DEVICE_INDATA_FRAME_BUFFER_SIZE, 1
- ldi R1.w2, 26 ; 26 bytes are already in the TX FIFO
+ ; loading number of bytes to transmit
+ lbco &R0.w0, ICSS_SHARED_RAM_CONST, DEVICE_INDATA_FRAME_BUFFER_SIZE, 2
+ ; if number of bytest to transmit is <= 24, packet and CRC was already pushed into TX FIFO at CMP0 task
+ qbge IOEX_TTS_COMPLETE, R0.w0, IOEX_TTS_PACKET_SIZE-8
+
+ ; calculate the loop for transmitting 32 byte chunks
+ sub R0.w0, R0.w0, IOEX_TTS_PACKET_SIZE - 8 ; this #of bytes amount was was already pushed into TX FIFO at CMP0 task
+ mov R0.w2, R0.w0; backup the remaining packet size
+ qbgt IOEX_TTS_SEND_LESS_Check, R0.w0, 32; Check if the remaining bytes to send is less than 32 or not?
+
+ ; TEMP_REG_1.w0 is the pointer to the data in shared memory
+ ldi TEMP_REG_1.w0, DEVICE_INDATA_FRAME_BUFFER_PTR
+ lbco &TEMP_REG_1.w0, ICSS_SHARED_RAM_CONST, TEMP_REG_1.w0, 2
+ add TEMP_REG_1.w0, TEMP_REG_1.w0, IOEX_TTS_PACKET_SIZE-8
+ lsr R0.b0, R0.w0, 5; divide by 32
+
+ ; start the loop for pushing 32 bytes of chunks to FIFO here
+IOEX_TTS_TX_LOOP:
+ qbeq IOEX_TTS_SEND_LESS_Check, R0.b0, 0 ; If the counter is zero goto check the remainig bytes to sent
+ sub R0.b0, R0.b0, 1
+ lbco &R2.b0, PRU1_DMEM_CONST, TEMP_REG_1.w0, 32
+ add TEMP_REG_1.w0, TEMP_REG_1.w0, 32; update the pointer to load next 32 chunks of data in shared memory
+ ldi R1.b0, &R2.b0
+
+ ldi TEMP_REG_2.b1, 0xff; Initialize the previous FIFO level to -1
IOEX_TTS_COMPLETE_CHECK_TXFIFOLEVEL:
.if $defined(PRU0)
- lbco &TEMP_REG_1.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL1, 1
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL1, 1 ; FIFO level is in nibbles (4-bits)
.else
- lbco &TEMP_REG_1.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL0, 1
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL0, 1
.endif
- qbeq IOEX_TTS_TIMEOUT, TEMP_REG_1.b0, TEMP_REG_1.b1 ; when new FIFO level does not increase, we detected a stuck -> update statistics and exit this function
- mov TEMP_REG_1.b1, TEMP_REG_1.b0
-
- qble IOEX_TTS_MULTI_FIFO_FILL, R1.w0, 26
- ; byte to transmit <=26 bytes: single FIFO fill in CMP0
- qbne IOEX_TTS_COMPLETE_CHECK_TXFIFOLEVEL, TEMP_REG_1.b0, 0
- qba IOEX_TTS_COMPLETE
-
-; multi FIFO fill
-IOEX_TTS_MULTI_FIFO_FILL:
- qble IOEX_TTS_COMPLETE_CHECK_TXFIFOLEVEL, TEMP_REG_1.b0, 40-16-4 ; 40 bytes FIFO, 16 bytes data, 4 bytes CRC
- ; load next 16 bytes
- sub R0.b0, R1.w0, R1.w2
- qble IOEX_TTS_MULTI_CHECK_ALL_BYTES_SENT, R0.b0, 16
- ldi R0.w0, 16 ; more than 16 bytes to sent, limit next send to 16 bytes
-IOEX_TTS_MULTI_CHECK_ALL_BYTES_SENT:
- qbne IOEX_TTS_MULTI_LOAD_DATA, R1.w0, R1.w2
- ; all bytes sent, wait for TXFIFO empty
- qbne IOEX_TTS_COMPLETE_CHECK_TXFIFOLEVEL, TEMP_REG_1.b0, 0
- qba IOEX_TTS_COMPLETE
-
-IOEX_TTS_MULTI_LOAD_DATA:
-; load payload from PRU data memory
- ldi TEMP_REG_1.w0, DEVICE_INDATA_FRAME_BUFFER_PTR
- lbco &TEMP_REG_1.w0, ICSS_SHARED_RAM_CONST, TEMP_REG_1.w0, 2
- lbco &R2.b0, PRU1_DMEM_CONST, TEMP_REG_1.w0, b0
+ qbeq IOEX_TTS_RECONFIGURE_MIIRT, TEMP_REG_2.b0, TEMP_REG_2.b1; Compare the current FIFO level with previous FIFO level, If they are equal, exit from loading data
+ mov TEMP_REG_2.b1, TEMP_REG_2.b0; Update the current FIFO level
+ qble IOEX_TTS_COMPLETE_CHECK_TXFIFOLEVEL, TEMP_REG_2.b0, (40-32)*2 ; 1 byte is 2 nibbles
+ loop IOEX_TTS_FIFO_FILL, 32/4
+ mvid TX_DATA_DOUBLE, *R1.b0++
+IOEX_TTS_FIFO_FILL:
+ qbne IOEX_TTS_TX_LOOP, R0.b0, 0
+ ; e/o 32 byte chunk transmission
+
+; now transmit bytes <32 bytes
+IOEX_TTS_SEND_LESS_Check:
+ ldi TEMP_REG_2.b1, 0xff; Initialize the previous FIFO level to -1
+ AND R0.b0, R0.w2, 0x1F
+ qbeq IOEX_TTS_TRANSMIT_CRC, R0.b0, 0
+ ; load the remaining bytes to registers
+ lbco &R2.b0, PRU1_DMEM_CONST, TEMP_REG_1.w0, b0
ldi R1.b0, &R2.b0
- loop IOEX_TTS_MULTI_SEND, R0.b0
+;IOEX_TTS_PUSH_8:
+ qbbc IOEX_TTS_PUSH_16, R0.b0, 0
mvib TX_DATA_BYTE, *R1.b0++
- nop ; DevNote: NOP needed?
-IOEX_TTS_MULTI_SEND:
- add R1.w0, R1.w0, R0.b0
- ; check if this is the last part of data: if yes, CRC/TX_EOF has to be generated.
- qbne IOEX_TTS_COMPLETE_CHECK_TXFIFOLEVEL, R1.w0, R1.w2
-
-IOEX_TTS_MULTI_CRC:
+IOEX_TTS_PUSH_16:
+ qbbc IOEX_TTS_PUSH_32, R0.b0, 1
+ mviw TX_DATA_WORD, *R1.b0++
+IOEX_TTS_PUSH_32:
+ lsr R0.b0, R0.b0, 2
+ qbeq IOEX_TTS_TRANSMIT_CRC, R0.b0, 0
+IOEX_TTS_PUSH_REMAINDER_CHECK_TXFIFOLEVEL:
+ .if $defined(PRU0)
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL1, 1 ; FIFO level is in nibbles (4-bits)
+ .else
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL0, 1
+ .endif
+ qbeq IOEX_TTS_RECONFIGURE_MIIRT, TEMP_REG_2.b0, TEMP_REG_2.b1; Compare the current FIFO level with previous FIFO level, If they are equal, exit from loading data
+ mov TEMP_REG_2.b1, TEMP_REG_2.b0; Update the current FIFO level
+ qble IOEX_TTS_PUSH_REMAINDER_CHECK_TXFIFOLEVEL, TEMP_REG_2.b0, (40-28)*2 ;Check for FIFO level (31 bytes is the maximum, and 3 bytes will be transmitted above -> max leftover bytes is 28)
+ loop IOEX_TTS_TRANSMIT_CRC, R0.b0
+ mvid TX_DATA_DOUBLE, *R1.b0++
+
+IOEX_TTS_TRANSMIT_CRC:
+ ldi TEMP_REG_2.b1, 0xff; Initialize the previous FIFO level to -1
+IOEX_TTS_TRANSMIT_CRC1:
+ .if $defined(PRU0)
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL1, 1
+ .else
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL0, 1
+ .endif
+ qbeq IOEX_TTS_RECONFIGURE_MIIRT, TEMP_REG_2.b0, TEMP_REG_2.b1; Compare the current FIFO level with previous FIFO level, If they are equal, exit from loading data
+ mov TEMP_REG_2.b1, TEMP_REG_2.b0; Update the current FIFO level
+ qble IOEX_TTS_TRANSMIT_CRC1, TEMP_REG_2.b0, (40-4-1)*2 ; don't fill 40 bytes max into the TX FIFO, hence we add 1 saftey byte
M_CMD16 (D_PUSH_CRC_MSWORD_CMD | D_PUSH_CRC_LSWORD_CMD | D_TX_EOF)
- qba IOEX_TTS_COMPLETE_CHECK_TXFIFOLEVEL
-IOEX_TTS_TIMEOUT:
- lbco &TEMP_REG_1.w0, ICSS_SHARED_RAM_CONST, TTS_TIMEOUT_COUNT, 2
- add TEMP_REG_1.w0, TEMP_REG_1.w0, 1
- sbco &TEMP_REG_1.w0, ICSS_SHARED_RAM_CONST, TTS_TIMEOUT_COUNT, 2
IOEX_TTS_COMPLETE:
+ ; no need to re-initialzie FIFO LEVEL temp register
+ .if $defined(PRU0)
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL1, 1
+ .else
+ lbco &TEMP_REG_2.b0, ICSS_MII_RT_CONST, ICSS_MIIRT_TX_FIFO_LEVEL0, 1
+ .endif
+ qbeq IOEX_TTS_RECONFIGURE_MIIRT, TEMP_REG_2.b0, TEMP_REG_2.b1; Compare the current FIFO level with previous FIFO level, If they are equal, exit from loading data
+ mov TEMP_REG_2.b1, TEMP_REG_2.b0; Update the current FIFO level
+ qbne IOEX_TTS_COMPLETE, TEMP_REG_2.b0, 0 ; wait for TX FIFO is empty and packet is sent before reconfiguring MII_RT to fast forward
+
+IOEX_TTS_RECONFIGURE_MIIRT:
; configure local port to AF
M_SET_MIIRT_AF_LOCAL
; reset RX- and TX-FIFO and clear TX errors
diff --git a/examples/am243x/SORTE_G/SORTE_g_device/sync_g.asm b/examples/am243x/SORTE_G/SORTE_g_device/sync_g.asm
index 130816ca96f6adbc181f2965c1fcbb488684e894..f447676f46989ced80233ca4ab28b2367108abf3 100644 (file)
; threshold value if >= xx\r
;qbge SYNC_HANDLER_AVERAGE_DONE, TEMP_REG_2, 11\r
mov TEMP_REG_4, TEMP_REG_2\r
- qbge sync_debug_update_buffer, TEMP_REG_2, 11\r
+ qbge sync_debug_update_buffer, TEMP_REG_2, 3\r
; limit compensation value to 4; When compensation <30, then use delta time\r
;qble SYNC_HANDLER_SET_COMP, TEMP_REG_2, 30\r
- ldi TEMP_REG_2.w0, 3\r
+ ;ldi TEMP_REG_2.w0, 3\r
\r
; filter\r
;lsr TEMP_REG_2, TEMP_REG_2, 2\r
diff --git a/examples/am243x/SORTE_G/SORTE_g_device/task_manager.asm b/examples/am243x/SORTE_G/SORTE_g_device/task_manager.asm
index d498768df4e4071a5dd2fe0fa35ba651fc124f2b..944f4b13cc77d8b47c01c660ceed484131fcc4b0 100644 (file)
.global TSK_IOEX_STATE_FWD_BKN\r
.global TSK_IOEX_STATE_FWD_EOF\r
.global TSK_IOEX_STATE_CMP0_EVENT\r
- .global TSK_IOEX_STATE_TTS_COMPLETE_EVENT\r
+ .global TSK_IOEX_STATE_TTS_START_EVENT\r
\r
.global FN_TASK_MANAGER_SETUP\r
\r
; set task entry pointers\r
ldi TEMP_REG_3.w0, $CODE(TSK_IOEX_STATE_CMP0_EVENT)\r
sbbo &TEMP_REG_3.w0, TEMP_REG_2, CSL_ICSS_G_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR_TS1_PC_S0, 2\r
- ldi TEMP_REG_3.w0, $CODE(TSK_IOEX_STATE_TTS_COMPLETE_EVENT)\r
+ ldi TEMP_REG_3.w0, $CODE(TSK_IOEX_STATE_TTS_START_EVENT)\r
sbbo &TEMP_REG_3.w0, TEMP_REG_2, CSL_ICSS_G_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR_TS1_PC_S1, 2\r
\r
; wait for IEP warp-around to reconfigure ports\r
lbco &TEMP_REG_1, ICSS_SHARED_RAM_CONST, TEMP_REG_1.w2, 4;\r
;sub TEMP_REG_1, TEMP_REG_1, 4 ; adjust by 4ns as IEP starts from 0 / wrap-around\r
sbco &TEMP_REG_1, ICSS_IEP_CONST, ICSS_IEP_CMP0_REG, 4\r
- ; configure TTS tigger - all devices start at 500ns\r
- ldi32 TEMP_REG_1, 500\r
- ;qbeq TMG_IOEX_TTS_WRITE_IEP, DEVICE_ADDR, 1\r
- ;lbco &TEMP_REG_2.w0, ICSS_SHARED_RAM_CONST, LINE_DELAY_PREVIOUS, 2\r
- ; DEBUG\r
- ;ldi TEMP_REG_1, 800\r
- ;add TEMP_REG_1, TEMP_REG_1, TEMP_REG_2.w0\r
+ ; configure TTS tigger\r
+ lbco &TEMP_REG_2.w0, ICSS_SHARED_RAM_CONST, TTS_BSPD, 2; load in data bytes sent by previous devices\r
+ ldi TEMP_REG_1, 500\r
+ qbge TMG_IOEX_TTS_WRITE_IEP, TEMP_REG_2.w0, IOEX_TTS_BSPD_LIMIT\r
+ ; calculate TTS based on data bytes send by previous devices\r
+ sub TEMP_REG_2.w0, TEMP_REG_2.w0, IOEX_TTS_BSPD_LIMIT\r
+ lsl TEMP_REG_2, TEMP_REG_2.w0, 3\r
+ add TEMP_REG_1, TEMP_REG_1, TEMP_REG_2\r
+ add TEMP_REG_1, TEMP_REG_1, BRIDGE_DELAY_SYNC_IOEX\r
\r
TMG_IOEX_TTS_WRITE_IEP:\r
.if $defined(PRU0)\r
sbco &TEMP_REG_1, ICSS_IEP_CONST, ICSS_IEP_CMP3_REG, 4\r
.endif\r
\r
-\r
; set SYNC0 pulse width\r
ldi TEMP_REG_1.w2, 125 ; 500ns = 125 * 4ns\r
ldi TEMP_REG_2.w0, ICSS_IEP_SYNC_PWIDTH_REG\r
\r
;DevNote: Clarify if e/o block is needed to receive the remaining bytes\r
;M_DISABLE_TXL2 ; disabling TXL2 not needed as state before does not use TXL2.\r
+ ;M_ENABLE_TXL2\r
M_SET_MIIRT_AF_LOCAL_IOEX\r
; last slave needs specific configuration\r
qbbc TMG_DONE, DEVICE_STATUS, LAST_DEVICE_FLAG\r
diff --git a/examples/am243x/SORTE_G/SORTE_g_master_AM243x/.cproject b/examples/am243x/SORTE_G/SORTE_g_master_AM243x/.cproject
index ed10d636ec1ae22b5549cd465fe2955c681b3a67..c62f9f38945ca1cd326885ab3e90bd2992b4fc19 100644 (file)
<option id="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.DISPLAY_ERROR_NUMBER.1474742997" name="Emit diagnostic identifier numbers (--display_error_number)" superClass="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
<option id="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.XML_LINK_INFO.4489320" name="Detailed link information data-base into <file> (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.XML_LINK_INFO" value="${ProjName}_linkInfo.xml" valueType="string"/>
<option id="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.INITIALIZATION_MODEL.427274841" name="Initialization model" superClass="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.INITIALIZATION_MODEL" value="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.INITIALIZATION_MODEL._none" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.ENTRY_POINT.1130408563" superClass="com.ti.ccstudio.buildDefinitions.PRU_2.3.linkerID.ENTRY_POINT" value="main" valueType="string"/>
<inputType id="com.ti.ccstudio.buildDefinitions.PRU_2.3.exeLinker.inputType__CMD_SRCS.107787761" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.PRU_2.3.exeLinker.inputType__CMD_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.PRU_2.3.exeLinker.inputType__CMD2_SRCS.1215756115" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.PRU_2.3.exeLinker.inputType__CMD2_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.PRU_2.3.exeLinker.inputType__GEN_CMDS.98880091" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.PRU_2.3.exeLinker.inputType__GEN_CMDS"/>
diff --git a/examples/am243x/SORTE_G/SORTE_g_master_AM243x/main_PRU0.asm b/examples/am243x/SORTE_G/SORTE_g_master_AM243x/main_PRU0.asm
index 0d3f1226fbadc56cea8ca562853876a7041e4e24..7107ec481241b6ac38a5aefa684c9f0fcae5891f 100644 (file)
add r1.w0, r1.w0, CTRL_REG_OFFSET
sbco &r1.b2, ICSS_DMEM0_CONST, r1.w0, 1
-; set cycle time to 10 us
+; set cycle time: time in ns - 1 IEP clock
; Save the Calculated Cycle Time in Device Data Memory
- ldi32 TEMP_REG_1, 3996
+ ;ldi32 TEMP_REG_1, 3996
+ ldi32 TEMP_REG_1, 10000-4
ldi TEMP_REG_2.w0, SORTE_REG_INTERFACE
add TEMP_REG_2.w0, TEMP_REG_2.w0, PARAM_DATA_OFFSET
sbco &TEMP_REG_1, ICSS_DMEM0_CONST, TEMP_REG_2.w0, 4
sbco &r2.b0, ICSS_MII_RT_CONST, CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_RX_FRMS0, 1
sbco &r2.b0, ICSS_MII_RT_CONST, CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_RX_FRMS1, 1
-; test if there is an active link on the port
-
-; test if there is an active link on the port using mdio interface
-; ldi TEMP_REG_2.w0, MDIO_PHY_CONFIG_OFFSET
-; lbco &TEMP_REG_2.w0, C28, TEMP_REG_2.w0, 2
LED_SET_STAT_RED:
ldi32 TEMP_REG_1, 0x00601040
sbbo &TEMP_REG_2, TEMP_REG_1, 4, 4
IDLE_WAIT_FOR_LINK_ACTIVE:
- lbco &TEMP_REG_1.b0, ICSS_MDIO_CONST, ICSS_MDIO_LINK, 1
+; test if there is an active link on the port
+
+; test if there is an active link on the port using mdio interface
+ ldi TEMP_REG_2.w0, MDIO_PHY_CONFIG_OFFSET
+ lbco &TEMP_REG_2.w0, C28, TEMP_REG_2.w0, 2
+
+ lbco &TEMP_REG_1.w0, ICSS_MDIO_CONST, ICSS_MDIO_LINK, 2
; update to fit phy address
- qbbc IDLE_WAIT_FOR_LINK_ACTIVE,TEMP_REG_1.b0, 3
-; qbbc IDLE_WAIT_FOR_LINK_ACTIVE,TEMP_REG_1.b0, TEMP_REG_2.b0
+; qbbc IDLE_WAIT_FOR_LINK_ACTIVE,TEMP_REG_1.b0, 3
+ qbbc IDLE_WAIT_FOR_LINK_ACTIVE,TEMP_REG_1.w0, TEMP_REG_2.b1
; check if enabled, enabling done at startup of pru firmware.
lbco &TEMP_REG_1.b0, ICSS_DMEM0_CONST, CTRL_REG_OFFSET , 1
diff --git a/examples/am243x/SORTE_G/include/icss/icss_miirt_macros.inc b/examples/am243x/SORTE_G/include/icss/icss_miirt_macros.inc
index b93e93f5ca769487bd467e749ef6f4bf2b2aee73..bb8fc02d5d7c820e9b082f317e29e2fbacf9689a 100644 (file)
.if ! $defined (__icss_macros_inc)\r
.define "1", __icss_macros_inc\r
\r
+ .asg R30, TX_DATA_DOUBLE\r
.asg R30.w0, TX_DATA_WORD\r
.asg R30.b0, TX_DATA_BYTE\r
.asg R30.w2, TX_DATA_WORD_MASK\r
diff --git a/examples/am243x/SORTE_G/include/protocol/sorte_g_device_cfg.inc b/examples/am243x/SORTE_G/include/protocol/sorte_g_device_cfg.inc
index 39fc1de524cda10a640d94e9eb21e02ef59e3c0e..94f4be744fc09d32f84829ed9e70ecfc598a22dc 100644 (file)
BRIDGE_DELAY_SYNC_IOEX .set 160 ; 0x14 in TXCFG START DELAY - 160ns ; (80ns + 2x40 L0 FIFO); measured jitter from 156 - 168ns\r
TTS_GUARD_DELAY .set 35\r
IEP_RW_ACCESS_CONST .set 15 ; read/write access to IEP timer\r
+IOEX_TTS_PACKET_SIZE .set 32 ; numbers of bytes that are pushed into the TX L1 FIFO during IO_EX\r
+IOEX_TTS_BSPD_LIMIT .set 40\r
\r
CYCLE_TIME_10US .set 10000 ; 10 usec cuycle time value\r
\r
diff --git a/examples/am243x/SORTE_G/include/protocol/sorte_g_host_interface.inc b/examples/am243x/SORTE_G/include/protocol/sorte_g_host_interface.inc
index 9d5704ec2e6d9feb9c76c26eeae047add0e40e32..09417ebbeed1d9ddee909d379faf022a7039582f 100644 (file)
DEBUG_PRU0_SLAVE_STATE .set 0x0032 ; .field8
DEBUG_PRU1_SLAVE_STATE .set 0x0033 ; .field8
-DEBUG_OFFSET_IN_PTR .set 0x0034 ; .field16
-DEBUG_OFFSET_OUT_PTR .set 0x0036 ; .field16
+TTS_BSPD .set 0x0034 ; .field16 ; bytes send by previous devices, used for TTS calculation in IOEX
SYNC_DELAY_1ST .set 0x0038 ; .field16
DEBUG_BUFFER_OFFSET .set 0x003A ; .field 16
diff --git a/examples/am243x/SORTE_G/include/sorte_g_device_host_interface.h b/examples/am243x/SORTE_G/include/sorte_g_device_host_interface.h
index 05f971dbcdc1adda4ad168f901ef59369380a6b1..c00065d3b5f8bbd1a2a4f24f57cb1b1398b397d8 100644 (file)
#define DEVICE_IOEX_DATA_FRAME_BUFFER_BASE 0x0000 //
#define DEVICE_INDATA_FRAME_BUFFER_LOCATION 0x0000 // INDATA -> slave to master data
-#define DEVICE_OUTDATA_FRAME_BUFFER_LOCATION 0x0040 // OUTDATA -> master to slave data
-#define DEVICE_MASTER_FRAME_BUFFER_LOCATION 0x0080 // frame buffer for the master frame
+#define DEVICE_OUTDATA_FRAME_BUFFER_LOCATION 0x0100 // OUTDATA -> master to slave data
+#define DEVICE_MASTER_FRAME_BUFFER_LOCATION 0x0180 // frame buffer for the master frame
#define DEVICE_ADDR_OFFSET 0x0024 // .field8