summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 4efd227)
raw | patch | inline | side by side (parent: 4efd227)
| author | Jason Reeder <jreeder@ti.com> | |
| Wed, 24 May 2017 18:12:33 +0000 (13:12 -0500) | ||
| committer | Jason Reeder <jreeder@ti.com> | |
| Wed, 24 May 2017 18:12:33 +0000 (13:12 -0500) |
Pulling the latest changes from the TRM into the pru_uart.h
header file for the AM572x 2.0 device.
Signed-off-by: Jason Reeder <jreeder@ti.com>
header file for the AM572x 2.0 device.
Signed-off-by: Jason Reeder <jreeder@ti.com>
| include/am572x_2_0/pru_uart.h | patch | blob | history |
index 2c63b8841be4839b6dc53e2e984e414f681fb8b0..1eea30fd9abef6e4d21263131a25a5167f65ced9 100644 (file)
/*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
#ifndef _PRU_UART_H_
#define _PRU_UART_H_
-/* UART Register set */
+/* PRU UART register set */
typedef struct {
- /* PRU_UART_RBR_TBR register bit field */
+ /* PRU_UART_RBR_THR_REGISTERS register bit field */
union {
- volatile uint32_t RBR_TBR;
+ volatile uint32_t RBR_THR_REGISTERS;
volatile struct {
- unsigned RBR_DATA : 8; // 7:0
- unsigned TBR_DATA : 10; // 17:8
- unsigned rsvd18 : 14; // 31:18
- } RBR_TBR_bit;
- }; // 0x0
+ uint32_t DATA : 8; // 7:0
+ uint32_t rsvd8 : 24; // 31:8
+ } RBR_THR_REGISTERS_bit;
+ }; // 0x0
-
- /* PRU_UART_IER register bit field */
+ /* PRU_UART_INTERRUPT_ENABLE_REGISTER register bit field */
union {
- volatile uint32_t IER;
+ volatile uint32_t INTERRUPT_ENABLE_REGISTER;
volatile struct {
- unsigned ERBI : 1; // 0
- unsigned ETBEI : 1; // 1
- unsigned ELSI : 1; // 2
- unsigned EDSSI : 1; // 3
- unsigned rsvd4 : 28; // 31:4
- } IER_bit;
- }; // 0x4
-
- /* PRU_UART_IIR_FCR register bit field */
+ uint32_t ERBI : 1; // 0
+ uint32_t ETBEI : 1; // 1
+ uint32_t ELSI : 1; // 2
+ uint32_t EDSSI : 1; // 3
+ uint32_t rsvd4 : 28; // 31:4
+ } INTERRUPT_ENABLE_REGISTER_bit;
+ }; // 0x4
+
+ /* PRU_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER register bit field */
union {
- volatile uint32_t IIR_FCR;
+ volatile uint32_t INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER;
volatile struct {
- unsigned IIR_IPEND : 1; // 0
- unsigned IIR_INTID : 3; // 3:1
- unsigned rsvd4 : 2; // 5:4
- unsigned IIR_FIFOEN : 2; // 7:6
- unsigned FCR_FIFOEN : 1; // 8
- unsigned FCR_RXCLR : 1; // 9
- unsigned FCR_TXCLR : 1; // 10
- unsigned FCR_DMAMODE1 : 1; // 11
- unsigned rsvd12 : 2; // 13:12
- unsigned FCR_RXFIFTL : 2; // 15:14
- unsigned rsvd16 : 16; // 31:16
- } IIR_FCR_bit;
- }; // 0x8
-
- /* PRU_UART_LCR register bit field */
+ uint32_t IPEND_FIFOEN : 1; // 0
+ uint32_t INTID : 3; // 3:1
+ uint32_t rsvd4 : 2; // 5:4
+ uint32_t FIFOEN_RXFIFTL : 2; // 7:6
+ uint32_t rsvd8 : 24; // 31:8
+ } INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER_bit;
+ }; // 0x8
+
+ /* PRU_UART_LINE_CONTROL_REGISTER register bit field */
union {
- volatile uint32_t LCR;
+ volatile uint32_t LINE_CONTROL_REGISTER;
volatile struct {
- unsigned WLS0 : 1; // 0
- unsigned WLS1 : 1; // 1
- unsigned STB : 1; // 2
- unsigned PEN : 1; // 3
- unsigned EPS : 1; // 4
- unsigned SP : 1; // 5
- unsigned BC : 1; // 6
- unsigned DLAB : 1; // 7
- unsigned rsvd8 : 24; // 31:8
- } LCR_bit;
- }; // 0xC
-
- /* PRU_UART_MCR register bit field */
+ uint32_t WLS : 2; // 1:0
+ uint32_t STB : 1; // 2
+ uint32_t PEN : 1; // 3
+ uint32_t EPS : 1; // 4
+ uint32_t SP : 1; // 5
+ uint32_t BC : 1; // 6
+ uint32_t DLAB : 1; // 7
+ uint32_t rsvd8 : 24; // 31:8
+ } LINE_CONTROL_REGISTER_bit;
+ }; // 0xc
+
+ /* PRU_UART_MODEM_CONTROL_REGISTER register bit field */
union {
- volatile uint32_t MCR;
+ volatile uint32_t MODEM_CONTROL_REGISTER;
volatile struct {
- unsigned rsvd0 : 1; // 0
- unsigned RTS : 1; // 1
- unsigned OUT1 : 1; // 2
- unsigned OUT2 : 1; // 3
- unsigned LOOP : 1; // 4
- unsigned AFE : 1; // 5
- unsigned rsvd8 : 26; // 31:6
- } MCR_bit;
- }; // 0x10
-
- /* PRU_UART_LSR register bit field */
+ uint32_t rsvd0 : 1; // 0
+ uint32_t RTS : 1; // 1
+ uint32_t OUT1 : 1; // 2
+ uint32_t OUT2 : 1; // 3
+ uint32_t LOOP : 1; // 4
+ uint32_t AFE : 1; // 5
+ uint32_t rsvd6 : 26; // 31:6
+ } MODEM_CONTROL_REGISTER_bit;
+ }; // 0x10
+
+ /* PRU_UART_LINE_STATUS_REGISTER register bit field */
union {
- volatile uint32_t LSR;
+ volatile uint32_t LINE_STATUS_REGISTER;
volatile struct {
- unsigned DR : 1; // 0
- unsigned OE : 1; // 1
- unsigned PE : 1; // 2
- unsigned FE : 1; // 3
- unsigned BI : 1; // 4
- unsigned THRE : 1; // 5
- unsigned TEMT : 1; // 6
- unsigned RXFIFOE : 1; // 7
- unsigned rsvd8 : 24; // 31:8
- } LSR_bit;
- }; // 0x14
-
- /* PRU_UART_MSR register bit field */
+ uint32_t DR : 1; // 0
+ uint32_t OE : 1; // 1
+ uint32_t PE : 1; // 2
+ uint32_t FE : 1; // 3
+ uint32_t BI : 1; // 4
+ uint32_t THRE : 1; // 5
+ uint32_t TEMT : 1; // 6
+ uint32_t RXFIFOE : 1; // 7
+ uint32_t rsvd8 : 24; // 31:8
+ } LINE_STATUS_REGISTER_bit;
+ }; // 0x14
+
+ /* PRU_UART_MODEM_STATUS_REGISTER register bit field */
union {
- volatile uint32_t MSR;
+ volatile uint32_t MODEM_STATUS_REGISTER;
volatile struct {
- unsigned DCTS : 1; // 0
- unsigned DDSR : 1; // 1
- unsigned TERI : 1; // 2
- unsigned DCD : 1; // 3
- unsigned CTS : 1; // 4
- unsigned DSR : 1; // 5
- unsigned RI : 1; // 6
- unsigned CD : 1; // 7
- unsigned rsvd8 : 24; // 31:8
- } MSR_bit;
- }; // 0x18
-
- /* PRU_UART_SCR register bit field */
+ uint32_t DCTS : 1; // 0
+ uint32_t DDSR : 1; // 1
+ uint32_t TERI : 1; // 2
+ uint32_t DCD : 1; // 3
+ uint32_t CTS : 1; // 4
+ uint32_t DSR : 1; // 5
+ uint32_t RI : 1; // 6
+ uint32_t CD : 1; // 7
+ uint32_t rsvd8 : 24; // 31:8
+ } MODEM_STATUS_REGISTER_bit;
+ }; // 0x18
+
+ /* PRU_UART_SCRATCH_REGISTER register bit field */
union {
- volatile uint32_t SCR;
+ volatile uint32_t SCRATCH_REGISTER;
volatile struct {
- unsigned DATA : 8; // 7:0
- unsigned rsvd8 : 24; // 31:8
- } SCR_bit;
- }; // 0x1C
+ uint32_t SCR : 8; // 7:0
+ uint32_t rsvd8 : 24; // 31:8
+ } SCRATCH_REGISTER_bit;
+ }; // 0x1c
- /* PRU_UART_DLL register bit field */
+ /* PRU_UART_DIVISOR_REGISTER_LSB_ register bit field */
union {
- volatile uint32_t DLL;
+ volatile uint32_t DIVISOR_REGISTER_LSB_;
volatile struct {
- unsigned DLL : 8; // 7:0
- unsigned rsvd8 : 24; // 31:8
- } DLL_bit;
- }; // 0x20
+ uint32_t DLL : 8; // 7:0
+ uint32_t rsvd8 : 24; // 31:8
+ } DIVISOR_REGISTER_LSB__bit;
+ }; // 0x20
- /* PRU_UART_DLH register bit field */
+ /* PRU_UART_DIVISOR_REGISTER_MSB_ register bit field */
union {
- volatile uint32_t DLH;
+ volatile uint32_t DIVISOR_REGISTER_MSB_;
- volatile struct {
- unsigned DLH : 8; // 7:0
- unsigned rsvd8 : 24; // 31:8
- } DLH_bit;
- }; // 0x24
+ volatile struct {
+ uint32_t DLH : 8; // 7:0
+ uint32_t rsvd8 : 24; // 31:8
+ } DIVISOR_REGISTER_MSB__bit;
+ }; // 0x24
- /* PRU_UART_PID register bit field */
+ /* PRU_UART_PERIPHERAL_ID_REGISTER register bit field */
union {
- volatile uint32_t PID;
+ volatile uint32_t PERIPHERAL_ID_REGISTER;
volatile struct {
- unsigned PID : 32; // 31:0
- } PID_bit;
- }; // 0x28
+ uint32_t PID : 32; // 31:0
+ } PERIPHERAL_ID_REGISTER_bit;
+ }; // 0x28
- uint8_t rsvd2c[4]; // 0x2C - 0x2F
+ uint8_t rsvd2c[4]; // 0x2c - 0x2f
- /* PRU_UART_PWREMU_MGMT register bit field */
+ /* PRU_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER register bit field */
union {
- volatile uint32_t PWREMU_MGMT;
+ volatile uint32_t POWERMANAGEMENT_AND_EMULATION_REGISTER;
volatile struct {
- unsigned FREE : 1; // 0
- unsigned rsvd1 : 12; // 12:1
- unsigned URRST : 1; // 13
- unsigned UTRST : 1; // 14
- unsigned rsvd15 : 17; // 31:15
- } PWREMU_MGMT_bit;
- }; // 0x30
-
- /* PRU_UART_MDR register bit field */
+ uint32_t FREE : 1; // 0
+ uint32_t rsvd1 : 12; // 12:1
+ uint32_t URRST : 1; // 13
+ uint32_t UTRST : 1; // 14
+ uint32_t rsvd15 : 17; // 31:15
+ } POWERMANAGEMENT_AND_EMULATION_REGISTER_bit;
+ }; // 0x30
+
+ /* PRU_UART_MODE_DEFINITION_REGISTER register bit field */
union {
- volatile uint32_t MDR;
+ volatile uint32_t MODE_DEFINITION_REGISTER;
volatile struct {
- unsigned OSM_SEL : 1; // 0
- unsigned rsvd1 : 31; // 31:1
- } MDR_bit;
- }; // 0x34
+ uint32_t OSM_SEL : 1; // 0
+ uint32_t rsvd1 : 31; // 31:1
+ } MODE_DEFINITION_REGISTER_bit;
+ }; // 0x34
} pruUart;
volatile __far pruUart CT_UART __attribute__((cregister("PRU_UART", near), peripheral));
#endif /* _PRU_UART_H_ */
+