ARM: OMAP2+: pm33xx-core: Add cpuidle_ops for am335x/am437x
[rpmsg/hwspinlock.git] / Documentation / devicetree / bindings / arm / cpus.txt
1 =================
2 ARM CPUs bindings
3 =================
5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the Devicetree Specification, available from:
11 https://www.devicetree.org/specifications/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the Devicetree
20 Specification, with the addition:
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23   the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the Devicetree Specification,
30 requires the cpus and cpu nodes to be present and contain the properties
31 described below.
33 - cpus node
35         Description: Container of cpu nodes
37         The node name must be "cpus".
39         A cpus node must define the following properties:
41         - #address-cells
42                 Usage: required
43                 Value type: <u32>
45                 Definition depends on ARM architecture version and
46                 configuration:
48                         # On uniprocessor ARM architectures previous to v7
49                           value must be 1, to enable a simple enumeration
50                           scheme for processors that do not have a HW CPU
51                           identification register.
52                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
53                           value must be 1, that corresponds to CPUID/MPIDR
54                           registers sizes.
55                         # On ARM v8 64-bit systems value should be set to 2,
56                           that corresponds to the MPIDR_EL1 register size.
57                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
58                           in the system, #address-cells can be set to 1, since
59                           MPIDR_EL1[63:32] bits are not used for CPUs
60                           identification.
61         - #size-cells
62                 Usage: required
63                 Value type: <u32>
64                 Definition: must be set to 0
66 - cpu node
68         Description: Describes a CPU in an ARM based system
70         PROPERTIES
72         - device_type
73                 Usage: required
74                 Value type: <string>
75                 Definition: must be "cpu"
76         - reg
77                 Usage and definition depend on ARM architecture version and
78                 configuration:
80                         # On uniprocessor ARM architectures previous to v7
81                           this property is required and must be set to 0.
83                         # On ARM 11 MPcore based systems this property is
84                           required and matches the CPUID[11:0] register bits.
86                           Bits [11:0] in the reg cell must be set to
87                           bits [11:0] in CPU ID register.
89                           All other bits in the reg cell must be set to 0.
91                         # On 32-bit ARM v7 or later systems this property is
92                           required and matches the CPU MPIDR[23:0] register
93                           bits.
95                           Bits [23:0] in the reg cell must be set to
96                           bits [23:0] in MPIDR.
98                           All other bits in the reg cell must be set to 0.
100                         # On ARM v8 64-bit systems this property is required
101                           and matches the MPIDR_EL1 register affinity bits.
103                           * If cpus node's #address-cells property is set to 2
105                             The first reg cell bits [7:0] must be set to
106                             bits [39:32] of MPIDR_EL1.
108                             The second reg cell bits [23:0] must be set to
109                             bits [23:0] of MPIDR_EL1.
111                           * If cpus node's #address-cells property is set to 1
113                             The reg cell bits [23:0] must be set to bits [23:0]
114                             of MPIDR_EL1.
116                           All other bits in the reg cells must be set to 0.
118         - compatible:
119                 Usage: required
120                 Value type: <string>
121                 Definition: should be one of:
122                             "arm,arm710t"
123                             "arm,arm720t"
124                             "arm,arm740t"
125                             "arm,arm7ej-s"
126                             "arm,arm7tdmi"
127                             "arm,arm7tdmi-s"
128                             "arm,arm9es"
129                             "arm,arm9ej-s"
130                             "arm,arm920t"
131                             "arm,arm922t"
132                             "arm,arm925"
133                             "arm,arm926e-s"
134                             "arm,arm926ej-s"
135                             "arm,arm940t"
136                             "arm,arm946e-s"
137                             "arm,arm966e-s"
138                             "arm,arm968e-s"
139                             "arm,arm9tdmi"
140                             "arm,arm1020e"
141                             "arm,arm1020t"
142                             "arm,arm1022e"
143                             "arm,arm1026ej-s"
144                             "arm,arm1136j-s"
145                             "arm,arm1136jf-s"
146                             "arm,arm1156t2-s"
147                             "arm,arm1156t2f-s"
148                             "arm,arm1176jzf"
149                             "arm,arm1176jz-s"
150                             "arm,arm1176jzf-s"
151                             "arm,arm11mpcore"
152                             "arm,cortex-a5"
153                             "arm,cortex-a7"
154                             "arm,cortex-a8"
155                             "arm,cortex-a9"
156                             "arm,cortex-a12"
157                             "arm,cortex-a15"
158                             "arm,cortex-a17"
159                             "arm,cortex-a53"
160                             "arm,cortex-a57"
161                             "arm,cortex-a72"
162                             "arm,cortex-a73"
163                             "arm,cortex-m0"
164                             "arm,cortex-m0+"
165                             "arm,cortex-m1"
166                             "arm,cortex-m3"
167                             "arm,cortex-m4"
168                             "arm,cortex-r4"
169                             "arm,cortex-r5"
170                             "arm,cortex-r7"
171                             "brcm,brahma-b15"
172                             "brcm,brahma-b53"
173                             "brcm,vulcan"
174                             "cavium,thunder"
175                             "cavium,thunder2"
176                             "faraday,fa526"
177                             "intel,sa110"
178                             "intel,sa1100"
179                             "marvell,feroceon"
180                             "marvell,mohawk"
181                             "marvell,pj4a"
182                             "marvell,pj4b"
183                             "marvell,sheeva-v5"
184                             "nvidia,tegra132-denver"
185                             "nvidia,tegra186-denver"
186                             "nvidia,tegra194-carmel"
187                             "qcom,krait"
188                             "qcom,kryo"
189                             "qcom,kryo385"
190                             "qcom,scorpion"
191         - enable-method
192                 Value type: <stringlist>
193                 Usage and definition depend on ARM architecture version.
194                         # On ARM v8 64-bit this property is required and must
195                           be one of:
196                              "psci"
197                              "spin-table"
198                         # On ARM 32-bit systems this property is optional and
199                           can be one of:
200                             "actions,s500-smp"
201                             "allwinner,sun6i-a31"
202                             "allwinner,sun8i-a23"
203                             "allwinner,sun9i-a80-smp"
204                             "amlogic,meson8-smp"
205                             "amlogic,meson8b-smp"
206                             "arm,realview-smp"
207                             "brcm,bcm11351-cpu-method"
208                             "brcm,bcm23550"
209                             "brcm,bcm2836-smp"
210                             "brcm,bcm-nsp-smp"
211                             "brcm,brahma-b15"
212                             "marvell,armada-375-smp"
213                             "marvell,armada-380-smp"
214                             "marvell,armada-390-smp"
215                             "marvell,armada-xp-smp"
216                             "marvell,98dx3236-smp"
217                             "mediatek,mt6589-smp"
218                             "mediatek,mt81xx-tz-smp"
219                             "qcom,gcc-msm8660"
220                             "qcom,kpss-acc-v1"
221                             "qcom,kpss-acc-v2"
222                             "renesas,apmu"
223                             "renesas,r9a06g032-smp"
224                             "rockchip,rk3036-smp"
225                             "rockchip,rk3066-smp"
226                             "ste,dbx500-smp"
227                             "ti,am3352"
228                             "ti,am4372"
230         - cpu-release-addr
231                 Usage: required for systems that have an "enable-method"
232                        property value of "spin-table".
233                 Value type: <prop-encoded-array>
234                 Definition:
235                         # On ARM v8 64-bit systems must be a two cell
236                           property identifying a 64-bit zero-initialised
237                           memory location.
239         - qcom,saw
240                 Usage: required for systems that have an "enable-method"
241                        property value of "qcom,kpss-acc-v1" or
242                        "qcom,kpss-acc-v2"
243                 Value type: <phandle>
244                 Definition: Specifies the SAW[1] node associated with this CPU.
246         - qcom,acc
247                 Usage: required for systems that have an "enable-method"
248                        property value of "qcom,kpss-acc-v1" or
249                        "qcom,kpss-acc-v2"
250                 Value type: <phandle>
251                 Definition: Specifies the ACC[2] node associated with this CPU.
253         - cpu-idle-states
254                 Usage: Optional
255                 Value type: <prop-encoded-array>
256                 Definition:
257                         # List of phandles to idle state nodes supported
258                           by this cpu [3].
260         - capacity-dmips-mhz
261                 Usage: Optional
262                 Value type: <u32>
263                 Definition:
264                         # u32 value representing CPU capacity [4] in
265                           DMIPS/MHz, relative to highest capacity-dmips-mhz
266                           in the system.
268         - rockchip,pmu
269                 Usage: optional for systems that have an "enable-method"
270                        property value of "rockchip,rk3066-smp"
271                        While optional, it is the preferred way to get access to
272                        the cpu-core power-domains.
273                 Value type: <phandle>
274                 Definition: Specifies the syscon node controlling the cpu core
275                             power domains.
277         - dynamic-power-coefficient
278                 Usage: optional
279                 Value type: <prop-encoded-array>
280                 Definition: A u32 value that represents the running time dynamic
281                             power coefficient in units of mW/MHz/uV^2. The
282                             coefficient can either be calculated from power
283                             measurements or derived by analysis.
285                             The dynamic power consumption of the CPU  is
286                             proportional to the square of the Voltage (V) and
287                             the clock frequency (f). The coefficient is used to
288                             calculate the dynamic power as below -
290                             Pdyn = dynamic-power-coefficient * V^2 * f
292                             where voltage is in uV, frequency is in MHz.
294 Example 1 (dual-cluster big.LITTLE system 32-bit):
296         cpus {
297                 #size-cells = <0>;
298                 #address-cells = <1>;
300                 cpu@0 {
301                         device_type = "cpu";
302                         compatible = "arm,cortex-a15";
303                         reg = <0x0>;
304                 };
306                 cpu@1 {
307                         device_type = "cpu";
308                         compatible = "arm,cortex-a15";
309                         reg = <0x1>;
310                 };
312                 cpu@100 {
313                         device_type = "cpu";
314                         compatible = "arm,cortex-a7";
315                         reg = <0x100>;
316                 };
318                 cpu@101 {
319                         device_type = "cpu";
320                         compatible = "arm,cortex-a7";
321                         reg = <0x101>;
322                 };
323         };
325 Example 2 (Cortex-A8 uniprocessor 32-bit system):
327         cpus {
328                 #size-cells = <0>;
329                 #address-cells = <1>;
331                 cpu@0 {
332                         device_type = "cpu";
333                         compatible = "arm,cortex-a8";
334                         reg = <0x0>;
335                 };
336         };
338 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
340         cpus {
341                 #size-cells = <0>;
342                 #address-cells = <1>;
344                 cpu@0 {
345                         device_type = "cpu";
346                         compatible = "arm,arm926ej-s";
347                         reg = <0x0>;
348                 };
349         };
351 Example 4 (ARM Cortex-A57 64-bit system):
353 cpus {
354         #size-cells = <0>;
355         #address-cells = <2>;
357         cpu@0 {
358                 device_type = "cpu";
359                 compatible = "arm,cortex-a57";
360                 reg = <0x0 0x0>;
361                 enable-method = "spin-table";
362                 cpu-release-addr = <0 0x20000000>;
363         };
365         cpu@1 {
366                 device_type = "cpu";
367                 compatible = "arm,cortex-a57";
368                 reg = <0x0 0x1>;
369                 enable-method = "spin-table";
370                 cpu-release-addr = <0 0x20000000>;
371         };
373         cpu@100 {
374                 device_type = "cpu";
375                 compatible = "arm,cortex-a57";
376                 reg = <0x0 0x100>;
377                 enable-method = "spin-table";
378                 cpu-release-addr = <0 0x20000000>;
379         };
381         cpu@101 {
382                 device_type = "cpu";
383                 compatible = "arm,cortex-a57";
384                 reg = <0x0 0x101>;
385                 enable-method = "spin-table";
386                 cpu-release-addr = <0 0x20000000>;
387         };
389         cpu@10000 {
390                 device_type = "cpu";
391                 compatible = "arm,cortex-a57";
392                 reg = <0x0 0x10000>;
393                 enable-method = "spin-table";
394                 cpu-release-addr = <0 0x20000000>;
395         };
397         cpu@10001 {
398                 device_type = "cpu";
399                 compatible = "arm,cortex-a57";
400                 reg = <0x0 0x10001>;
401                 enable-method = "spin-table";
402                 cpu-release-addr = <0 0x20000000>;
403         };
405         cpu@10100 {
406                 device_type = "cpu";
407                 compatible = "arm,cortex-a57";
408                 reg = <0x0 0x10100>;
409                 enable-method = "spin-table";
410                 cpu-release-addr = <0 0x20000000>;
411         };
413         cpu@10101 {
414                 device_type = "cpu";
415                 compatible = "arm,cortex-a57";
416                 reg = <0x0 0x10101>;
417                 enable-method = "spin-table";
418                 cpu-release-addr = <0 0x20000000>;
419         };
421         cpu@100000000 {
422                 device_type = "cpu";
423                 compatible = "arm,cortex-a57";
424                 reg = <0x1 0x0>;
425                 enable-method = "spin-table";
426                 cpu-release-addr = <0 0x20000000>;
427         };
429         cpu@100000001 {
430                 device_type = "cpu";
431                 compatible = "arm,cortex-a57";
432                 reg = <0x1 0x1>;
433                 enable-method = "spin-table";
434                 cpu-release-addr = <0 0x20000000>;
435         };
437         cpu@100000100 {
438                 device_type = "cpu";
439                 compatible = "arm,cortex-a57";
440                 reg = <0x1 0x100>;
441                 enable-method = "spin-table";
442                 cpu-release-addr = <0 0x20000000>;
443         };
445         cpu@100000101 {
446                 device_type = "cpu";
447                 compatible = "arm,cortex-a57";
448                 reg = <0x1 0x101>;
449                 enable-method = "spin-table";
450                 cpu-release-addr = <0 0x20000000>;
451         };
453         cpu@100010000 {
454                 device_type = "cpu";
455                 compatible = "arm,cortex-a57";
456                 reg = <0x1 0x10000>;
457                 enable-method = "spin-table";
458                 cpu-release-addr = <0 0x20000000>;
459         };
461         cpu@100010001 {
462                 device_type = "cpu";
463                 compatible = "arm,cortex-a57";
464                 reg = <0x1 0x10001>;
465                 enable-method = "spin-table";
466                 cpu-release-addr = <0 0x20000000>;
467         };
469         cpu@100010100 {
470                 device_type = "cpu";
471                 compatible = "arm,cortex-a57";
472                 reg = <0x1 0x10100>;
473                 enable-method = "spin-table";
474                 cpu-release-addr = <0 0x20000000>;
475         };
477         cpu@100010101 {
478                 device_type = "cpu";
479                 compatible = "arm,cortex-a57";
480                 reg = <0x1 0x10101>;
481                 enable-method = "spin-table";
482                 cpu-release-addr = <0 0x20000000>;
483         };
484 };
486 --
487 [1] arm/msm/qcom,saw2.txt
488 [2] arm/msm/qcom,kpss-acc.txt
489 [3] ARM Linux kernel documentation - idle states bindings
490     Documentation/devicetree/bindings/arm/idle-states.txt
491 [4] ARM Linux kernel documentation - cpu capacity bindings
492     Documentation/devicetree/bindings/arm/cpu-capacity.txt