64fc1e6aebe7fc5de7ae04b54d4e0334f0347ba5
[rpmsg/hwspinlock.git] / arch / arm / boot / dts / dra76x.dtsi
1 /*
2  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
9 #include "dra74x.dtsi"
11 / {
12         compatible = "ti,dra762", "ti,dra7";
14         ocp {
15                 emif1: emif@4c000000 {
16                         compatible = "ti,emif-dra7xx";
17                         reg = <0x4c000000 0x200>;
18                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
19                         status = "disabled";
20                 };
22                 target-module@42c01900 {
23                         compatible = "ti,sysc-dra7-mcan", "ti,sysc";
24                         ranges = <0x0 0x42c00000 0x2000>;
25                         #address-cells = <1>;
26                         #size-cells = <1>;
27                         reg = <0x42c01900 0x4>,
28                               <0x42c01904 0x4>,
29                               <0x42c01908 0x4>;
30                         reg-names = "rev", "sysc", "syss";
31                         ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
32                                          SYSC_DRA7_MCAN_ENAWAKEUP)>;
33                         ti,syss-mask = <1>;
34                         clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>;
35                         clock-names = "fck";
37                         m_can0: mcan@1a00 {
38                                 compatible = "bosch,m_can";
39                                 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
40                                 reg-names = "m_can", "message_ram";
41                                 interrupt-parent = <&gic>;
42                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
43                                              <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
44                                 interrupt-names = "int0", "int1";
45                                 clocks = <&mcan_clk>, <&l3_iclk_div>;
46                                 clock-names = "cclk", "hclk";
47                                 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
48                         };
49                 };
50         };
52 };
54 /* MCAN interrupts are hard-wired to irqs 67, 68 */
55 &crossbar_mpu {
56         ti,irqs-skip = <10 67 68 133 139 140>;
57 };
59 &scm_conf_clocks {
60         dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
61                 #clock-cells = <0>;
62                 compatible = "ti,divider-clock";
63                 clocks = <&dpll_gmac_x2_ck>;
64                 ti,max-div = <63>;
65                 reg = <0x03fc>;
66                 ti,bit-shift=<20>;
67                 ti,latch-bit=<26>;
68                 assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
69                 assigned-clock-rates = <80000000>;
70         };
72         dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
73                 #clock-cells = <0>;
74                 compatible = "ti,mux-clock";
75                 clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
76                 reg = <0x3fc>;
77                 ti,bit-shift = <29>;
78                 ti,latch-bit=<26>;
79                 assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
80                 assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
81         };
83         mcan_clk: mcan_clk@3fc {
84                 #clock-cells = <0>;
85                 compatible = "ti,gate-clock";
86                 clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
87                 ti,bit-shift = <27>;
88                 reg = <0x3fc>;
89         };
90 };