arch/arm/boot/dts/imx1.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
   4
   5 #include "imx1-pinfunc.h"
   6
   7 #include <dt-bindings/clock/imx1-clock.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          * Also for U-Boot there must be a pre-existing /memory node.
  19          */
  20         chosen {};
  21         memory { device_type = "memory"; };
  22
  23         aliases {
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 i2c0 = &i2c;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 spi0 = &cspi1;
  33                 spi1 = &cspi2;
  34         };
  35
  36         aitc: aitc-interrupt-controller@223000 {
  37                 compatible = "fsl,imx1-aitc", "fsl,avic";
  38                 interrupt-controller;
  39                 #interrupt-cells = <1>;
  40                 reg = <0x00223000 0x1000>;
  41         };
  42
  43         cpus {
  44                 #size-cells = <0>;
  45                 #address-cells = <1>;
  46
  47                 cpu@0 {
  48                         device_type = "cpu";
  49                         reg = <0>;
  50                         compatible = "arm,arm920t";
  51                         operating-points = <200000 1900000>;
  52                         clock-latency = <62500>;
  53                         clocks = <&clks IMX1_CLK_MCU>;
  54                         voltage-tolerance = <5>;
  55                 };
  56         };
  57
  58         clocks {
  59                 clk32 {
  60                         compatible = "fsl,imx-clk32", "fixed-clock";
  61                         #clock-cells = <0>;
  62                         clock-frequency = <32000>;
  63                 };
  64         };
  65
  66         soc {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 compatible = "simple-bus";
  70                 interrupt-parent = <&aitc>;
  71                 ranges;
  72
  73                 aipi@200000 {
  74                         compatible = "fsl,aipi-bus", "simple-bus";
  75                         #address-cells = <1>;
  76                         #size-cells = <1>;
  77                         reg = <0x00200000 0x10000>;
  78                         ranges;
  79
  80                         gpt1: timer@202000 {
  81                                 compatible = "fsl,imx1-gpt";
  82                                 reg = <0x00202000 0x1000>;
  83                                 interrupts = <59>;
  84                                 clocks = <&clks IMX1_CLK_HCLK>,
  85                                          <&clks IMX1_CLK_PER1>;
  86                                 clock-names = "ipg", "per";
  87                         };
  88
  89                         gpt2: timer@203000 {
  90                                 compatible = "fsl,imx1-gpt";
  91                                 reg = <0x00203000 0x1000>;
  92                                 interrupts = <58>;
  93                                 clocks = <&clks IMX1_CLK_HCLK>,
  94                                          <&clks IMX1_CLK_PER1>;
  95                                 clock-names = "ipg", "per";
  96                         };
  97
  98                         fb: fb@205000 {
  99                                 compatible = "fsl,imx1-fb";
 100                                 reg = <0x00205000 0x1000>;
 101                                 interrupts = <14>;
 102                                 clocks = <&clks IMX1_CLK_DUMMY>,
 103                                          <&clks IMX1_CLK_DUMMY>,
 104                                          <&clks IMX1_CLK_PER2>;
 105                                 clock-names = "ipg", "ahb", "per";
 106                                 status = "disabled";
 107                         };
 108
 109                         uart1: serial@206000 {
 110                                 compatible = "fsl,imx1-uart";
 111                                 reg = <0x00206000 0x1000>;
 112                                 interrupts = <30 29 26>;
 113                                 clocks = <&clks IMX1_CLK_HCLK>,
 114                                          <&clks IMX1_CLK_PER1>;
 115                                 clock-names = "ipg", "per";
 116                                 status = "disabled";
 117                         };
 118
 119                         uart2: serial@207000 {
 120                                 compatible = "fsl,imx1-uart";
 121                                 reg = <0x00207000 0x1000>;
 122                                 interrupts = <24 23 20>;
 123                                 clocks = <&clks IMX1_CLK_HCLK>,
 124                                          <&clks IMX1_CLK_PER1>;
 125                                 clock-names = "ipg", "per";
 126                                 status = "disabled";
 127                         };
 128
 129                         pwm: pwm@208000 {
 130                                 #pwm-cells = <2>;
 131                                 compatible = "fsl,imx1-pwm";
 132                                 reg = <0x00208000 0x1000>;
 133                                 interrupts = <34>;
 134                                 clocks = <&clks IMX1_CLK_DUMMY>,
 135                                          <&clks IMX1_CLK_PER1>;
 136                                 clock-names = "ipg", "per";
 137                         };
 138
 139                         dma: dma@209000 {
 140                                 compatible = "fsl,imx1-dma";
 141                                 reg = <0x00209000 0x1000>;
 142                                 interrupts = <61 60>;
 143                                 clocks = <&clks IMX1_CLK_HCLK>,
 144                                          <&clks IMX1_CLK_DMA_GATE>;
 145                                 clock-names = "ipg", "ahb";
 146                                 #dma-cells = <1>;
 147                         };
 148
 149                         uart3: serial@20a000 {
 150                                 compatible = "fsl,imx1-uart";
 151                                 reg = <0x0020a000 0x1000>;
 152                                 interrupts = <54 4 1>;
 153                                 clocks = <&clks IMX1_CLK_UART3_GATE>,
 154                                          <&clks IMX1_CLK_PER1>;
 155                                 clock-names = "ipg", "per";
 156                                 status = "disabled";
 157                         };
 158                 };
 159
 160                 aipi@210000 {
 161                         compatible = "fsl,aipi-bus", "simple-bus";
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         reg = <0x00210000 0x10000>;
 165                         ranges;
 166
 167                         cspi1: cspi@213000 {
 168                                 #address-cells = <1>;
 169                                 #size-cells = <0>;
 170                                 compatible = "fsl,imx1-cspi";
 171                                 reg = <0x00213000 0x1000>;
 172                                 interrupts = <41>;
 173                                 clocks = <&clks IMX1_CLK_DUMMY>,
 174                                          <&clks IMX1_CLK_PER1>;
 175                                 clock-names = "ipg", "per";
 176                                 status = "disabled";
 177                         };
 178
 179                         i2c: i2c@217000 {
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182                                 compatible = "fsl,imx1-i2c";
 183                                 reg = <0x00217000 0x1000>;
 184                                 interrupts = <39>;
 185                                 clocks = <&clks IMX1_CLK_HCLK>;
 186                                 status = "disabled";
 187                         };
 188
 189                         cspi2: cspi@219000 {
 190                                 #address-cells = <1>;
 191                                 #size-cells = <0>;
 192                                 compatible = "fsl,imx1-cspi";
 193                                 reg = <0x00219000 0x1000>;
 194                                 interrupts = <40>;
 195                                 clocks = <&clks IMX1_CLK_DUMMY>,
 196                                          <&clks IMX1_CLK_PER1>;
 197                                 clock-names = "ipg", "per";
 198                                 status = "disabled";
 199                         };
 200
 201                         clks: ccm@21b000 {
 202                                 compatible = "fsl,imx1-ccm";
 203                                 reg = <0x0021b000 0x1000>;
 204                                 #clock-cells = <1>;
 205                         };
 206
 207                         iomuxc: iomuxc@21c000 {
 208                                 compatible = "fsl,imx1-iomuxc";
 209                                 reg = <0x0021c000 0x1000>;
 210                                 #address-cells = <1>;
 211                                 #size-cells = <1>;
 212                                 ranges;
 213
 214                                 gpio1: gpio@21c000 {
 215                                         compatible = "fsl,imx1-gpio";
 216                                         reg = <0x0021c000 0x100>;
 217                                         interrupts = <11>;
 218                                         gpio-controller;
 219                                         #gpio-cells = <2>;
 220                                         interrupt-controller;
 221                                         #interrupt-cells = <2>;
 222                                 };
 223
 224                                 gpio2: gpio@21c100 {
 225                                         compatible = "fsl,imx1-gpio";
 226                                         reg = <0x0021c100 0x100>;
 227                                         interrupts = <12>;
 228                                         gpio-controller;
 229                                         #gpio-cells = <2>;
 230                                         interrupt-controller;
 231                                         #interrupt-cells = <2>;
 232                                 };
 233
 234                                 gpio3: gpio@21c200 {
 235                                         compatible = "fsl,imx1-gpio";
 236                                         reg = <0x0021c200 0x100>;
 237                                         interrupts = <13>;
 238                                         gpio-controller;
 239                                         #gpio-cells = <2>;
 240                                         interrupt-controller;
 241                                         #interrupt-cells = <2>;
 242                                 };
 243
 244                                 gpio4: gpio@21c300 {
 245                                         compatible = "fsl,imx1-gpio";
 246                                         reg = <0x0021c300 0x100>;
 247                                         interrupts = <62>;
 248                                         gpio-controller;
 249                                         #gpio-cells = <2>;
 250                                         interrupt-controller;
 251                                         #interrupt-cells = <2>;
 252                                 };
 253                         };
 254                 };
 255
 256                 weim: weim@220000 {
 257                         #address-cells = <2>;
 258                         #size-cells = <1>;
 259                         compatible = "fsl,imx1-weim";
 260                         reg = <0x00220000 0x1000>;
 261                         clocks = <&clks IMX1_CLK_DUMMY>;
 262                         ranges = <
 263                                 0 0 0x10000000 0x02000000
 264                                 1 0 0x12000000 0x01000000
 265                                 2 0 0x13000000 0x01000000
 266                                 3 0 0x14000000 0x01000000
 267                                 4 0 0x15000000 0x01000000
 268                                 5 0 0x16000000 0x01000000
 269                         >;
 270                         status = "disabled";
 271                 };
 272
 273                 esram: esram@300000 {
 274                         compatible = "mmio-sram";
 275                         reg = <0x00300000 0x20000>;
 276                 };
 277         };
 278 };