1 /*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
14 #include "imx50-pinfunc.h"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/imx5-clock.h>
18 / {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 /*
22 * The decompressor and also some bootloaders rely on a
23 * pre-existing /chosen node to be available to insert the
24 * command line and merge other ATAGS info.
25 * Also for U-Boot there must be a pre-existing /memory node.
26 */
27 chosen {};
28 memory { device_type = "memory"; };
30 aliases {
31 ethernet0 = &fec;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 };
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a8";
51 reg = <0x0>;
52 };
53 };
55 tzic: tz-interrupt-controller@fffc000 {
56 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x0fffc000 0x4000>;
60 };
62 clocks {
63 ckil {
64 compatible = "fsl,imx-ckil", "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <32768>;
67 };
69 ckih1 {
70 compatible = "fsl,imx-ckih1", "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <22579200>;
73 };
75 ckih2 {
76 compatible = "fsl,imx-ckih2", "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <0>;
79 };
81 osc {
82 compatible = "fsl,imx-osc", "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <24000000>;
85 };
86 };
88 soc {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "simple-bus";
92 interrupt-parent = <&tzic>;
93 ranges;
95 aips@50000000 { /* AIPS1 */
96 compatible = "fsl,aips-bus", "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 reg = <0x50000000 0x10000000>;
100 ranges;
102 spba@50000000 {
103 compatible = "fsl,spba-bus", "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 reg = <0x50000000 0x40000>;
107 ranges;
109 esdhc1: esdhc@50004000 {
110 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
111 reg = <0x50004000 0x4000>;
112 interrupts = <1>;
113 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
114 <&clks IMX5_CLK_DUMMY>,
115 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
116 clock-names = "ipg", "ahb", "per";
117 bus-width = <4>;
118 status = "disabled";
119 };
121 esdhc2: esdhc@50008000 {
122 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
123 reg = <0x50008000 0x4000>;
124 interrupts = <2>;
125 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
126 <&clks IMX5_CLK_DUMMY>,
127 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
128 clock-names = "ipg", "ahb", "per";
129 bus-width = <4>;
130 status = "disabled";
131 };
133 uart3: serial@5000c000 {
134 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
135 reg = <0x5000c000 0x4000>;
136 interrupts = <33>;
137 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
138 <&clks IMX5_CLK_UART3_PER_GATE>;
139 clock-names = "ipg", "per";
140 status = "disabled";
141 };
143 ecspi1: ecspi@50010000 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
147 reg = <0x50010000 0x4000>;
148 interrupts = <36>;
149 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
150 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
151 clock-names = "ipg", "per";
152 status = "disabled";
153 };
155 ssi2: ssi@50014000 {
156 #sound-dai-cells = <0>;
157 compatible = "fsl,imx50-ssi",
158 "fsl,imx51-ssi",
159 "fsl,imx21-ssi";
160 reg = <0x50014000 0x4000>;
161 interrupts = <30>;
162 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
163 dmas = <&sdma 24 1 0>,
164 <&sdma 25 1 0>;
165 dma-names = "rx", "tx";
166 fsl,fifo-depth = <15>;
167 status = "disabled";
168 };
170 esdhc3: esdhc@50020000 {
171 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
172 reg = <0x50020000 0x4000>;
173 interrupts = <3>;
174 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
175 <&clks IMX5_CLK_DUMMY>,
176 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
177 clock-names = "ipg", "ahb", "per";
178 bus-width = <4>;
179 status = "disabled";
180 };
182 esdhc4: esdhc@50024000 {
183 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
184 reg = <0x50024000 0x4000>;
185 interrupts = <4>;
186 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
187 <&clks IMX5_CLK_DUMMY>,
188 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
189 clock-names = "ipg", "ahb", "per";
190 bus-width = <4>;
191 status = "disabled";
192 };
193 };
195 usbotg: usb@53f80000 {
196 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
197 reg = <0x53f80000 0x0200>;
198 interrupts = <18>;
199 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
200 status = "disabled";
201 };
203 usbh1: usb@53f80200 {
204 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
205 reg = <0x53f80200 0x0200>;
206 interrupts = <14>;
207 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
208 dr_mode = "host";
209 status = "disabled";
210 };
212 gpio1: gpio@53f84000 {
213 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
214 reg = <0x53f84000 0x4000>;
215 interrupts = <50 51>;
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 gpio-ranges = <&iomuxc 0 151 28>;
221 };
223 gpio2: gpio@53f88000 {
224 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
225 reg = <0x53f88000 0x4000>;
226 interrupts = <52 53>;
227 gpio-controller;
228 #gpio-cells = <2>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
232 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
233 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
234 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
235 };
237 gpio3: gpio@53f8c000 {
238 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
239 reg = <0x53f8c000 0x4000>;
240 interrupts = <54 55>;
241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
245 gpio-ranges = <&iomuxc 0 108 32>;
246 };
248 gpio4: gpio@53f90000 {
249 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
250 reg = <0x53f90000 0x4000>;
251 interrupts = <56 57>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
257 <&iomuxc 20 140 11>;
258 };
260 wdog1: wdog@53f98000 {
261 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
262 reg = <0x53f98000 0x4000>;
263 interrupts = <58>;
264 clocks = <&clks IMX5_CLK_DUMMY>;
265 };
267 gpt: timer@53fa0000 {
268 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
269 reg = <0x53fa0000 0x4000>;
270 interrupts = <39>;
271 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
272 <&clks IMX5_CLK_GPT_HF_GATE>;
273 clock-names = "ipg", "per";
274 };
276 iomuxc: iomuxc@53fa8000 {
277 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
278 reg = <0x53fa8000 0x4000>;
279 };
281 gpr: iomuxc-gpr@53fa8000 {
282 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
283 reg = <0x53fa8000 0xc>;
284 };
286 pwm1: pwm@53fb4000 {
287 #pwm-cells = <2>;
288 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
289 reg = <0x53fb4000 0x4000>;
290 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
291 <&clks IMX5_CLK_PWM1_HF_GATE>;
292 clock-names = "ipg", "per";
293 interrupts = <61>;
294 };
296 pwm2: pwm@53fb8000 {
297 #pwm-cells = <2>;
298 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
299 reg = <0x53fb8000 0x4000>;
300 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
301 <&clks IMX5_CLK_PWM2_HF_GATE>;
302 clock-names = "ipg", "per";
303 interrupts = <94>;
304 };
306 uart1: serial@53fbc000 {
307 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
308 reg = <0x53fbc000 0x4000>;
309 interrupts = <31>;
310 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
311 <&clks IMX5_CLK_UART1_PER_GATE>;
312 clock-names = "ipg", "per";
313 status = "disabled";
314 };
316 uart2: serial@53fc0000 {
317 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
318 reg = <0x53fc0000 0x4000>;
319 interrupts = <32>;
320 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
321 <&clks IMX5_CLK_UART2_PER_GATE>;
322 clock-names = "ipg", "per";
323 status = "disabled";
324 };
326 src: src@53fd0000 {
327 compatible = "fsl,imx50-src", "fsl,imx51-src";
328 reg = <0x53fd0000 0x4000>;
329 #reset-cells = <1>;
330 };
332 clks: ccm@53fd4000{
333 compatible = "fsl,imx50-ccm";
334 reg = <0x53fd4000 0x4000>;
335 interrupts = <0 71 0x04 0 72 0x04>;
336 #clock-cells = <1>;
337 };
339 gpio5: gpio@53fdc000 {
340 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
341 reg = <0x53fdc000 0x4000>;
342 interrupts = <103 104>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
348 };
350 gpio6: gpio@53fe0000 {
351 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
352 reg = <0x53fe0000 0x4000>;
353 interrupts = <105 106>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
359 };
361 i2c3: i2c@53fec000 {
362 #address-cells = <1>;
363 #size-cells = <0>;
364 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
365 reg = <0x53fec000 0x4000>;
366 interrupts = <64>;
367 clocks = <&clks IMX5_CLK_I2C3_GATE>;
368 status = "disabled";
369 };
371 uart4: serial@53ff0000 {
372 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
373 reg = <0x53ff0000 0x4000>;
374 interrupts = <13>;
375 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
376 <&clks IMX5_CLK_UART4_PER_GATE>;
377 clock-names = "ipg", "per";
378 status = "disabled";
379 };
380 };
382 aips@60000000 { /* AIPS2 */
383 compatible = "fsl,aips-bus", "simple-bus";
384 #address-cells = <1>;
385 #size-cells = <1>;
386 reg = <0x60000000 0x10000000>;
387 ranges;
389 uart5: serial@63f90000 {
390 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
391 reg = <0x63f90000 0x4000>;
392 interrupts = <86>;
393 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
394 <&clks IMX5_CLK_UART5_PER_GATE>;
395 clock-names = "ipg", "per";
396 status = "disabled";
397 };
399 owire: owire@63fa4000 {
400 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
401 reg = <0x63fa4000 0x4000>;
402 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
403 status = "disabled";
404 };
406 ecspi2: ecspi@63fac000 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
410 reg = <0x63fac000 0x4000>;
411 interrupts = <37>;
412 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
413 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
414 clock-names = "ipg", "per";
415 status = "disabled";
416 };
418 sdma: sdma@63fb0000 {
419 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
420 reg = <0x63fb0000 0x4000>;
421 interrupts = <6>;
422 clocks = <&clks IMX5_CLK_SDMA_GATE>,
423 <&clks IMX5_CLK_SDMA_GATE>;
424 clock-names = "ipg", "ahb";
425 #dma-cells = <3>;
426 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
427 };
429 cspi: cspi@63fc0000 {
430 #address-cells = <1>;
431 #size-cells = <0>;
432 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
433 reg = <0x63fc0000 0x4000>;
434 interrupts = <38>;
435 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
436 <&clks IMX5_CLK_CSPI_IPG_GATE>;
437 clock-names = "ipg", "per";
438 status = "disabled";
439 };
441 i2c2: i2c@63fc4000 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
445 reg = <0x63fc4000 0x4000>;
446 interrupts = <63>;
447 clocks = <&clks IMX5_CLK_I2C2_GATE>;
448 status = "disabled";
449 };
451 i2c1: i2c@63fc8000 {
452 #address-cells = <1>;
453 #size-cells = <0>;
454 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
455 reg = <0x63fc8000 0x4000>;
456 interrupts = <62>;
457 clocks = <&clks IMX5_CLK_I2C1_GATE>;
458 status = "disabled";
459 };
461 ssi1: ssi@63fcc000 {
462 #sound-dai-cells = <0>;
463 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
464 "fsl,imx21-ssi";
465 reg = <0x63fcc000 0x4000>;
466 interrupts = <29>;
467 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
468 dmas = <&sdma 28 0 0>,
469 <&sdma 29 0 0>;
470 dma-names = "rx", "tx";
471 fsl,fifo-depth = <15>;
472 status = "disabled";
473 };
475 audmux: audmux@63fd0000 {
476 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
477 reg = <0x63fd0000 0x4000>;
478 status = "disabled";
479 };
481 fec: ethernet@63fec000 {
482 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
483 reg = <0x63fec000 0x4000>;
484 interrupts = <87>;
485 clocks = <&clks IMX5_CLK_FEC_GATE>,
486 <&clks IMX5_CLK_FEC_GATE>,
487 <&clks IMX5_CLK_FEC_GATE>;
488 clock-names = "ipg", "ahb", "ptp";
489 status = "disabled";
490 };
491 };
492 };
493 };