arch/arm/boot/dts/imx51-babbage.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2011 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 /dts-v1/;
   7 #include "imx51.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX51 Babbage Board";
  11         compatible = "fsl,imx51-babbage", "fsl,imx51";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         memory@90000000 {
  18                 reg = <0x90000000 0x20000000>;
  19         };
  20
  21         ckih1 {
  22                 clock-frequency = <22579200>;
  23         };
  24
  25         clk_osc: clk-osc {
  26                 compatible = "fixed-clock";
  27                 #clock-cells = <0>;
  28                 clock-frequency = <26000000>;
  29         };
  30
  31         clk_osc_gate: clk-osc-gate {
  32                 compatible = "gpio-gate-clock";
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&pinctrl_clk26mhz_osc>;
  35                 clocks = <&clk_osc>;
  36                 #clock-cells = <0>;
  37                 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
  38         };
  39
  40         clk_audio: clk-audio {
  41                 compatible = "gpio-gate-clock";
  42                 pinctrl-names = "default";
  43                 pinctrl-0 = <&pinctrl_clk26mhz_audio>;
  44                 clocks = <&clk_osc_gate>;
  45                 #clock-cells = <0>;
  46                 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  47         };
  48
  49         clk_usb: clk-usb {
  50                 compatible = "gpio-gate-clock";
  51                 pinctrl-names = "default";
  52                 pinctrl-0 = <&pinctrl_clk26mhz_usb>;
  53                 clocks = <&clk_osc_gate>;
  54                 #clock-cells = <0>;
  55                 enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  56         };
  57
  58         display1: disp1 {
  59                 compatible = "fsl,imx-parallel-display";
  60                 interface-pix-fmt = "rgb24";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_ipu_disp1>;
  63                 display-timings {
  64                         native-mode = <&timing0>;
  65                         timing0: dvi {
  66                                 clock-frequency = <65000000>;
  67                                 hactive = <1024>;
  68                                 vactive = <768>;
  69                                 hback-porch = <220>;
  70                                 hfront-porch = <40>;
  71                                 vback-porch = <21>;
  72                                 vfront-porch = <7>;
  73                                 hsync-len = <60>;
  74                                 vsync-len = <10>;
  75                         };
  76                 };
  77
  78                 port {
  79                         display0_in: endpoint {
  80                                 remote-endpoint = <&ipu_di0_disp1>;
  81                         };
  82                 };
  83         };
  84
  85         display2: disp2 {
  86                 compatible = "fsl,imx-parallel-display";
  87                 interface-pix-fmt = "rgb565";
  88                 pinctrl-names = "default";
  89                 pinctrl-0 = <&pinctrl_ipu_disp2>;
  90                 status = "disabled";
  91                 display-timings {
  92                         native-mode = <&timing1>;
  93                         timing1: claawvga {
  94                                 clock-frequency = <27000000>;
  95                                 hactive = <800>;
  96                                 vactive = <480>;
  97                                 hback-porch = <40>;
  98                                 hfront-porch = <60>;
  99                                 vback-porch = <10>;
 100                                 vfront-porch = <10>;
 101                                 hsync-len = <20>;
 102                                 vsync-len = <10>;
 103                                 hsync-active = <0>;
 104                                 vsync-active = <0>;
 105                                 de-active = <1>;
 106                                 pixelclk-active = <0>;
 107                         };
 108                 };
 109
 110                 port {
 111                         display1_in: endpoint {
 112                                 remote-endpoint = <&ipu_di1_disp2>;
 113                         };
 114                 };
 115         };
 116
 117         gpio-keys {
 118                 compatible = "gpio-keys";
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&pinctrl_gpio_keys>;
 121
 122                 power {
 123                         label = "Power Button";
 124                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 125                         linux,code = <KEY_POWER>;
 126                         wakeup-source;
 127                 };
 128         };
 129
 130         leds {
 131                 compatible = "gpio-leds";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_gpio_leds>;
 134
 135                 led-diagnostic {
 136                         label = "diagnostic";
 137                         gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 138                 };
 139         };
 140
 141         regulators {
 142                 compatible = "simple-bus";
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145
 146                 reg_hub_reset: regulator@0 {
 147                         compatible = "regulator-fixed";
 148                         pinctrl-names = "default";
 149                         pinctrl-0 = <&pinctrl_usbotgreg>;
 150                         reg = <0>;
 151                         regulator-name = "hub_reset";
 152                         regulator-min-microvolt = <5000000>;
 153                         regulator-max-microvolt = <5000000>;
 154                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 155                         enable-active-high;
 156                 };
 157         };
 158
 159         sound {
 160                 compatible = "fsl,imx51-babbage-sgtl5000",
 161                              "fsl,imx-audio-sgtl5000";
 162                 model = "imx51-babbage-sgtl5000";
 163                 ssi-controller = <&ssi2>;
 164                 audio-codec = <&sgtl5000>;
 165                 audio-routing =
 166                         "MIC_IN", "Mic Jack",
 167                         "Mic Jack", "Mic Bias",
 168                         "Headphone Jack", "HP_OUT";
 169                 mux-int-port = <2>;
 170                 mux-ext-port = <3>;
 171         };
 172
 173         usbphy1: usbphy1 {
 174                 compatible = "usb-nop-xceiv";
 175                 pinctrl-names = "default";
 176                 pinctrl-0 = <&pinctrl_usbh1reg>;
 177                 clocks = <&clk_usb>;
 178                 clock-names = "main_clk";
 179                 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
 180                 vcc-supply = <&vusb_reg>;
 181                 #phy-cells = <0>;
 182         };
 183 };
 184
 185 &audmux {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_audmux>;
 188         status = "okay";
 189 };
 190
 191 &ecspi1 {
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_ecspi1>;
 194         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
 195                    <&gpio4 25 GPIO_ACTIVE_LOW>;
 196         status = "okay";
 197
 198         pmic: mc13892@0 {
 199                 compatible = "fsl,mc13892";
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&pinctrl_pmic>;
 202                 spi-max-frequency = <6000000>;
 203                 spi-cs-high;
 204                 reg = <0>;
 205                 interrupt-parent = <&gpio1>;
 206                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 207                 fsl,mc13xxx-uses-rtc;
 208
 209                 regulators {
 210                         sw1_reg: sw1 {
 211                                 regulator-min-microvolt = <600000>;
 212                                 regulator-max-microvolt = <1375000>;
 213                                 regulator-boot-on;
 214                                 regulator-always-on;
 215                         };
 216
 217                         sw2_reg: sw2 {
 218                                 regulator-min-microvolt = <900000>;
 219                                 regulator-max-microvolt = <1850000>;
 220                                 regulator-boot-on;
 221                                 regulator-always-on;
 222                         };
 223
 224                         sw3_reg: sw3 {
 225                                 regulator-min-microvolt = <1100000>;
 226                                 regulator-max-microvolt = <1850000>;
 227                                 regulator-boot-on;
 228                                 regulator-always-on;
 229                         };
 230
 231                         sw4_reg: sw4 {
 232                                 regulator-min-microvolt = <1100000>;
 233                                 regulator-max-microvolt = <1850000>;
 234                                 regulator-boot-on;
 235                                 regulator-always-on;
 236                         };
 237
 238                         vpll_reg: vpll {
 239                                 regulator-min-microvolt = <1050000>;
 240                                 regulator-max-microvolt = <1800000>;
 241                                 regulator-boot-on;
 242                                 regulator-always-on;
 243                         };
 244
 245                         vdig_reg: vdig {
 246                                 regulator-min-microvolt = <1650000>;
 247                                 regulator-max-microvolt = <1650000>;
 248                                 regulator-boot-on;
 249                         };
 250
 251                         vsd_reg: vsd {
 252                                 regulator-min-microvolt = <1800000>;
 253                                 regulator-max-microvolt = <3150000>;
 254                         };
 255
 256                         vusb_reg: vusb {
 257                                 regulator-boot-on;
 258                         };
 259
 260                         vusb2_reg: vusb2 {
 261                                 regulator-min-microvolt = <2400000>;
 262                                 regulator-max-microvolt = <2775000>;
 263                                 regulator-boot-on;
 264                                 regulator-always-on;
 265                         };
 266
 267                         vvideo_reg: vvideo {
 268                                 regulator-min-microvolt = <2775000>;
 269                                 regulator-max-microvolt = <2775000>;
 270                         };
 271
 272                         vaudio_reg: vaudio {
 273                                 regulator-min-microvolt = <2300000>;
 274                                 regulator-max-microvolt = <3000000>;
 275                         };
 276
 277                         vcam_reg: vcam {
 278                                 regulator-min-microvolt = <2500000>;
 279                                 regulator-max-microvolt = <3000000>;
 280                         };
 281
 282                         vgen1_reg: vgen1 {
 283                                 regulator-min-microvolt = <1200000>;
 284                                 regulator-max-microvolt = <1200000>;
 285                         };
 286
 287                         vgen2_reg: vgen2 {
 288                                 regulator-min-microvolt = <1200000>;
 289                                 regulator-max-microvolt = <3150000>;
 290                                 regulator-always-on;
 291                         };
 292
 293                         vgen3_reg: vgen3 {
 294                                 regulator-min-microvolt = <1800000>;
 295                                 regulator-max-microvolt = <2900000>;
 296                                 regulator-always-on;
 297                         };
 298                 };
 299         };
 300
 301         flash: at45db321d@1 {
 302                 #address-cells = <1>;
 303                 #size-cells = <1>;
 304                 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
 305                 spi-max-frequency = <25000000>;
 306                 reg = <1>;
 307
 308                 partition@0 {
 309                         label = "U-Boot";
 310                         reg = <0x0 0x40000>;
 311                         read-only;
 312                 };
 313
 314                 partition@40000 {
 315                         label = "Kernel";
 316                         reg = <0x40000 0x3c0000>;
 317                 };
 318         };
 319 };
 320
 321 &esdhc1 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_esdhc1>;
 324         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 325         wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 326         status = "okay";
 327 };
 328
 329 &esdhc2 {
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&pinctrl_esdhc2>;
 332         cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
 333         wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 334         status = "okay";
 335 };
 336
 337 &fec {
 338         pinctrl-names = "default";
 339         pinctrl-0 = <&pinctrl_fec>;
 340         phy-mode = "mii";
 341         phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
 342         phy-reset-duration = <1>;
 343         status = "okay";
 344 };
 345
 346 &i2c1 {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&pinctrl_i2c1>;
 349         status = "okay";
 350 };
 351
 352 &i2c2 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_i2c2>;
 355         status = "okay";
 356
 357         sgtl5000: codec@a {
 358                 compatible = "fsl,sgtl5000";
 359                 reg = <0x0a>;
 360                 #sound-dai-cells = <0>;
 361                 clocks = <&clk_audio>;
 362                 VDDA-supply = <&vdig_reg>;
 363                 VDDIO-supply = <&vvideo_reg>;
 364         };
 365 };
 366
 367 &ipu_di0_disp1 {
 368         remote-endpoint = <&display0_in>;
 369 };
 370
 371 &ipu_di1_disp2 {
 372         remote-endpoint = <&display1_in>;
 373 };
 374
 375 &kpp {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_kpp>;
 378         linux,keymap = <
 379                 MATRIX_KEY(0, 0, KEY_UP)
 380                 MATRIX_KEY(0, 1, KEY_DOWN)
 381                 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
 382                 MATRIX_KEY(0, 3, KEY_HOME)
 383                 MATRIX_KEY(1, 0, KEY_RIGHT)
 384                 MATRIX_KEY(1, 1, KEY_LEFT)
 385                 MATRIX_KEY(1, 2, KEY_ENTER)
 386                 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
 387                 MATRIX_KEY(2, 0, KEY_F6)
 388                 MATRIX_KEY(2, 1, KEY_F8)
 389                 MATRIX_KEY(2, 2, KEY_F9)
 390                 MATRIX_KEY(2, 3, KEY_F10)
 391                 MATRIX_KEY(3, 0, KEY_F1)
 392                 MATRIX_KEY(3, 1, KEY_F2)
 393                 MATRIX_KEY(3, 2, KEY_F3)
 394                 MATRIX_KEY(3, 3, KEY_POWER)
 395         >;
 396         status = "okay";
 397 };
 398
 399 &pmu {
 400         secure-reg-access;
 401 };
 402
 403 &ssi2 {
 404         status = "okay";
 405 };
 406
 407 &uart1 {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_uart1>;
 410         uart-has-rtscts;
 411         status = "okay";
 412 };
 413
 414 &uart2 {
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&pinctrl_uart2>;
 417         status = "okay";
 418 };
 419
 420 &uart3 {
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&pinctrl_uart3>;
 423         uart-has-rtscts;
 424         status = "okay";
 425 };
 426
 427 &usbh1 {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_usbh1>;
 430         vbus-supply = <&reg_hub_reset>;
 431         fsl,usbphy = <&usbphy1>;
 432         phy_type = "ulpi";
 433         status = "okay";
 434 };
 435
 436 &usbphy0 {
 437         vcc-supply = <&vusb_reg>;
 438 };
 439
 440 &usbotg {
 441         dr_mode = "otg";
 442         disable-over-current;
 443         phy_type = "utmi_wide";
 444         status = "okay";
 445 };
 446
 447 &iomuxc {
 448         imx51-babbage {
 449                 pinctrl_audmux: audmuxgrp {
 450                         fsl,pins = <
 451                                 MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
 452                                 MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
 453                                 MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
 454                                 MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
 455                         >;
 456                 };
 457
 458                 pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
 459                         fsl,pins = <
 460                                 MX51_PAD_CSPI1_RDY__GPIO4_26            0x85
 461                         >;
 462                 };
 463
 464                 pinctrl_clk26mhz_osc: clk26mhzoscgrp {
 465                         fsl,pins = <
 466                                 MX51_PAD_DI1_PIN12__GPIO3_1             0x85
 467                         >;
 468                 };
 469
 470                 pinctrl_clk26mhz_usb: clk26mhzusbgrp {
 471                         fsl,pins = <
 472                                 MX51_PAD_EIM_D17__GPIO2_1               0x85
 473                         >;
 474                 };
 475
 476                 pinctrl_ecspi1: ecspi1grp {
 477                         fsl,pins = <
 478                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
 479                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
 480                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
 481                                 MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
 482                                 MX51_PAD_CSPI1_SS1__GPIO4_25            0x85 /* CS1 */
 483                         >;
 484                 };
 485
 486                 pinctrl_esdhc1: esdhc1grp {
 487                         fsl,pins = <
 488                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
 489                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
 490                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
 491                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
 492                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
 493                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
 494                                 MX51_PAD_GPIO1_0__GPIO1_0               0x100
 495                                 MX51_PAD_GPIO1_1__GPIO1_1               0x100
 496                         >;
 497                 };
 498
 499                 pinctrl_esdhc2: esdhc2grp {
 500                         fsl,pins = <
 501                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
 502                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
 503                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
 504                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
 505                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
 506                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
 507                                 MX51_PAD_GPIO1_5__GPIO1_5               0x100 /* WP */
 508                                 MX51_PAD_GPIO1_6__GPIO1_6               0x100 /* CD */
 509                         >;
 510                 };
 511
 512                 pinctrl_fec: fecgrp {
 513                         fsl,pins = <
 514                                 MX51_PAD_EIM_EB2__FEC_MDIO              0x000001f5
 515                                 MX51_PAD_EIM_EB3__FEC_RDATA1            0x00000085
 516                                 MX51_PAD_EIM_CS2__FEC_RDATA2            0x00000085
 517                                 MX51_PAD_EIM_CS3__FEC_RDATA3            0x00000085
 518                                 MX51_PAD_EIM_CS4__FEC_RX_ER             0x00000180
 519                                 MX51_PAD_EIM_CS5__FEC_CRS               0x00000180
 520                                 MX51_PAD_NANDF_RB2__FEC_COL             0x00000180
 521                                 MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x00000180
 522                                 MX51_PAD_NANDF_D9__FEC_RDATA0           0x00002180
 523                                 MX51_PAD_NANDF_D8__FEC_TDATA0           0x00002004
 524                                 MX51_PAD_NANDF_CS2__FEC_TX_ER           0x00002004
 525                                 MX51_PAD_NANDF_CS3__FEC_MDC             0x00002004
 526                                 MX51_PAD_NANDF_CS4__FEC_TDATA1          0x00002004
 527                                 MX51_PAD_NANDF_CS5__FEC_TDATA2          0x00002004
 528                                 MX51_PAD_NANDF_CS6__FEC_TDATA3          0x00002004
 529                                 MX51_PAD_NANDF_CS7__FEC_TX_EN           0x00002004
 530                                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x00002180
 531                                 MX51_PAD_NANDF_D11__FEC_RX_DV           0x000020a4
 532                                 MX51_PAD_EIM_A20__GPIO2_14              0x00000085 /* Phy Reset */
 533                         >;
 534                 };
 535
 536                 pinctrl_gpio_keys: gpiokeysgrp {
 537                         fsl,pins = <
 538                                 MX51_PAD_EIM_A27__GPIO2_21              0x5
 539                         >;
 540                 };
 541
 542                 pinctrl_gpio_leds: gpioledsgrp {
 543                         fsl,pins = <
 544                                 MX51_PAD_EIM_D22__GPIO2_6               0x80000000
 545                         >;
 546                 };
 547
 548                 pinctrl_i2c1: i2c1grp {
 549                         fsl,pins = <
 550                                 MX51_PAD_EIM_D19__I2C1_SCL              0x400001ed
 551                                 MX51_PAD_EIM_D16__I2C1_SDA              0x400001ed
 552                         >;
 553                 };
 554
 555                 pinctrl_i2c2: i2c2grp {
 556                         fsl,pins = <
 557                                 MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
 558                                 MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
 559                         >;
 560                 };
 561
 562                 pinctrl_ipu_disp1: ipudisp1grp {
 563                         fsl,pins = <
 564                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
 565                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
 566                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
 567                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
 568                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
 569                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
 570                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
 571                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
 572                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
 573                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
 574                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
 575                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
 576                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
 577                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
 578                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
 579                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
 580                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
 581                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
 582                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
 583                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
 584                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
 585                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
 586                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
 587                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
 588                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
 589                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
 590                         >;
 591                 };
 592
 593                 pinctrl_ipu_disp2: ipudisp2grp {
 594                         fsl,pins = <
 595                                 MX51_PAD_DISP2_DAT0__DISP2_DAT0         0x5
 596                                 MX51_PAD_DISP2_DAT1__DISP2_DAT1         0x5
 597                                 MX51_PAD_DISP2_DAT2__DISP2_DAT2         0x5
 598                                 MX51_PAD_DISP2_DAT3__DISP2_DAT3         0x5
 599                                 MX51_PAD_DISP2_DAT4__DISP2_DAT4         0x5
 600                                 MX51_PAD_DISP2_DAT5__DISP2_DAT5         0x5
 601                                 MX51_PAD_DISP2_DAT6__DISP2_DAT6         0x5
 602                                 MX51_PAD_DISP2_DAT7__DISP2_DAT7         0x5
 603                                 MX51_PAD_DISP2_DAT8__DISP2_DAT8         0x5
 604                                 MX51_PAD_DISP2_DAT9__DISP2_DAT9         0x5
 605                                 MX51_PAD_DISP2_DAT10__DISP2_DAT10       0x5
 606                                 MX51_PAD_DISP2_DAT11__DISP2_DAT11       0x5
 607                                 MX51_PAD_DISP2_DAT12__DISP2_DAT12       0x5
 608                                 MX51_PAD_DISP2_DAT13__DISP2_DAT13       0x5
 609                                 MX51_PAD_DISP2_DAT14__DISP2_DAT14       0x5
 610                                 MX51_PAD_DISP2_DAT15__DISP2_DAT15       0x5
 611                                 MX51_PAD_DI2_PIN2__DI2_PIN2             0x5
 612                                 MX51_PAD_DI2_PIN3__DI2_PIN3             0x5
 613                                 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
 614                                 MX51_PAD_DI_GP4__DI2_PIN15              0x5
 615                         >;
 616                 };
 617
 618                 pinctrl_kpp: kppgrp {
 619                         fsl,pins = <
 620                                 MX51_PAD_KEY_ROW0__KEY_ROW0             0xe0
 621                                 MX51_PAD_KEY_ROW1__KEY_ROW1             0xe0
 622                                 MX51_PAD_KEY_ROW2__KEY_ROW2             0xe0
 623                                 MX51_PAD_KEY_ROW3__KEY_ROW3             0xe0
 624                                 MX51_PAD_KEY_COL0__KEY_COL0             0xe8
 625                                 MX51_PAD_KEY_COL1__KEY_COL1             0xe8
 626                                 MX51_PAD_KEY_COL2__KEY_COL2             0xe8
 627                                 MX51_PAD_KEY_COL3__KEY_COL3             0xe8
 628                         >;
 629                 };
 630
 631                 pinctrl_pmic: pmicgrp {
 632                         fsl,pins = <
 633                                 MX51_PAD_GPIO1_8__GPIO1_8               0xe5 /* IRQ */
 634                         >;
 635                 };
 636
 637                 pinctrl_uart1: uart1grp {
 638                         fsl,pins = <
 639                                 MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
 640                                 MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
 641                                 MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
 642                                 MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
 643                         >;
 644                 };
 645
 646                 pinctrl_uart2: uart2grp {
 647                         fsl,pins = <
 648                                 MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
 649                                 MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
 650                         >;
 651                 };
 652
 653                 pinctrl_uart3: uart3grp {
 654                         fsl,pins = <
 655                                 MX51_PAD_EIM_D25__UART3_RXD             0x1c5
 656                                 MX51_PAD_EIM_D26__UART3_TXD             0x1c5
 657                                 MX51_PAD_EIM_D27__UART3_RTS             0x1c5
 658                                 MX51_PAD_EIM_D24__UART3_CTS             0x1c5
 659                         >;
 660                 };
 661
 662                 pinctrl_usbh1: usbh1grp {
 663                         fsl,pins = <
 664                                 MX51_PAD_USBH1_CLK__USBH1_CLK           0x80000000
 665                                 MX51_PAD_USBH1_DIR__USBH1_DIR           0x80000000
 666                                 MX51_PAD_USBH1_NXT__USBH1_NXT           0x80000000
 667                                 MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x80000000
 668                                 MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x80000000
 669                                 MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x80000000
 670                                 MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x80000000
 671                                 MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x80000000
 672                                 MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x80000000
 673                                 MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x80000000
 674                                 MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x80000000
 675                         >;
 676                 };
 677
 678                 pinctrl_usbh1reg: usbh1reggrp {
 679                         fsl,pins = <
 680                                 MX51_PAD_EIM_D21__GPIO2_5               0x85
 681                         >;
 682                 };
 683
 684                 pinctrl_usbotgreg: usbotgreggrp {
 685                         fsl,pins = <
 686                                 MX51_PAD_GPIO1_7__GPIO1_7               0x85
 687                         >;
 688                 };
 689         };
 690 };