1 /*
2 * Copyright 2015 Technexion Ltd.
3 *
4 * Author: Wig Cheng <wig.cheng@technexion.com>
5 * Richard Hu <richard.hu@technexion.com>
6 * Tapani Utriainen <tapani@technexion.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * version 2 as published by the Free Software Foundation.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
46 /dts-v1/;
48 #include "imx6ul.dtsi"
50 / {
51 model = "Technexion Pico i.MX6UL Board";
52 compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
54 /* Will be filled by the bootloader */
55 memory@80000000 {
56 reg = <0x80000000 0>;
57 };
59 chosen {
60 stdout-path = &uart6;
61 };
63 backlight {
64 compatible = "pwm-backlight";
65 pwms = <&pwm3 0 5000000>;
66 brightness-levels = <0 4 8 16 32 64 128 255>;
67 default-brightness-level = <6>;
68 status = "okay";
69 };
71 reg_2p5v: regulator-2p5v {
72 compatible = "regulator-fixed";
73 regulator-name = "2P5V";
74 regulator-min-microvolt = <2500000>;
75 regulator-max-microvolt = <2500000>;
76 };
78 reg_3p3v: regulator-3p3v {
79 compatible = "regulator-fixed";
80 regulator-name = "3P3V";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 };
85 reg_sd1_vmmc: regulator-sd1-vmmc {
86 compatible = "regulator-fixed";
87 regulator-name = "VSD_3V3";
88 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>;
90 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
91 enable-active-high;
92 };
94 reg_usb_otg_vbus: regulator-usb-otg-vbus {
95 compatible = "regulator-fixed";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usb_otg1>;
98 regulator-name = "usb_otg_vbus";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
101 gpio = <&gpio1 6 0>;
102 };
104 reg_brcm: regulator-brcm {
105 compatible = "regulator-fixed";
106 enable-active-high;
107 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_brcm_reg>;
110 regulator-name = "brcm_reg";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 startup-delay-us = <200000>;
114 };
116 sound {
117 compatible = "fsl,imx-audio-sgtl5000";
118 model = "imx6ul-sgtl5000";
119 audio-cpu = <&sai1>;
120 audio-codec = <&codec>;
121 audio-routing =
122 "LINE_IN", "Line In Jack",
123 "MIC_IN", "Mic Jack",
124 "Mic Jack", "Mic Bias",
125 "Headphone Jack", "HP_OUT";
126 };
128 sys_mclk: clock-sys-mclk {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <24576000>;
132 };
134 leds {
135 compatible = "gpio-leds";
137 hobbitled {
138 label = "hobbitled";
139 gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
140 };
141 };
142 };
144 &can1 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_flexcan1>;
147 status = "okay";
148 };
150 &can2 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_flexcan2>;
153 status = "okay";
154 };
156 &clks {
157 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
158 assigned-clock-rates = <786432000>;
159 };
161 &fec2 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_enet2>;
164 phy-mode = "rmii";
165 phy-handle = <ðphy1>;
166 status = "okay";
167 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
168 phy-reset-duration = <1>;
170 mdio {
171 #address-cells = <1>;
172 #size-cells = <0>;
174 ethphy1: ethernet-phy@1 {
175 compatible = "ethernet-phy-ieee802.3-c22";
176 reg = <1>;
177 max-speed = <100>;
178 interrupt-parent = <&gpio5>;
179 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
180 };
181 };
182 };
184 &i2c1 {
185 clock-frequency = <100000>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_i2c1>;
188 status = "okay";
190 pmic: pfuze3000@8 {
191 compatible = "fsl,pfuze3000";
192 reg = <0x08>;
194 regulators {
195 /* VDD_ARM_SOC_IN*/
196 sw1b_reg: sw1b {
197 regulator-min-microvolt = <700000>;
198 regulator-max-microvolt = <1475000>;
199 regulator-boot-on;
200 regulator-always-on;
201 regulator-ramp-delay = <6250>;
202 };
204 /* DRAM */
205 sw3a_reg: sw3 {
206 regulator-min-microvolt = <900000>;
207 regulator-max-microvolt = <1650000>;
208 regulator-boot-on;
209 regulator-always-on;
210 };
212 /* DRAM */
213 vref_reg: vrefddr {
214 regulator-boot-on;
215 regulator-always-on;
216 };
217 };
218 };
219 };
221 &i2c2 {
222 clock_frequency = <100000>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_i2c2>;
225 status = "okay";
227 codec: sgtl5000@a {
228 reg = <0x0a>;
229 compatible = "fsl,sgtl5000";
230 clocks = <&sys_mclk>;
231 VDDA-supply = <®_2p5v>;
232 VDDIO-supply = <®_3p3v>;
233 };
234 };
236 &i2c3 {
237 clock_frequency = <100000>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c3>;
240 status = "okay";
241 };
243 &lcdif {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
246 display = <&display0>;
247 status = "okay";
249 display0: display0 {
250 bits-per-pixel = <32>;
251 bus-width = <24>;
253 display-timings {
254 native-mode = <&timing0>;
256 timing0: timing0 {
257 clock-frequency = <33200000>;
258 hactive = <800>;
259 vactive = <480>;
260 hfront-porch = <210>;
261 hback-porch = <46>;
262 hsync-len = <1>;
263 vback-porch = <22>;
264 vfront-porch = <23>;
265 vsync-len = <1>;
266 hsync-active = <0>;
267 vsync-active = <0>;
268 de-active = <1>;
269 pixelclk-active = <0>;
270 };
271 };
272 };
273 };
275 &pwm3 {
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_pwm3>;
278 status = "okay";
279 };
281 &pwm7 {
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_pwm7>;
284 status = "okay";
285 };
287 &pwm8 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_pwm8>;
290 status = "okay";
291 };
293 &sai1 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_sai1>;
296 status = "okay";
297 };
299 &uart3 {
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_uart3>;
302 uart-has-rtscts;
303 status = "okay";
304 };
306 &uart6 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart6>;
309 status = "okay";
310 };
312 &usbotg1 {
313 vbus-supply = <®_usb_otg_vbus>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb_otg1_id>;
316 dr_mode = "otg";
317 disable-over-current;
318 status = "okay";
319 };
321 &usbotg2 {
322 dr_mode = "host";
323 disable-over-current;
324 status = "okay";
325 };
327 &usdhc1 {
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usdhc1>;
330 bus-width = <8>;
331 no-1-8-v;
332 non-removable;
333 keep-power-in-suspend;
334 status = "okay";
335 };
337 &usdhc2 { /* Wifi SDIO */
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_usdhc2>;
340 no-1-8-v;
341 non-removable;
342 keep-power-in-suspend;
343 wakeup-source;
344 vmmc-supply = <®_brcm>;
345 status = "okay";
346 };
348 &wdog1 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_wdog>;
351 fsl,ext-reset-output;
352 };
354 &iomuxc {
355 pinctrl_brcm_reg: brcmreggrp {
356 fsl,pins = <
357 MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
358 MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
359 >;
360 };
362 pinctrl_enet2: enet2grp {
363 fsl,pins = <
364 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
365 MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
366 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
367 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
368 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
369 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
370 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
371 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
372 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
373 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
374 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
375 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
376 >;
377 };
379 pinctrl_flexcan1: flexcan1grp {
380 fsl,pins = <
381 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
382 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
383 >;
384 };
386 pinctrl_flexcan2: flexcan2grp {
387 fsl,pins = <
388 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
389 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
390 >;
391 };
393 pinctrl_i2c1: i2c1grp {
394 fsl,pins = <
395 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
396 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
397 >;
398 };
400 pinctrl_i2c2: i2c2grp {
401 fsl,pins = <
402 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
403 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
404 >;
405 };
407 pinctrl_i2c3: i2c3grp {
408 fsl,pins = <
409 MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
410 MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
411 >;
412 };
414 pinctrl_lcdif_dat: lcdifdatgrp {
415 fsl,pins = <
416 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
417 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
418 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
419 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
420 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
421 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
422 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
423 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
424 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
425 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
426 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
427 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
428 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
429 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
430 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
431 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
432 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
433 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
434 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
435 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
436 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
437 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
438 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
439 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
440 >;
441 };
443 pinctrl_lcdif_ctrl: lcdifctrlgrp {
444 fsl,pins = <
445 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
446 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
447 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
448 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
449 /* LCD reset */
450 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
451 >;
452 };
454 pinctrl_pwm3: pwm3grp {
455 fsl,pins = <
456 MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
457 >;
458 };
460 pinctrl_pwm7: pwm7grp {
461 fsl,pins = <
462 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
463 >;
464 };
466 pinctrl_pwm8: pwm8grp {
467 fsl,pins = <
468 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
469 >;
470 };
472 pinctrl_sai1: sai1grp {
473 fsl,pins = <
474 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
475 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
476 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
477 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
478 >;
479 };
481 pinctrl_uart3: uart3grp {
482 fsl,pins = <
483 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
484 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
485 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
486 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
487 >;
488 };
490 pinctrl_uart5: uart5grp {
491 fsl,pins = <
492 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
493 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
494 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
495 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
496 >;
497 };
499 pinctrl_uart6: uart6grp {
500 fsl,pins = <
501 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
502 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
503 >;
504 };
506 pinctrl_usb_otg1: usbotg1grp {
507 fsl,pins = <
508 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
509 >;
510 };
512 pinctrl_usb_otg1_id: usbotg1idgrp {
513 fsl,pins = <
514 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
515 >;
516 };
518 pinctrl_usdhc1: usdhc1grp {
519 fsl,pins = <
520 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
521 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
522 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
523 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
524 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
525 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
526 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
527 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
528 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
529 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
530 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
531 >;
532 };
534 pinctrl_usdhc2: usdhc2grp {
535 fsl,pins = <
536 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
537 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
538 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
539 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
540 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
541 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
542 >;
543 };
545 pinctrl_wdog: wdoggrp {
546 fsl,pins = <
547 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
548 >;
549 };
550 };