1 /*
2 * omap_hwmod implementation for OMAP2/3/4
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2011-2012 Texas Instruments, Inc.
6 *
7 * Paul Walmsley, BenoƮt Cousson, Kevin Hilman
8 *
9 * Created in collaboration with (alphabetical order): Thara Gopinath,
10 * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
11 * Sawant, Santosh Shilimkar, Richard Woodruff
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Introduction
18 * ------------
19 * One way to view an OMAP SoC is as a collection of largely unrelated
20 * IP blocks connected by interconnects. The IP blocks include
21 * devices such as ARM processors, audio serial interfaces, UARTs,
22 * etc. Some of these devices, like the DSP, are created by TI;
23 * others, like the SGX, largely originate from external vendors. In
24 * TI's documentation, on-chip devices are referred to as "OMAP
25 * modules." Some of these IP blocks are identical across several
26 * OMAP versions. Others are revised frequently.
27 *
28 * These OMAP modules are tied together by various interconnects.
29 * Most of the address and data flow between modules is via OCP-based
30 * interconnects such as the L3 and L4 buses; but there are other
31 * interconnects that distribute the hardware clock tree, handle idle
32 * and reset signaling, supply power, and connect the modules to
33 * various pads or balls on the OMAP package.
34 *
35 * OMAP hwmod provides a consistent way to describe the on-chip
36 * hardware blocks and their integration into the rest of the chip.
37 * This description can be automatically generated from the TI
38 * hardware database. OMAP hwmod provides a standard, consistent API
39 * to reset, enable, idle, and disable these hardware blocks. And
40 * hwmod provides a way for other core code, such as the Linux device
41 * code or the OMAP power management and address space mapping code,
42 * to query the hardware database.
43 *
44 * Using hwmod
45 * -----------
46 * Drivers won't call hwmod functions directly. That is done by the
47 * omap_device code, and in rare occasions, by custom integration code
48 * in arch/arm/ *omap*. The omap_device code includes functions to
49 * build a struct platform_device using omap_hwmod data, and that is
50 * currently how hwmod data is communicated to drivers and to the
51 * Linux driver model. Most drivers will call omap_hwmod functions only
52 * indirectly, via pm_runtime*() functions.
53 *
54 * From a layering perspective, here is where the OMAP hwmod code
55 * fits into the kernel software stack:
56 *
57 * +-------------------------------+
58 * | Device driver code |
59 * | (e.g., drivers/) |
60 * +-------------------------------+
61 * | Linux driver model |
62 * | (platform_device / |
63 * | platform_driver data/code) |
64 * +-------------------------------+
65 * | OMAP core-driver integration |
66 * |(arch/arm/mach-omap2/devices.c)|
67 * +-------------------------------+
68 * | omap_device code |
69 * | (../plat-omap/omap_device.c) |
70 * +-------------------------------+
71 * ----> | omap_hwmod code/data | <-----
72 * | (../mach-omap2/omap_hwmod*) |
73 * +-------------------------------+
74 * | OMAP clock/PRCM/register fns |
75 * | ({read,write}l_relaxed, clk*) |
76 * +-------------------------------+
77 *
78 * Device drivers should not contain any OMAP-specific code or data in
79 * them. They should only contain code to operate the IP block that
80 * the driver is responsible for. This is because these IP blocks can
81 * also appear in other SoCs, either from TI (such as DaVinci) or from
82 * other manufacturers; and drivers should be reusable across other
83 * platforms.
84 *
85 * The OMAP hwmod code also will attempt to reset and idle all on-chip
86 * devices upon boot. The goal here is for the kernel to be
87 * completely self-reliant and independent from bootloaders. This is
88 * to ensure a repeatable configuration, both to ensure consistent
89 * runtime behavior, and to make it easier for others to reproduce
90 * bugs.
91 *
92 * OMAP module activity states
93 * ---------------------------
94 * The hwmod code considers modules to be in one of several activity
95 * states. IP blocks start out in an UNKNOWN state, then once they
96 * are registered via the hwmod code, proceed to the REGISTERED state.
97 * Once their clock names are resolved to clock pointers, the module
98 * enters the CLKS_INITED state; and finally, once the module has been
99 * reset and the integration registers programmed, the INITIALIZED state
100 * is entered. The hwmod code will then place the module into either
101 * the IDLE state to save power, or in the case of a critical system
102 * module, the ENABLED state.
103 *
104 * OMAP core integration code can then call omap_hwmod*() functions
105 * directly to move the module between the IDLE, ENABLED, and DISABLED
106 * states, as needed. This is done during both the PM idle loop, and
107 * in the OMAP core integration code's implementation of the PM runtime
108 * functions.
109 *
110 * References
111 * ----------
112 * This is a partial list.
113 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
114 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
115 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
116 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
117 * - Open Core Protocol Specification 2.2
118 *
119 * To do:
120 * - handle IO mapping
121 * - bus throughput & module latency measurement code
122 *
123 * XXX add tests at the beginning of each function to ensure the hwmod is
124 * in the appropriate state
125 * XXX error return values should be checked to ensure that they are
126 * appropriate
127 */
128 #undef DEBUG
130 #include <linux/kernel.h>
131 #include <linux/errno.h>
132 #include <linux/io.h>
133 #include <linux/clk.h>
134 #include <linux/clk-provider.h>
135 #include <linux/delay.h>
136 #include <linux/err.h>
137 #include <linux/list.h>
138 #include <linux/mutex.h>
139 #include <linux/spinlock.h>
140 #include <linux/slab.h>
141 #include <linux/cpu.h>
142 #include <linux/of.h>
143 #include <linux/of_address.h>
144 #include <linux/bootmem.h>
146 #include <linux/platform_data/ti-sysc.h>
148 #include <dt-bindings/bus/ti-sysc.h>
150 #include <asm/system_misc.h>
152 #include "clock.h"
153 #include "omap_hwmod.h"
155 #include "soc.h"
156 #include "common.h"
157 #include "clockdomain.h"
158 #include "powerdomain.h"
159 #include "cm2xxx.h"
160 #include "cm3xxx.h"
161 #include "cm33xx.h"
162 #include "prm.h"
163 #include "prm3xxx.h"
164 #include "prm44xx.h"
165 #include "prm33xx.h"
166 #include "prminst44xx.h"
167 #include "pm.h"
169 /* Name of the OMAP hwmod for the MPU */
170 #define MPU_INITIATOR_NAME "mpu"
172 /*
173 * Number of struct omap_hwmod_link records per struct
174 * omap_hwmod_ocp_if record (master->slave and slave->master)
175 */
176 #define LINKS_PER_OCP_IF 2
178 /*
179 * Address offset (in bytes) between the reset control and the reset
180 * status registers: 4 bytes on OMAP4
181 */
182 #define OMAP4_RST_CTRL_ST_OFFSET 4
184 /*
185 * Maximum length for module clock handle names
186 */
187 #define MOD_CLK_MAX_NAME_LEN 32
189 /**
190 * struct clkctrl_provider - clkctrl provider mapping data
191 * @addr: base address for the provider
192 * @size: size of the provider address space
193 * @offset: offset of the provider from PRCM instance base
194 * @node: device node associated with the provider
195 * @link: list link
196 */
197 struct clkctrl_provider {
198 u32 addr;
199 u32 size;
200 u16 offset;
201 struct device_node *node;
202 struct list_head link;
203 };
205 static LIST_HEAD(clkctrl_providers);
207 /**
208 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
209 * @enable_module: function to enable a module (via MODULEMODE)
210 * @disable_module: function to disable a module (via MODULEMODE)
211 *
212 * XXX Eventually this functionality will be hidden inside the PRM/CM
213 * device drivers. Until then, this should avoid huge blocks of cpu_is_*()
214 * conditionals in this code.
215 */
216 struct omap_hwmod_soc_ops {
217 void (*enable_module)(struct omap_hwmod *oh);
218 int (*disable_module)(struct omap_hwmod *oh);
219 int (*wait_target_ready)(struct omap_hwmod *oh);
220 int (*assert_hardreset)(struct omap_hwmod *oh,
221 struct omap_hwmod_rst_info *ohri);
222 int (*deassert_hardreset)(struct omap_hwmod *oh,
223 struct omap_hwmod_rst_info *ohri);
224 int (*is_hardreset_asserted)(struct omap_hwmod *oh,
225 struct omap_hwmod_rst_info *ohri);
226 int (*init_clkdm)(struct omap_hwmod *oh);
227 void (*update_context_lost)(struct omap_hwmod *oh);
228 int (*get_context_lost)(struct omap_hwmod *oh);
229 int (*disable_direct_prcm)(struct omap_hwmod *oh);
230 u32 (*xlate_clkctrl)(struct omap_hwmod *oh);
231 };
233 /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
234 static struct omap_hwmod_soc_ops soc_ops;
236 /* omap_hwmod_list contains all registered struct omap_hwmods */
237 static LIST_HEAD(omap_hwmod_list);
239 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
240 static struct omap_hwmod *mpu_oh;
242 /* inited: set to true once the hwmod code is initialized */
243 static bool inited;
245 /* Private functions */
247 /**
248 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
249 * @oh: struct omap_hwmod *
250 *
251 * Load the current value of the hwmod OCP_SYSCONFIG register into the
252 * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no
253 * OCP_SYSCONFIG register or 0 upon success.
254 */
255 static int _update_sysc_cache(struct omap_hwmod *oh)
256 {
257 if (!oh->class->sysc) {
258 WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
259 return -EINVAL;
260 }
262 /* XXX ensure module interface clock is up */
264 oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
266 if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
267 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
269 return 0;
270 }
272 /**
273 * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register
274 * @v: OCP_SYSCONFIG value to write
275 * @oh: struct omap_hwmod *
276 *
277 * Write @v into the module class' OCP_SYSCONFIG register, if it has
278 * one. No return value.
279 */
280 static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
281 {
282 if (!oh->class->sysc) {
283 WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
284 return;
285 }
287 /* XXX ensure module interface clock is up */
289 /* Module might have lost context, always update cache and register */
290 oh->_sysc_cache = v;
292 /*
293 * Some IP blocks (such as RTC) require unlocking of IP before
294 * accessing its registers. If a function pointer is present
295 * to unlock, then call it before accessing sysconfig and
296 * call lock after writing sysconfig.
297 */
298 if (oh->class->unlock)
299 oh->class->unlock(oh);
301 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
303 if (oh->class->lock)
304 oh->class->lock(oh);
305 }
307 /**
308 * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v
309 * @oh: struct omap_hwmod *
310 * @standbymode: MIDLEMODE field bits
311 * @v: pointer to register contents to modify
312 *
313 * Update the master standby mode bits in @v to be @standbymode for
314 * the @oh hwmod. Does not write to the hardware. Returns -EINVAL
315 * upon error or 0 upon success.
316 */
317 static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
318 u32 *v)
319 {
320 u32 mstandby_mask;
321 u8 mstandby_shift;
323 if (!oh->class->sysc ||
324 !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
325 return -EINVAL;
327 if (!oh->class->sysc->sysc_fields) {
328 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
329 return -EINVAL;
330 }
332 mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
333 mstandby_mask = (0x3 << mstandby_shift);
335 *v &= ~mstandby_mask;
336 *v |= __ffs(standbymode) << mstandby_shift;
338 return 0;
339 }
341 /**
342 * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v
343 * @oh: struct omap_hwmod *
344 * @idlemode: SIDLEMODE field bits
345 * @v: pointer to register contents to modify
346 *
347 * Update the slave idle mode bits in @v to be @idlemode for the @oh
348 * hwmod. Does not write to the hardware. Returns -EINVAL upon error
349 * or 0 upon success.
350 */
351 static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
352 {
353 u32 sidle_mask;
354 u8 sidle_shift;
356 if (!oh->class->sysc ||
357 !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
358 return -EINVAL;
360 if (!oh->class->sysc->sysc_fields) {
361 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
362 return -EINVAL;
363 }
365 sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
366 sidle_mask = (0x3 << sidle_shift);
368 *v &= ~sidle_mask;
369 *v |= __ffs(idlemode) << sidle_shift;
371 return 0;
372 }
374 /**
375 * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
376 * @oh: struct omap_hwmod *
377 * @clockact: CLOCKACTIVITY field bits
378 * @v: pointer to register contents to modify
379 *
380 * Update the clockactivity mode bits in @v to be @clockact for the
381 * @oh hwmod. Used for additional powersaving on some modules. Does
382 * not write to the hardware. Returns -EINVAL upon error or 0 upon
383 * success.
384 */
385 static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
386 {
387 u32 clkact_mask;
388 u8 clkact_shift;
390 if (!oh->class->sysc ||
391 !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
392 return -EINVAL;
394 if (!oh->class->sysc->sysc_fields) {
395 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
396 return -EINVAL;
397 }
399 clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
400 clkact_mask = (0x3 << clkact_shift);
402 *v &= ~clkact_mask;
403 *v |= clockact << clkact_shift;
405 return 0;
406 }
408 /**
409 * _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v
410 * @oh: struct omap_hwmod *
411 * @v: pointer to register contents to modify
412 *
413 * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon
414 * error or 0 upon success.
415 */
416 static int _set_softreset(struct omap_hwmod *oh, u32 *v)
417 {
418 u32 softrst_mask;
420 if (!oh->class->sysc ||
421 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
422 return -EINVAL;
424 if (!oh->class->sysc->sysc_fields) {
425 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
426 return -EINVAL;
427 }
429 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
431 *v |= softrst_mask;
433 return 0;
434 }
436 /**
437 * _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v
438 * @oh: struct omap_hwmod *
439 * @v: pointer to register contents to modify
440 *
441 * Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon
442 * error or 0 upon success.
443 */
444 static int _clear_softreset(struct omap_hwmod *oh, u32 *v)
445 {
446 u32 softrst_mask;
448 if (!oh->class->sysc ||
449 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
450 return -EINVAL;
452 if (!oh->class->sysc->sysc_fields) {
453 WARN(1,
454 "omap_hwmod: %s: sysc_fields absent for sysconfig class\n",
455 oh->name);
456 return -EINVAL;
457 }
459 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
461 *v &= ~softrst_mask;
463 return 0;
464 }
466 /**
467 * _wait_softreset_complete - wait for an OCP softreset to complete
468 * @oh: struct omap_hwmod * to wait on
469 *
470 * Wait until the IP block represented by @oh reports that its OCP
471 * softreset is complete. This can be triggered by software (see
472 * _ocp_softreset()) or by hardware upon returning from off-mode (one
473 * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT
474 * microseconds. Returns the number of microseconds waited.
475 */
476 static int _wait_softreset_complete(struct omap_hwmod *oh)
477 {
478 struct omap_hwmod_class_sysconfig *sysc;
479 u32 softrst_mask;
480 int c = 0;
482 sysc = oh->class->sysc;
484 if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS && sysc->syss_offs > 0)
485 omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs)
486 & SYSS_RESETDONE_MASK),
487 MAX_MODULE_SOFTRESET_WAIT, c);
488 else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
489 softrst_mask = (0x1 << sysc->sysc_fields->srst_shift);
490 omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs)
491 & softrst_mask),
492 MAX_MODULE_SOFTRESET_WAIT, c);
493 }
495 return c;
496 }
498 /**
499 * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v
500 * @oh: struct omap_hwmod *
501 *
502 * The DMADISABLE bit is a semi-automatic bit present in sysconfig register
503 * of some modules. When the DMA must perform read/write accesses, the
504 * DMADISABLE bit is cleared by the hardware. But when the DMA must stop
505 * for power management, software must set the DMADISABLE bit back to 1.
506 *
507 * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon
508 * error or 0 upon success.
509 */
510 static int _set_dmadisable(struct omap_hwmod *oh)
511 {
512 u32 v;
513 u32 dmadisable_mask;
515 if (!oh->class->sysc ||
516 !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE))
517 return -EINVAL;
519 if (!oh->class->sysc->sysc_fields) {
520 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
521 return -EINVAL;
522 }
524 /* clocks must be on for this operation */
525 if (oh->_state != _HWMOD_STATE_ENABLED) {
526 pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name);
527 return -EINVAL;
528 }
530 pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name);
532 v = oh->_sysc_cache;
533 dmadisable_mask =
534 (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift);
535 v |= dmadisable_mask;
536 _write_sysconfig(v, oh);
538 return 0;
539 }
541 /**
542 * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
543 * @oh: struct omap_hwmod *
544 * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
545 * @v: pointer to register contents to modify
546 *
547 * Update the module autoidle bit in @v to be @autoidle for the @oh
548 * hwmod. The autoidle bit controls whether the module can gate
549 * internal clocks automatically when it isn't doing anything; the
550 * exact function of this bit varies on a per-module basis. This
551 * function does not write to the hardware. Returns -EINVAL upon
552 * error or 0 upon success.
553 */
554 static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
555 u32 *v)
556 {
557 u32 autoidle_mask;
558 u8 autoidle_shift;
560 if (!oh->class->sysc ||
561 !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
562 return -EINVAL;
564 if (!oh->class->sysc->sysc_fields) {
565 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
566 return -EINVAL;
567 }
569 autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
570 autoidle_mask = (0x1 << autoidle_shift);
572 *v &= ~autoidle_mask;
573 *v |= autoidle << autoidle_shift;
575 return 0;
576 }
578 /**
579 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
580 * @oh: struct omap_hwmod *
581 *
582 * Allow the hardware module @oh to send wakeups. Returns -EINVAL
583 * upon error or 0 upon success.
584 */
585 static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
586 {
587 if (!oh->class->sysc ||
588 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
589 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
590 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
591 return -EINVAL;
593 if (!oh->class->sysc->sysc_fields) {
594 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
595 return -EINVAL;
596 }
598 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
599 *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
601 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
602 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
603 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
604 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
606 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
608 return 0;
609 }
611 /**
612 * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
613 * @oh: struct omap_hwmod *
614 *
615 * Prevent the hardware module @oh to send wakeups. Returns -EINVAL
616 * upon error or 0 upon success.
617 */
618 static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
619 {
620 if (!oh->class->sysc ||
621 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
622 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
623 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
624 return -EINVAL;
626 if (!oh->class->sysc->sysc_fields) {
627 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
628 return -EINVAL;
629 }
631 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
632 *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
634 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
635 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
636 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
637 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v);
639 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
641 return 0;
642 }
644 static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
645 {
646 struct clk_hw_omap *clk;
648 if (oh->clkdm) {
649 return oh->clkdm;
650 } else if (oh->_clk) {
651 if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
652 return NULL;
653 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
654 return clk->clkdm;
655 }
656 return NULL;
657 }
659 /**
660 * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
661 * @oh: struct omap_hwmod *
662 *
663 * Prevent the hardware module @oh from entering idle while the
664 * hardare module initiator @init_oh is active. Useful when a module
665 * will be accessed by a particular initiator (e.g., if a module will
666 * be accessed by the IVA, there should be a sleepdep between the IVA
667 * initiator and the module). Only applies to modules in smart-idle
668 * mode. If the clockdomain is marked as not needing autodeps, return
669 * 0 without doing anything. Otherwise, returns -EINVAL upon error or
670 * passes along clkdm_add_sleepdep() value upon success.
671 */
672 static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
673 {
674 struct clockdomain *clkdm, *init_clkdm;
676 clkdm = _get_clkdm(oh);
677 init_clkdm = _get_clkdm(init_oh);
679 if (!clkdm || !init_clkdm)
680 return -EINVAL;
682 if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
683 return 0;
685 return clkdm_add_sleepdep(clkdm, init_clkdm);
686 }
688 /**
689 * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active
690 * @oh: struct omap_hwmod *
691 *
692 * Allow the hardware module @oh to enter idle while the hardare
693 * module initiator @init_oh is active. Useful when a module will not
694 * be accessed by a particular initiator (e.g., if a module will not
695 * be accessed by the IVA, there should be no sleepdep between the IVA
696 * initiator and the module). Only applies to modules in smart-idle
697 * mode. If the clockdomain is marked as not needing autodeps, return
698 * 0 without doing anything. Returns -EINVAL upon error or passes
699 * along clkdm_del_sleepdep() value upon success.
700 */
701 static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
702 {
703 struct clockdomain *clkdm, *init_clkdm;
705 clkdm = _get_clkdm(oh);
706 init_clkdm = _get_clkdm(init_oh);
708 if (!clkdm || !init_clkdm)
709 return -EINVAL;
711 if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
712 return 0;
714 return clkdm_del_sleepdep(clkdm, init_clkdm);
715 }
717 static const struct of_device_id ti_clkctrl_match_table[] __initconst = {
718 { .compatible = "ti,clkctrl" },
719 { }
720 };
722 static int __init _setup_clkctrl_provider(struct device_node *np)
723 {
724 const __be32 *addrp;
725 struct clkctrl_provider *provider;
726 u64 size;
728 provider = memblock_virt_alloc(sizeof(*provider), 0);
729 if (!provider)
730 return -ENOMEM;
732 addrp = of_get_address(np, 0, &size, NULL);
733 provider->addr = (u32)of_translate_address(np, addrp);
734 addrp = of_get_address(np->parent, 0, NULL, NULL);
735 provider->offset = provider->addr -
736 (u32)of_translate_address(np->parent, addrp);
737 provider->addr &= ~0xff;
738 provider->size = size | 0xff;
739 provider->node = np;
741 pr_debug("%s: %s: %x...%x [+%x]\n", __func__, np->parent->name,
742 provider->addr, provider->addr + provider->size,
743 provider->offset);
745 list_add(&provider->link, &clkctrl_providers);
747 return 0;
748 }
750 static int __init _init_clkctrl_providers(void)
751 {
752 struct device_node *np;
753 int ret = 0;
755 for_each_matching_node(np, ti_clkctrl_match_table) {
756 ret = _setup_clkctrl_provider(np);
757 if (ret)
758 break;
759 }
761 return ret;
762 }
764 static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh)
765 {
766 if (!oh->prcm.omap4.modulemode)
767 return 0;
769 return omap_cm_xlate_clkctrl(oh->clkdm->prcm_partition,
770 oh->clkdm->cm_inst,
771 oh->prcm.omap4.clkctrl_offs);
772 }
774 static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh)
775 {
776 struct clkctrl_provider *provider;
777 struct clk *clk;
778 u32 addr;
780 if (!soc_ops.xlate_clkctrl)
781 return NULL;
783 addr = soc_ops.xlate_clkctrl(oh);
784 if (!addr)
785 return NULL;
787 pr_debug("%s: %s: addr=%x\n", __func__, oh->name, addr);
789 list_for_each_entry(provider, &clkctrl_providers, link) {
790 if (provider->addr <= addr &&
791 provider->addr + provider->size >= addr) {
792 struct of_phandle_args clkspec;
794 clkspec.np = provider->node;
795 clkspec.args_count = 2;
796 clkspec.args[0] = addr - provider->addr -
797 provider->offset;
798 clkspec.args[1] = 0;
800 clk = of_clk_get_from_provider(&clkspec);
802 pr_debug("%s: %s got %p (offset=%x, provider=%s)\n",
803 __func__, oh->name, clk, clkspec.args[0],
804 provider->node->parent->name);
806 return clk;
807 }
808 }
810 return NULL;
811 }
813 /**
814 * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
815 * @oh: struct omap_hwmod *
816 *
817 * Called from _init_clocks(). Populates the @oh _clk (main
818 * functional clock pointer) if a clock matching the hwmod name is found,
819 * or a main_clk is present. Returns 0 on success or -EINVAL on error.
820 */
821 static int _init_main_clk(struct omap_hwmod *oh)
822 {
823 int ret = 0;
824 struct clk *clk = NULL;
826 clk = _lookup_clkctrl_clk(oh);
828 if (!IS_ERR_OR_NULL(clk)) {
829 pr_debug("%s: mapped main_clk %s for %s\n", __func__,
830 __clk_get_name(clk), oh->name);
831 oh->main_clk = __clk_get_name(clk);
832 oh->_clk = clk;
833 soc_ops.disable_direct_prcm(oh);
834 } else {
835 if (!oh->main_clk)
836 return 0;
838 oh->_clk = clk_get(NULL, oh->main_clk);
839 }
841 if (IS_ERR(oh->_clk)) {
842 pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
843 oh->name, oh->main_clk);
844 return -EINVAL;
845 }
846 /*
847 * HACK: This needs a re-visit once clk_prepare() is implemented
848 * to do something meaningful. Today its just a no-op.
849 * If clk_prepare() is used at some point to do things like
850 * voltage scaling etc, then this would have to be moved to
851 * some point where subsystems like i2c and pmic become
852 * available.
853 */
854 clk_prepare(oh->_clk);
856 if (!_get_clkdm(oh))
857 pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
858 oh->name, oh->main_clk);
860 return ret;
861 }
863 /**
864 * _init_interface_clks - get a struct clk * for the the hwmod's interface clks
865 * @oh: struct omap_hwmod *
866 *
867 * Called from _init_clocks(). Populates the @oh OCP slave interface
868 * clock pointers. Returns 0 on success or -EINVAL on error.
869 */
870 static int _init_interface_clks(struct omap_hwmod *oh)
871 {
872 struct omap_hwmod_ocp_if *os;
873 struct clk *c;
874 int ret = 0;
876 list_for_each_entry(os, &oh->slave_ports, node) {
877 if (!os->clk)
878 continue;
880 c = clk_get(NULL, os->clk);
881 if (IS_ERR(c)) {
882 pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
883 oh->name, os->clk);
884 ret = -EINVAL;
885 continue;
886 }
887 os->_clk = c;
888 /*
889 * HACK: This needs a re-visit once clk_prepare() is implemented
890 * to do something meaningful. Today its just a no-op.
891 * If clk_prepare() is used at some point to do things like
892 * voltage scaling etc, then this would have to be moved to
893 * some point where subsystems like i2c and pmic become
894 * available.
895 */
896 clk_prepare(os->_clk);
897 }
899 return ret;
900 }
902 /**
903 * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
904 * @oh: struct omap_hwmod *
905 *
906 * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
907 * clock pointers. Returns 0 on success or -EINVAL on error.
908 */
909 static int _init_opt_clks(struct omap_hwmod *oh)
910 {
911 struct omap_hwmod_opt_clk *oc;
912 struct clk *c;
913 int i;
914 int ret = 0;
916 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
917 c = clk_get(NULL, oc->clk);
918 if (IS_ERR(c)) {
919 pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
920 oh->name, oc->clk);
921 ret = -EINVAL;
922 continue;
923 }
924 oc->_clk = c;
925 /*
926 * HACK: This needs a re-visit once clk_prepare() is implemented
927 * to do something meaningful. Today its just a no-op.
928 * If clk_prepare() is used at some point to do things like
929 * voltage scaling etc, then this would have to be moved to
930 * some point where subsystems like i2c and pmic become
931 * available.
932 */
933 clk_prepare(oc->_clk);
934 }
936 return ret;
937 }
939 static void _enable_optional_clocks(struct omap_hwmod *oh)
940 {
941 struct omap_hwmod_opt_clk *oc;
942 int i;
944 pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
946 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
947 if (oc->_clk) {
948 pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
949 __clk_get_name(oc->_clk));
950 clk_enable(oc->_clk);
951 }
952 }
954 static void _disable_optional_clocks(struct omap_hwmod *oh)
955 {
956 struct omap_hwmod_opt_clk *oc;
957 int i;
959 pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
961 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
962 if (oc->_clk) {
963 pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
964 __clk_get_name(oc->_clk));
965 clk_disable(oc->_clk);
966 }
967 }
969 /**
970 * _enable_clocks - enable hwmod main clock and interface clocks
971 * @oh: struct omap_hwmod *
972 *
973 * Enables all clocks necessary for register reads and writes to succeed
974 * on the hwmod @oh. Returns 0.
975 */
976 static int _enable_clocks(struct omap_hwmod *oh)
977 {
978 struct omap_hwmod_ocp_if *os;
980 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
982 if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
983 _enable_optional_clocks(oh);
985 if (oh->_clk)
986 clk_enable(oh->_clk);
988 list_for_each_entry(os, &oh->slave_ports, node) {
989 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
990 clk_enable(os->_clk);
991 }
993 /* The opt clocks are controlled by the device driver. */
995 return 0;
996 }
998 /**
999 * _omap4_clkctrl_managed_by_clkfwk - true if clkctrl managed by clock framework
1000 * @oh: struct omap_hwmod *
1001 */
1002 static bool _omap4_clkctrl_managed_by_clkfwk(struct omap_hwmod *oh)
1003 {
1004 if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK)
1005 return true;
1007 return false;
1008 }
1010 /**
1011 * _omap4_has_clkctrl_clock - returns true if a module has clkctrl clock
1012 * @oh: struct omap_hwmod *
1013 */
1014 static bool _omap4_has_clkctrl_clock(struct omap_hwmod *oh)
1015 {
1016 if (oh->prcm.omap4.clkctrl_offs)
1017 return true;
1019 if (!oh->prcm.omap4.clkctrl_offs &&
1020 oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET)
1021 return true;
1023 return false;
1024 }
1026 /**
1027 * _disable_clocks - disable hwmod main clock and interface clocks
1028 * @oh: struct omap_hwmod *
1029 *
1030 * Disables the hwmod @oh main functional and interface clocks. Returns 0.
1031 */
1032 static int _disable_clocks(struct omap_hwmod *oh)
1033 {
1034 struct omap_hwmod_ocp_if *os;
1036 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
1038 if (oh->_clk)
1039 clk_disable(oh->_clk);
1041 list_for_each_entry(os, &oh->slave_ports, node) {
1042 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
1043 clk_disable(os->_clk);
1044 }
1046 if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
1047 _disable_optional_clocks(oh);
1049 /* The opt clocks are controlled by the device driver. */
1051 return 0;
1052 }
1054 /**
1055 * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4
1056 * @oh: struct omap_hwmod *
1057 *
1058 * Enables the PRCM module mode related to the hwmod @oh.
1059 * No return value.
1060 */
1061 static void _omap4_enable_module(struct omap_hwmod *oh)
1062 {
1063 if (!oh->clkdm || !oh->prcm.omap4.modulemode ||
1064 _omap4_clkctrl_managed_by_clkfwk(oh))
1065 return;
1067 pr_debug("omap_hwmod: %s: %s: %d\n",
1068 oh->name, __func__, oh->prcm.omap4.modulemode);
1070 omap_cm_module_enable(oh->prcm.omap4.modulemode,
1071 oh->clkdm->prcm_partition,
1072 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs);
1073 }
1075 /**
1076 * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
1077 * @oh: struct omap_hwmod *
1078 *
1079 * Wait for a module @oh to enter slave idle. Returns 0 if the module
1080 * does not have an IDLEST bit or if the module successfully enters
1081 * slave idle; otherwise, pass along the return value of the
1082 * appropriate *_cm*_wait_module_idle() function.
1083 */
1084 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
1085 {
1086 if (!oh)
1087 return -EINVAL;
1089 if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
1090 return 0;
1092 if (oh->flags & HWMOD_NO_IDLEST)
1093 return 0;
1095 if (_omap4_clkctrl_managed_by_clkfwk(oh))
1096 return 0;
1098 if (!_omap4_has_clkctrl_clock(oh))
1099 return 0;
1101 return omap_cm_wait_module_idle(oh->clkdm->prcm_partition,
1102 oh->clkdm->cm_inst,
1103 oh->prcm.omap4.clkctrl_offs, 0);
1104 }
1106 /**
1107 * _save_mpu_port_index - find and save the index to @oh's MPU port
1108 * @oh: struct omap_hwmod *
1109 *
1110 * Determines the array index of the OCP slave port that the MPU uses
1111 * to address the device, and saves it into the struct omap_hwmod.
1112 * Intended to be called during hwmod registration only. No return
1113 * value.
1114 */
1115 static void __init _save_mpu_port_index(struct omap_hwmod *oh)
1116 {
1117 struct omap_hwmod_ocp_if *os = NULL;
1119 if (!oh)
1120 return;
1122 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
1124 list_for_each_entry(os, &oh->slave_ports, node) {
1125 if (os->user & OCP_USER_MPU) {
1126 oh->_mpu_port = os;
1127 oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
1128 break;
1129 }
1130 }
1132 return;
1133 }
1135 /**
1136 * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
1137 * @oh: struct omap_hwmod *
1138 *
1139 * Given a pointer to a struct omap_hwmod record @oh, return a pointer
1140 * to the struct omap_hwmod_ocp_if record that is used by the MPU to
1141 * communicate with the IP block. This interface need not be directly
1142 * connected to the MPU (and almost certainly is not), but is directly
1143 * connected to the IP block represented by @oh. Returns a pointer
1144 * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
1145 * error or if there does not appear to be a path from the MPU to this
1146 * IP block.
1147 */
1148 static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
1149 {
1150 if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
1151 return NULL;
1153 return oh->_mpu_port;
1154 };
1156 /**
1157 * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
1158 * @oh: struct omap_hwmod *
1159 *
1160 * Ensure that the OCP_SYSCONFIG register for the IP block represented
1161 * by @oh is set to indicate to the PRCM that the IP block is active.
1162 * Usually this means placing the module into smart-idle mode and
1163 * smart-standby, but if there is a bug in the automatic idle handling
1164 * for the IP block, it may need to be placed into the force-idle or
1165 * no-idle variants of these modes. No return value.
1166 */
1167 static void _enable_sysc(struct omap_hwmod *oh)
1168 {
1169 u8 idlemode, sf;
1170 u32 v;
1171 bool clkdm_act;
1172 struct clockdomain *clkdm;
1174 if (!oh->class->sysc)
1175 return;
1177 /*
1178 * Wait until reset has completed, this is needed as the IP
1179 * block is reset automatically by hardware in some cases
1180 * (off-mode for example), and the drivers require the
1181 * IP to be ready when they access it
1182 */
1183 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1184 _enable_optional_clocks(oh);
1185 _wait_softreset_complete(oh);
1186 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1187 _disable_optional_clocks(oh);
1189 v = oh->_sysc_cache;
1190 sf = oh->class->sysc->sysc_flags;
1192 clkdm = _get_clkdm(oh);
1193 if (sf & SYSC_HAS_SIDLEMODE) {
1194 if (oh->flags & HWMOD_SWSUP_SIDLE ||
1195 oh->flags & HWMOD_SWSUP_SIDLE_ACT) {
1196 idlemode = HWMOD_IDLEMODE_NO;
1197 } else {
1198 if (sf & SYSC_HAS_ENAWAKEUP)
1199 _enable_wakeup(oh, &v);
1200 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1201 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1202 else
1203 idlemode = HWMOD_IDLEMODE_SMART;
1204 }
1206 /*
1207 * This is special handling for some IPs like
1208 * 32k sync timer. Force them to idle!
1209 */
1210 clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU);
1211 if (clkdm_act && !(oh->class->sysc->idlemodes &
1212 (SIDLE_SMART | SIDLE_SMART_WKUP)))
1213 idlemode = HWMOD_IDLEMODE_FORCE;
1215 _set_slave_idlemode(oh, idlemode, &v);
1216 }
1218 if (sf & SYSC_HAS_MIDLEMODE) {
1219 if (oh->flags & HWMOD_FORCE_MSTANDBY) {
1220 idlemode = HWMOD_IDLEMODE_FORCE;
1221 } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
1222 idlemode = HWMOD_IDLEMODE_NO;
1223 } else {
1224 if (sf & SYSC_HAS_ENAWAKEUP)
1225 _enable_wakeup(oh, &v);
1226 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
1227 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1228 else
1229 idlemode = HWMOD_IDLEMODE_SMART;
1230 }
1231 _set_master_standbymode(oh, idlemode, &v);
1232 }
1234 /*
1235 * XXX The clock framework should handle this, by
1236 * calling into this code. But this must wait until the
1237 * clock structures are tagged with omap_hwmod entries
1238 */
1239 if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
1240 (sf & SYSC_HAS_CLOCKACTIVITY))
1241 _set_clockactivity(oh, CLOCKACT_TEST_ICLK, &v);
1243 _write_sysconfig(v, oh);
1245 /*
1246 * Set the autoidle bit only after setting the smartidle bit
1247 * Setting this will not have any impact on the other modules.
1248 */
1249 if (sf & SYSC_HAS_AUTOIDLE) {
1250 idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
1251 0 : 1;
1252 _set_module_autoidle(oh, idlemode, &v);
1253 _write_sysconfig(v, oh);
1254 }
1255 }
1257 /**
1258 * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
1259 * @oh: struct omap_hwmod *
1260 *
1261 * If module is marked as SWSUP_SIDLE, force the module into slave
1262 * idle; otherwise, configure it for smart-idle. If module is marked
1263 * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
1264 * configure it for smart-standby. No return value.
1265 */
1266 static void _idle_sysc(struct omap_hwmod *oh)
1267 {
1268 u8 idlemode, sf;
1269 u32 v;
1271 if (!oh->class->sysc)
1272 return;
1274 v = oh->_sysc_cache;
1275 sf = oh->class->sysc->sysc_flags;
1277 if (sf & SYSC_HAS_SIDLEMODE) {
1278 if (oh->flags & HWMOD_SWSUP_SIDLE) {
1279 idlemode = HWMOD_IDLEMODE_FORCE;
1280 } else {
1281 if (sf & SYSC_HAS_ENAWAKEUP)
1282 _enable_wakeup(oh, &v);
1283 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1284 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1285 else
1286 idlemode = HWMOD_IDLEMODE_SMART;
1287 }
1288 _set_slave_idlemode(oh, idlemode, &v);
1289 }
1291 if (sf & SYSC_HAS_MIDLEMODE) {
1292 if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
1293 (oh->flags & HWMOD_FORCE_MSTANDBY)) {
1294 idlemode = HWMOD_IDLEMODE_FORCE;
1295 } else {
1296 if (sf & SYSC_HAS_ENAWAKEUP)
1297 _enable_wakeup(oh, &v);
1298 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
1299 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1300 else
1301 idlemode = HWMOD_IDLEMODE_SMART;
1302 }
1303 _set_master_standbymode(oh, idlemode, &v);
1304 }
1306 /* If the cached value is the same as the new value, skip the write */
1307 if (oh->_sysc_cache != v)
1308 _write_sysconfig(v, oh);
1309 }
1311 /**
1312 * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
1313 * @oh: struct omap_hwmod *
1314 *
1315 * Force the module into slave idle and master suspend. No return
1316 * value.
1317 */
1318 static void _shutdown_sysc(struct omap_hwmod *oh)
1319 {
1320 u32 v;
1321 u8 sf;
1323 if (!oh->class->sysc)
1324 return;
1326 v = oh->_sysc_cache;
1327 sf = oh->class->sysc->sysc_flags;
1329 if (sf & SYSC_HAS_SIDLEMODE)
1330 _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
1332 if (sf & SYSC_HAS_MIDLEMODE)
1333 _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
1335 if (sf & SYSC_HAS_AUTOIDLE)
1336 _set_module_autoidle(oh, 1, &v);
1338 _write_sysconfig(v, oh);
1339 }
1341 /**
1342 * _lookup - find an omap_hwmod by name
1343 * @name: find an omap_hwmod by name
1344 *
1345 * Return a pointer to an omap_hwmod by name, or NULL if not found.
1346 */
1347 static struct omap_hwmod *_lookup(const char *name)
1348 {
1349 struct omap_hwmod *oh, *temp_oh;
1351 oh = NULL;
1353 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
1354 if (!strcmp(name, temp_oh->name)) {
1355 oh = temp_oh;
1356 break;
1357 }
1358 }
1360 return oh;
1361 }
1363 /**
1364 * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
1365 * @oh: struct omap_hwmod *
1366 *
1367 * Convert a clockdomain name stored in a struct omap_hwmod into a
1368 * clockdomain pointer, and save it into the struct omap_hwmod.
1369 * Return -EINVAL if the clkdm_name lookup failed.
1370 */
1371 static int _init_clkdm(struct omap_hwmod *oh)
1372 {
1373 if (!oh->clkdm_name) {
1374 pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
1375 return 0;
1376 }
1378 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1379 if (!oh->clkdm) {
1380 pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n",
1381 oh->name, oh->clkdm_name);
1382 return 0;
1383 }
1385 pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
1386 oh->name, oh->clkdm_name);
1388 return 0;
1389 }
1391 /**
1392 * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
1393 * well the clockdomain.
1394 * @oh: struct omap_hwmod *
1395 * @np: device_node mapped to this hwmod
1396 *
1397 * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
1398 * Resolves all clock names embedded in the hwmod. Returns 0 on
1399 * success, or a negative error code on failure.
1400 */
1401 static int _init_clocks(struct omap_hwmod *oh, struct device_node *np)
1402 {
1403 int ret = 0;
1405 if (oh->_state != _HWMOD_STATE_REGISTERED)
1406 return 0;
1408 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
1410 if (soc_ops.init_clkdm)
1411 ret |= soc_ops.init_clkdm(oh);
1413 ret |= _init_main_clk(oh);
1414 ret |= _init_interface_clks(oh);
1415 ret |= _init_opt_clks(oh);
1417 if (!ret)
1418 oh->_state = _HWMOD_STATE_CLKS_INITED;
1419 else
1420 pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
1422 return ret;
1423 }
1425 /**
1426 * _lookup_hardreset - fill register bit info for this hwmod/reset line
1427 * @oh: struct omap_hwmod *
1428 * @name: name of the reset line in the context of this hwmod
1429 * @ohri: struct omap_hwmod_rst_info * that this function will fill in
1430 *
1431 * Return the bit position of the reset line that match the
1432 * input name. Return -ENOENT if not found.
1433 */
1434 static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
1435 struct omap_hwmod_rst_info *ohri)
1436 {
1437 int i;
1439 for (i = 0; i < oh->rst_lines_cnt; i++) {
1440 const char *rst_line = oh->rst_lines[i].name;
1441 if (!strcmp(rst_line, name)) {
1442 ohri->rst_shift = oh->rst_lines[i].rst_shift;
1443 ohri->st_shift = oh->rst_lines[i].st_shift;
1444 pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
1445 oh->name, __func__, rst_line, ohri->rst_shift,
1446 ohri->st_shift);
1448 return 0;
1449 }
1450 }
1452 return -ENOENT;
1453 }
1455 /**
1456 * _assert_hardreset - assert the HW reset line of submodules
1457 * contained in the hwmod module.
1458 * @oh: struct omap_hwmod *
1459 * @name: name of the reset line to lookup and assert
1460 *
1461 * Some IP like dsp, ipu or iva contain processor that require an HW
1462 * reset line to be assert / deassert in order to enable fully the IP.
1463 * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1464 * asserting the hardreset line on the currently-booted SoC, or passes
1465 * along the return value from _lookup_hardreset() or the SoC's
1466 * assert_hardreset code.
1467 */
1468 static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1469 {
1470 struct omap_hwmod_rst_info ohri;
1471 int ret = -EINVAL;
1473 if (!oh)
1474 return -EINVAL;
1476 if (!soc_ops.assert_hardreset)
1477 return -ENOSYS;
1479 ret = _lookup_hardreset(oh, name, &ohri);
1480 if (ret < 0)
1481 return ret;
1483 ret = soc_ops.assert_hardreset(oh, &ohri);
1485 return ret;
1486 }
1488 /**
1489 * _deassert_hardreset - deassert the HW reset line of submodules contained
1490 * in the hwmod module.
1491 * @oh: struct omap_hwmod *
1492 * @name: name of the reset line to look up and deassert
1493 *
1494 * Some IP like dsp, ipu or iva contain processor that require an HW
1495 * reset line to be assert / deassert in order to enable fully the IP.
1496 * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1497 * deasserting the hardreset line on the currently-booted SoC, or passes
1498 * along the return value from _lookup_hardreset() or the SoC's
1499 * deassert_hardreset code.
1500 */
1501 static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1502 {
1503 struct omap_hwmod_rst_info ohri;
1504 int ret = -EINVAL;
1506 if (!oh)
1507 return -EINVAL;
1509 if (!soc_ops.deassert_hardreset)
1510 return -ENOSYS;
1512 ret = _lookup_hardreset(oh, name, &ohri);
1513 if (ret < 0)
1514 return ret;
1516 if (oh->clkdm) {
1517 /*
1518 * A clockdomain must be in SW_SUP otherwise reset
1519 * might not be completed. The clockdomain can be set
1520 * in HW_AUTO only when the module become ready.
1521 */
1522 clkdm_deny_idle(oh->clkdm);
1523 ret = clkdm_hwmod_enable(oh->clkdm, oh);
1524 if (ret) {
1525 WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
1526 oh->name, oh->clkdm->name, ret);
1527 return ret;
1528 }
1529 }
1531 _enable_clocks(oh);
1532 if (soc_ops.enable_module)
1533 soc_ops.enable_module(oh);
1535 ret = soc_ops.deassert_hardreset(oh, &ohri);
1537 if (soc_ops.disable_module)
1538 soc_ops.disable_module(oh);
1539 _disable_clocks(oh);
1541 if (ret == -EBUSY)
1542 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
1544 if (oh->clkdm) {
1545 /*
1546 * Set the clockdomain to HW_AUTO, assuming that the
1547 * previous state was HW_AUTO.
1548 */
1549 clkdm_allow_idle(oh->clkdm);
1551 clkdm_hwmod_disable(oh->clkdm, oh);
1552 }
1554 return ret;
1555 }
1557 /**
1558 * _read_hardreset - read the HW reset line state of submodules
1559 * contained in the hwmod module
1560 * @oh: struct omap_hwmod *
1561 * @name: name of the reset line to look up and read
1562 *
1563 * Return the state of the reset line. Returns -EINVAL if @oh is
1564 * null, -ENOSYS if we have no way of reading the hardreset line
1565 * status on the currently-booted SoC, or passes along the return
1566 * value from _lookup_hardreset() or the SoC's is_hardreset_asserted
1567 * code.
1568 */
1569 static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1570 {
1571 struct omap_hwmod_rst_info ohri;
1572 int ret = -EINVAL;
1574 if (!oh)
1575 return -EINVAL;
1577 if (!soc_ops.is_hardreset_asserted)
1578 return -ENOSYS;
1580 ret = _lookup_hardreset(oh, name, &ohri);
1581 if (ret < 0)
1582 return ret;
1584 return soc_ops.is_hardreset_asserted(oh, &ohri);
1585 }
1587 /**
1588 * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
1589 * @oh: struct omap_hwmod *
1590 *
1591 * If all hardreset lines associated with @oh are asserted, then return true.
1592 * Otherwise, if part of @oh is out hardreset or if no hardreset lines
1593 * associated with @oh are asserted, then return false.
1594 * This function is used to avoid executing some parts of the IP block
1595 * enable/disable sequence if its hardreset line is set.
1596 */
1597 static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
1598 {
1599 int i, rst_cnt = 0;
1601 if (oh->rst_lines_cnt == 0)
1602 return false;
1604 for (i = 0; i < oh->rst_lines_cnt; i++)
1605 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
1606 rst_cnt++;
1608 if (oh->rst_lines_cnt == rst_cnt)
1609 return true;
1611 return false;
1612 }
1614 /**
1615 * _are_any_hardreset_lines_asserted - return true if any part of @oh is
1616 * hard-reset
1617 * @oh: struct omap_hwmod *
1618 *
1619 * If any hardreset lines associated with @oh are asserted, then
1620 * return true. Otherwise, if no hardreset lines associated with @oh
1621 * are asserted, or if @oh has no hardreset lines, then return false.
1622 * This function is used to avoid executing some parts of the IP block
1623 * enable/disable sequence if any hardreset line is set.
1624 */
1625 static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
1626 {
1627 int rst_cnt = 0;
1628 int i;
1630 for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++)
1631 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
1632 rst_cnt++;
1634 return (rst_cnt) ? true : false;
1635 }
1637 /**
1638 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
1639 * @oh: struct omap_hwmod *
1640 *
1641 * Disable the PRCM module mode related to the hwmod @oh.
1642 * Return EINVAL if the modulemode is not supported and 0 in case of success.
1643 */
1644 static int _omap4_disable_module(struct omap_hwmod *oh)
1645 {
1646 int v;
1648 if (!oh->clkdm || !oh->prcm.omap4.modulemode ||
1649 _omap4_clkctrl_managed_by_clkfwk(oh))
1650 return -EINVAL;
1652 /*
1653 * Since integration code might still be doing something, only
1654 * disable if all lines are under hardreset.
1655 */
1656 if (_are_any_hardreset_lines_asserted(oh))
1657 return 0;
1659 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
1661 omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst,
1662 oh->prcm.omap4.clkctrl_offs);
1664 v = _omap4_wait_target_disable(oh);
1665 if (v)
1666 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1667 oh->name);
1669 return 0;
1670 }
1672 /**
1673 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
1674 * @oh: struct omap_hwmod *
1675 *
1676 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
1677 * enabled for this to work. Returns -ENOENT if the hwmod cannot be
1678 * reset this way, -EINVAL if the hwmod is in the wrong state,
1679 * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
1680 *
1681 * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
1682 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
1683 * use the SYSCONFIG softreset bit to provide the status.
1684 *
1685 * Note that some IP like McBSP do have reset control but don't have
1686 * reset status.
1687 */
1688 static int _ocp_softreset(struct omap_hwmod *oh)
1689 {
1690 u32 v;
1691 int c = 0;
1692 int ret = 0;
1694 if (!oh->class->sysc ||
1695 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
1696 return -ENOENT;
1698 /* clocks must be on for this operation */
1699 if (oh->_state != _HWMOD_STATE_ENABLED) {
1700 pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
1701 oh->name);
1702 return -EINVAL;
1703 }
1705 /* For some modules, all optionnal clocks need to be enabled as well */
1706 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1707 _enable_optional_clocks(oh);
1709 pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
1711 v = oh->_sysc_cache;
1712 ret = _set_softreset(oh, &v);
1713 if (ret)
1714 goto dis_opt_clks;
1716 _write_sysconfig(v, oh);
1718 if (oh->class->sysc->srst_udelay)
1719 udelay(oh->class->sysc->srst_udelay);
1721 c = _wait_softreset_complete(oh);
1722 if (c == MAX_MODULE_SOFTRESET_WAIT) {
1723 pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1724 oh->name, MAX_MODULE_SOFTRESET_WAIT);
1725 ret = -ETIMEDOUT;
1726 goto dis_opt_clks;
1727 } else {
1728 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
1729 }
1731 ret = _clear_softreset(oh, &v);
1732 if (ret)
1733 goto dis_opt_clks;
1735 _write_sysconfig(v, oh);
1737 /*
1738 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
1739 * _wait_target_ready() or _reset()
1740 */
1742 dis_opt_clks:
1743 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1744 _disable_optional_clocks(oh);
1746 return ret;
1747 }
1749 /**
1750 * _reset - reset an omap_hwmod
1751 * @oh: struct omap_hwmod *
1752 *
1753 * Resets an omap_hwmod @oh. If the module has a custom reset
1754 * function pointer defined, then call it to reset the IP block, and
1755 * pass along its return value to the caller. Otherwise, if the IP
1756 * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
1757 * associated with it, call a function to reset the IP block via that
1758 * method, and pass along the return value to the caller. Finally, if
1759 * the IP block has some hardreset lines associated with it, assert
1760 * all of those, but do _not_ deassert them. (This is because driver
1761 * authors have expressed an apparent requirement to control the
1762 * deassertion of the hardreset lines themselves.)
1763 *
1764 * The default software reset mechanism for most OMAP IP blocks is
1765 * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some
1766 * hwmods cannot be reset via this method. Some are not targets and
1767 * therefore have no OCP header registers to access. Others (like the
1768 * IVA) have idiosyncratic reset sequences. So for these relatively
1769 * rare cases, custom reset code can be supplied in the struct
1770 * omap_hwmod_class .reset function pointer.
1771 *
1772 * _set_dmadisable() is called to set the DMADISABLE bit so that it
1773 * does not prevent idling of the system. This is necessary for cases
1774 * where ROMCODE/BOOTLOADER uses dma and transfers control to the
1775 * kernel without disabling dma.
1776 *
1777 * Passes along the return value from either _ocp_softreset() or the
1778 * custom reset function - these must return -EINVAL if the hwmod
1779 * cannot be reset this way or if the hwmod is in the wrong state,
1780 * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
1781 */
1782 static int _reset(struct omap_hwmod *oh)
1783 {
1784 int i, r;
1786 pr_debug("omap_hwmod: %s: resetting\n", oh->name);
1788 if (oh->class->reset) {
1789 r = oh->class->reset(oh);
1790 } else {
1791 if (oh->rst_lines_cnt > 0) {
1792 for (i = 0; i < oh->rst_lines_cnt; i++)
1793 _assert_hardreset(oh, oh->rst_lines[i].name);
1794 return 0;
1795 } else {
1796 r = _ocp_softreset(oh);
1797 if (r == -ENOENT)
1798 r = 0;
1799 }
1800 }
1802 _set_dmadisable(oh);
1804 /*
1805 * OCP_SYSCONFIG bits need to be reprogrammed after a
1806 * softreset. The _enable() function should be split to avoid
1807 * the rewrite of the OCP_SYSCONFIG register.
1808 */
1809 if (oh->class->sysc) {
1810 _update_sysc_cache(oh);
1811 _enable_sysc(oh);
1812 }
1814 return r;
1815 }
1817 /**
1818 * _omap4_update_context_lost - increment hwmod context loss counter if
1819 * hwmod context was lost, and clear hardware context loss reg
1820 * @oh: hwmod to check for context loss
1821 *
1822 * If the PRCM indicates that the hwmod @oh lost context, increment
1823 * our in-memory context loss counter, and clear the RM_*_CONTEXT
1824 * bits. No return value.
1825 */
1826 static void _omap4_update_context_lost(struct omap_hwmod *oh)
1827 {
1828 if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT)
1829 return;
1831 if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition,
1832 oh->clkdm->pwrdm.ptr->prcm_offs,
1833 oh->prcm.omap4.context_offs))
1834 return;
1836 oh->prcm.omap4.context_lost_counter++;
1837 prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition,
1838 oh->clkdm->pwrdm.ptr->prcm_offs,
1839 oh->prcm.omap4.context_offs);
1840 }
1842 /**
1843 * _omap4_get_context_lost - get context loss counter for a hwmod
1844 * @oh: hwmod to get context loss counter for
1845 *
1846 * Returns the in-memory context loss counter for a hwmod.
1847 */
1848 static int _omap4_get_context_lost(struct omap_hwmod *oh)
1849 {
1850 return oh->prcm.omap4.context_lost_counter;
1851 }
1853 /**
1854 * _enable_preprogram - Pre-program an IP block during the _enable() process
1855 * @oh: struct omap_hwmod *
1856 *
1857 * Some IP blocks (such as AESS) require some additional programming
1858 * after enable before they can enter idle. If a function pointer to
1859 * do so is present in the hwmod data, then call it and pass along the
1860 * return value; otherwise, return 0.
1861 */
1862 static int _enable_preprogram(struct omap_hwmod *oh)
1863 {
1864 if (!oh->class->enable_preprogram)
1865 return 0;
1867 return oh->class->enable_preprogram(oh);
1868 }
1870 /**
1871 * _enable - enable an omap_hwmod
1872 * @oh: struct omap_hwmod *
1873 *
1874 * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
1875 * register target. Returns -EINVAL if the hwmod is in the wrong
1876 * state or passes along the return value of _wait_target_ready().
1877 */
1878 static int _enable(struct omap_hwmod *oh)
1879 {
1880 int r;
1882 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1884 /*
1885 * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
1886 * state at init.
1887 */
1888 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
1889 oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
1890 return 0;
1891 }
1893 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1894 oh->_state != _HWMOD_STATE_IDLE &&
1895 oh->_state != _HWMOD_STATE_DISABLED) {
1896 WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
1897 oh->name);
1898 return -EINVAL;
1899 }
1901 /*
1902 * If an IP block contains HW reset lines and all of them are
1903 * asserted, we let integration code associated with that
1904 * block handle the enable. We've received very little
1905 * information on what those driver authors need, and until
1906 * detailed information is provided and the driver code is
1907 * posted to the public lists, this is probably the best we
1908 * can do.
1909 */
1910 if (_are_all_hardreset_lines_asserted(oh))
1911 return 0;
1913 _add_initiator_dep(oh, mpu_oh);
1915 if (oh->clkdm) {
1916 /*
1917 * A clockdomain must be in SW_SUP before enabling
1918 * completely the module. The clockdomain can be set
1919 * in HW_AUTO only when the module become ready.
1920 */
1921 clkdm_deny_idle(oh->clkdm);
1922 r = clkdm_hwmod_enable(oh->clkdm, oh);
1923 if (r) {
1924 WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
1925 oh->name, oh->clkdm->name, r);
1926 return r;
1927 }
1928 }
1930 _enable_clocks(oh);
1931 if (soc_ops.enable_module)
1932 soc_ops.enable_module(oh);
1933 if (oh->flags & HWMOD_BLOCK_WFI)
1934 cpu_idle_poll_ctrl(true);
1936 if (soc_ops.update_context_lost)
1937 soc_ops.update_context_lost(oh);
1939 r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
1940 -EINVAL;
1941 if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO))
1942 clkdm_allow_idle(oh->clkdm);
1944 if (!r) {
1945 oh->_state = _HWMOD_STATE_ENABLED;
1947 /* Access the sysconfig only if the target is ready */
1948 if (oh->class->sysc) {
1949 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1950 _update_sysc_cache(oh);
1951 _enable_sysc(oh);
1952 }
1953 r = _enable_preprogram(oh);
1954 } else {
1955 if (soc_ops.disable_module)
1956 soc_ops.disable_module(oh);
1957 _disable_clocks(oh);
1958 pr_err("omap_hwmod: %s: _wait_target_ready failed: %d\n",
1959 oh->name, r);
1961 if (oh->clkdm)
1962 clkdm_hwmod_disable(oh->clkdm, oh);
1963 }
1965 return r;
1966 }
1968 /**
1969 * _idle - idle an omap_hwmod
1970 * @oh: struct omap_hwmod *
1971 *
1972 * Idles an omap_hwmod @oh. This should be called once the hwmod has
1973 * no further work. Returns -EINVAL if the hwmod is in the wrong
1974 * state or returns 0.
1975 */
1976 static int _idle(struct omap_hwmod *oh)
1977 {
1978 if (oh->flags & HWMOD_NO_IDLE) {
1979 oh->_int_flags |= _HWMOD_SKIP_ENABLE;
1980 return 0;
1981 }
1983 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1985 if (_are_all_hardreset_lines_asserted(oh))
1986 return 0;
1988 if (oh->_state != _HWMOD_STATE_ENABLED) {
1989 WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",
1990 oh->name);
1991 return -EINVAL;
1992 }
1994 if (oh->class->sysc)
1995 _idle_sysc(oh);
1996 _del_initiator_dep(oh, mpu_oh);
1998 /*
1999 * If HWMOD_CLKDM_NOAUTO is set then we don't
2000 * deny idle the clkdm again since idle was already denied
2001 * in _enable()
2002 */
2003 if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO))
2004 clkdm_deny_idle(oh->clkdm);
2006 if (oh->flags & HWMOD_BLOCK_WFI)
2007 cpu_idle_poll_ctrl(false);
2008 if (soc_ops.disable_module)
2009 soc_ops.disable_module(oh);
2011 /*
2012 * The module must be in idle mode before disabling any parents
2013 * clocks. Otherwise, the parent clock might be disabled before
2014 * the module transition is done, and thus will prevent the
2015 * transition to complete properly.
2016 */
2017 _disable_clocks(oh);
2018 if (oh->clkdm) {
2019 clkdm_allow_idle(oh->clkdm);
2020 clkdm_hwmod_disable(oh->clkdm, oh);
2021 }
2023 oh->_state = _HWMOD_STATE_IDLE;
2025 return 0;
2026 }
2028 /**
2029 * _shutdown - shutdown an omap_hwmod
2030 * @oh: struct omap_hwmod *
2031 *
2032 * Shut down an omap_hwmod @oh. This should be called when the driver
2033 * used for the hwmod is removed or unloaded or if the driver is not
2034 * used by the system. Returns -EINVAL if the hwmod is in the wrong
2035 * state or returns 0.
2036 */
2037 static int _shutdown(struct omap_hwmod *oh)
2038 {
2039 int ret, i;
2040 u8 prev_state;
2042 if (_are_all_hardreset_lines_asserted(oh))
2043 return 0;
2045 if (oh->_state != _HWMOD_STATE_IDLE &&
2046 oh->_state != _HWMOD_STATE_ENABLED) {
2047 WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
2048 oh->name);
2049 return -EINVAL;
2050 }
2052 pr_debug("omap_hwmod: %s: disabling\n", oh->name);
2054 if (oh->class->pre_shutdown) {
2055 prev_state = oh->_state;
2056 if (oh->_state == _HWMOD_STATE_IDLE)
2057 _enable(oh);
2058 ret = oh->class->pre_shutdown(oh);
2059 if (ret) {
2060 if (prev_state == _HWMOD_STATE_IDLE)
2061 _idle(oh);
2062 return ret;
2063 }
2064 }
2066 if (oh->class->sysc) {
2067 if (oh->_state == _HWMOD_STATE_IDLE)
2068 _enable(oh);
2069 _shutdown_sysc(oh);
2070 }
2072 /* clocks and deps are already disabled in idle */
2073 if (oh->_state == _HWMOD_STATE_ENABLED) {
2074 _del_initiator_dep(oh, mpu_oh);
2075 /* XXX what about the other system initiators here? dma, dsp */
2076 if (oh->flags & HWMOD_BLOCK_WFI)
2077 cpu_idle_poll_ctrl(false);
2078 if (soc_ops.disable_module)
2079 soc_ops.disable_module(oh);
2080 _disable_clocks(oh);
2081 if (oh->clkdm)
2082 clkdm_hwmod_disable(oh->clkdm, oh);
2083 }
2084 /* XXX Should this code also force-disable the optional clocks? */
2086 for (i = 0; i < oh->rst_lines_cnt; i++)
2087 _assert_hardreset(oh, oh->rst_lines[i].name);
2089 oh->_state = _HWMOD_STATE_DISABLED;
2091 return 0;
2092 }
2094 static int of_dev_find_hwmod(struct device_node *np,
2095 struct omap_hwmod *oh)
2096 {
2097 int count, i, res;
2098 const char *p;
2100 count = of_property_count_strings(np, "ti,hwmods");
2101 if (count < 1)
2102 return -ENODEV;
2104 for (i = 0; i < count; i++) {
2105 res = of_property_read_string_index(np, "ti,hwmods",
2106 i, &p);
2107 if (res)
2108 continue;
2109 if (!strcmp(p, oh->name)) {
2110 pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n",
2111 np->name, i, oh->name);
2112 return i;
2113 }
2114 }
2116 return -ENODEV;
2117 }
2119 /**
2120 * of_dev_hwmod_lookup - look up needed hwmod from dt blob
2121 * @np: struct device_node *
2122 * @oh: struct omap_hwmod *
2123 * @index: index of the entry found
2124 * @found: struct device_node * found or NULL
2125 *
2126 * Parse the dt blob and find out needed hwmod. Recursive function is
2127 * implemented to take care hierarchical dt blob parsing.
2128 * Return: Returns 0 on success, -ENODEV when not found.
2129 */
2130 static int of_dev_hwmod_lookup(struct device_node *np,
2131 struct omap_hwmod *oh,
2132 int *index,
2133 struct device_node **found)
2134 {
2135 struct device_node *np0 = NULL;
2136 int res;
2138 res = of_dev_find_hwmod(np, oh);
2139 if (res >= 0) {
2140 *found = np;
2141 *index = res;
2142 return 0;
2143 }
2145 for_each_child_of_node(np, np0) {
2146 struct device_node *fc;
2147 int i;
2149 res = of_dev_hwmod_lookup(np0, oh, &i, &fc);
2150 if (res == 0) {
2151 *found = fc;
2152 *index = i;
2153 return 0;
2154 }
2155 }
2157 *found = NULL;
2158 *index = 0;
2160 return -ENODEV;
2161 }
2163 /**
2164 * omap_hwmod_parse_module_range - map module IO range from device tree
2165 * @oh: struct omap_hwmod *
2166 * @np: struct device_node *
2167 *
2168 * Parse the device tree range an interconnect target module provides
2169 * for it's child device IP blocks. This way we can support the old
2170 * "ti,hwmods" property with just dts data without a need for platform
2171 * data for IO resources. And we don't need all the child IP device
2172 * nodes available in the dts.
2173 */
2174 int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
2175 struct device_node *np,
2176 struct resource *res)
2177 {
2178 struct property *prop;
2179 const __be32 *ranges;
2180 const char *name;
2181 u32 nr_addr, nr_size;
2182 u64 base, size;
2183 int len, error;
2185 if (!res)
2186 return -EINVAL;
2188 ranges = of_get_property(np, "ranges", &len);
2189 if (!ranges)
2190 return -ENOENT;
2192 len /= sizeof(*ranges);
2194 if (len < 3)
2195 return -EINVAL;
2197 of_property_for_each_string(np, "compatible", prop, name)
2198 if (!strncmp("ti,sysc-", name, 8))
2199 break;
2201 if (!name)
2202 return -ENOENT;
2204 error = of_property_read_u32(np, "#address-cells", &nr_addr);
2205 if (error)
2206 return -ENOENT;
2208 error = of_property_read_u32(np, "#size-cells", &nr_size);
2209 if (error)
2210 return -ENOENT;
2212 if (nr_addr != 1 || nr_size != 1) {
2213 pr_err("%s: invalid range for %s->%s\n", __func__,
2214 oh->name, np->name);
2215 return -EINVAL;
2216 }
2218 ranges++;
2219 base = of_translate_address(np, ranges++);
2220 size = be32_to_cpup(ranges);
2222 pr_debug("omap_hwmod: %s %s at 0x%llx size 0x%llx\n",
2223 oh->name, np->name, base, size);
2225 res->start = base;
2226 res->end = base + size - 1;
2227 res->flags = IORESOURCE_MEM;
2229 return 0;
2230 }
2232 /**
2233 * _init_mpu_rt_base - populate the virtual address for a hwmod
2234 * @oh: struct omap_hwmod * to locate the virtual address
2235 * @data: (unused, caller should pass NULL)
2236 * @index: index of the reg entry iospace in device tree
2237 * @np: struct device_node * of the IP block's device node in the DT data
2238 *
2239 * Cache the virtual address used by the MPU to access this IP block's
2240 * registers. This address is needed early so the OCP registers that
2241 * are part of the device's address space can be ioremapped properly.
2242 *
2243 * If SYSC access is not needed, the registers will not be remapped
2244 * and non-availability of MPU access is not treated as an error.
2245 *
2246 * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and
2247 * -ENXIO on absent or invalid register target address space.
2248 */
2249 static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
2250 int index, struct device_node *np)
2251 {
2252 void __iomem *va_start = NULL;
2253 struct resource res;
2254 int error;
2256 if (!oh)
2257 return -EINVAL;
2259 _save_mpu_port_index(oh);
2261 /* if we don't need sysc access we don't need to ioremap */
2262 if (!oh->class->sysc)
2263 return 0;
2265 /* we can't continue without MPU PORT if we need sysc access */
2266 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
2267 return -ENXIO;
2269 if (!np) {
2270 pr_err("omap_hwmod: %s: no dt node\n", oh->name);
2271 return -ENXIO;
2272 }
2274 /* Do we have a dts range for the interconnect target module? */
2275 error = omap_hwmod_parse_module_range(oh, np, &res);
2276 if (!error)
2277 va_start = ioremap(res.start, resource_size(&res));
2279 /* No ranges, rely on device reg entry */
2280 if (!va_start)
2281 va_start = of_iomap(np, index + oh->mpu_rt_idx);
2282 if (!va_start) {
2283 pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n",
2284 oh->name, index, np);
2285 return -ENXIO;
2286 }
2288 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
2289 oh->name, va_start);
2291 oh->_mpu_rt_va = va_start;
2292 return 0;
2293 }
2295 /**
2296 * _init - initialize internal data for the hwmod @oh
2297 * @oh: struct omap_hwmod *
2298 * @n: (unused)
2299 *
2300 * Look up the clocks and the address space used by the MPU to access
2301 * registers belonging to the hwmod @oh. @oh must already be
2302 * registered at this point. This is the first of two phases for
2303 * hwmod initialization. Code called here does not touch any hardware
2304 * registers, it simply prepares internal data structures. Returns 0
2305 * upon success or if the hwmod isn't registered or if the hwmod's
2306 * address space is not defined, or -EINVAL upon failure.
2307 */
2308 static int __init _init(struct omap_hwmod *oh, void *data)
2309 {
2310 int r, index;
2311 struct device_node *np = NULL;
2312 struct device_node *bus;
2314 if (oh->_state != _HWMOD_STATE_REGISTERED)
2315 return 0;
2317 bus = of_find_node_by_name(NULL, "ocp");
2318 if (!bus)
2319 return -ENODEV;
2321 r = of_dev_hwmod_lookup(bus, oh, &index, &np);
2322 if (r)
2323 pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
2324 else if (np && index)
2325 pr_warn("omap_hwmod: %s using broken dt data from %s\n",
2326 oh->name, np->name);
2328 r = _init_mpu_rt_base(oh, NULL, index, np);
2329 if (r < 0) {
2330 WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
2331 oh->name);
2332 return 0;
2333 }
2335 r = _init_clocks(oh, np);
2336 if (r < 0) {
2337 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
2338 return -EINVAL;
2339 }
2341 if (np) {
2342 if (of_find_property(np, "ti,no-reset-on-init", NULL))
2343 oh->flags |= HWMOD_INIT_NO_RESET;
2344 if (of_find_property(np, "ti,no-idle-on-init", NULL))
2345 oh->flags |= HWMOD_INIT_NO_IDLE;
2346 if (of_find_property(np, "ti,no-idle", NULL))
2347 oh->flags |= HWMOD_NO_IDLE;
2348 }
2350 oh->_state = _HWMOD_STATE_INITIALIZED;
2352 return 0;
2353 }
2355 /**
2356 * _setup_iclk_autoidle - configure an IP block's interface clocks
2357 * @oh: struct omap_hwmod *
2358 *
2359 * Set up the module's interface clocks. XXX This function is still mostly
2360 * a stub; implementing this properly requires iclk autoidle usecounting in
2361 * the clock code. No return value.
2362 */
2363 static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
2364 {
2365 struct omap_hwmod_ocp_if *os;
2367 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2368 return;
2370 list_for_each_entry(os, &oh->slave_ports, node) {
2371 if (!os->_clk)
2372 continue;
2374 if (os->flags & OCPIF_SWSUP_IDLE) {
2375 /* XXX omap_iclk_deny_idle(c); */
2376 } else {
2377 /* XXX omap_iclk_allow_idle(c); */
2378 clk_enable(os->_clk);
2379 }
2380 }
2382 return;
2383 }
2385 /**
2386 * _setup_reset - reset an IP block during the setup process
2387 * @oh: struct omap_hwmod *
2388 *
2389 * Reset the IP block corresponding to the hwmod @oh during the setup
2390 * process. The IP block is first enabled so it can be successfully
2391 * reset. Returns 0 upon success or a negative error code upon
2392 * failure.
2393 */
2394 static int __init _setup_reset(struct omap_hwmod *oh)
2395 {
2396 int r;
2398 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2399 return -EINVAL;
2401 if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK)
2402 return -EPERM;
2404 if (oh->rst_lines_cnt == 0) {
2405 r = _enable(oh);
2406 if (r) {
2407 pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
2408 oh->name, oh->_state);
2409 return -EINVAL;
2410 }
2411 }
2413 if (!(oh->flags & HWMOD_INIT_NO_RESET))
2414 r = _reset(oh);
2416 return r;
2417 }
2419 /**
2420 * _setup_postsetup - transition to the appropriate state after _setup
2421 * @oh: struct omap_hwmod *
2422 *
2423 * Place an IP block represented by @oh into a "post-setup" state --
2424 * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that
2425 * this function is called at the end of _setup().) The postsetup
2426 * state for an IP block can be changed by calling
2427 * omap_hwmod_enter_postsetup_state() early in the boot process,
2428 * before one of the omap_hwmod_setup*() functions are called for the
2429 * IP block.
2430 *
2431 * The IP block stays in this state until a PM runtime-based driver is
2432 * loaded for that IP block. A post-setup state of IDLE is
2433 * appropriate for almost all IP blocks with runtime PM-enabled
2434 * drivers, since those drivers are able to enable the IP block. A
2435 * post-setup state of ENABLED is appropriate for kernels with PM
2436 * runtime disabled. The DISABLED state is appropriate for unusual IP
2437 * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
2438 * included, since the WDTIMER starts running on reset and will reset
2439 * the MPU if left active.
2440 *
2441 * This post-setup mechanism is deprecated. Once all of the OMAP
2442 * drivers have been converted to use PM runtime, and all of the IP
2443 * block data and interconnect data is available to the hwmod code, it
2444 * should be possible to replace this mechanism with a "lazy reset"
2445 * arrangement. In a "lazy reset" setup, each IP block is enabled
2446 * when the driver first probes, then all remaining IP blocks without
2447 * drivers are either shut down or enabled after the drivers have
2448 * loaded. However, this cannot take place until the above
2449 * preconditions have been met, since otherwise the late reset code
2450 * has no way of knowing which IP blocks are in use by drivers, and
2451 * which ones are unused.
2452 *
2453 * No return value.
2454 */
2455 static void __init _setup_postsetup(struct omap_hwmod *oh)
2456 {
2457 u8 postsetup_state;
2459 if (oh->rst_lines_cnt > 0)
2460 return;
2462 postsetup_state = oh->_postsetup_state;
2463 if (postsetup_state == _HWMOD_STATE_UNKNOWN)
2464 postsetup_state = _HWMOD_STATE_ENABLED;
2466 /*
2467 * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
2468 * it should be set by the core code as a runtime flag during startup
2469 */
2470 if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) &&
2471 (postsetup_state == _HWMOD_STATE_IDLE)) {
2472 oh->_int_flags |= _HWMOD_SKIP_ENABLE;
2473 postsetup_state = _HWMOD_STATE_ENABLED;
2474 }
2476 if (postsetup_state == _HWMOD_STATE_IDLE)
2477 _idle(oh);
2478 else if (postsetup_state == _HWMOD_STATE_DISABLED)
2479 _shutdown(oh);
2480 else if (postsetup_state != _HWMOD_STATE_ENABLED)
2481 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
2482 oh->name, postsetup_state);
2484 return;
2485 }
2487 /**
2488 * _setup - prepare IP block hardware for use
2489 * @oh: struct omap_hwmod *
2490 * @n: (unused, pass NULL)
2491 *
2492 * Configure the IP block represented by @oh. This may include
2493 * enabling the IP block, resetting it, and placing it into a
2494 * post-setup state, depending on the type of IP block and applicable
2495 * flags. IP blocks are reset to prevent any previous configuration
2496 * by the bootloader or previous operating system from interfering
2497 * with power management or other parts of the system. The reset can
2498 * be avoided; see omap_hwmod_no_setup_reset(). This is the second of
2499 * two phases for hwmod initialization. Code called here generally
2500 * affects the IP block hardware, or system integration hardware
2501 * associated with the IP block. Returns 0.
2502 */
2503 static int _setup(struct omap_hwmod *oh, void *data)
2504 {
2505 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2506 return 0;
2508 if (oh->parent_hwmod) {
2509 int r;
2511 r = _enable(oh->parent_hwmod);
2512 WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n",
2513 oh->name, oh->parent_hwmod->name);
2514 }
2516 _setup_iclk_autoidle(oh);
2518 if (!_setup_reset(oh))
2519 _setup_postsetup(oh);
2521 if (oh->parent_hwmod) {
2522 u8 postsetup_state;
2524 postsetup_state = oh->parent_hwmod->_postsetup_state;
2526 if (postsetup_state == _HWMOD_STATE_IDLE)
2527 _idle(oh->parent_hwmod);
2528 else if (postsetup_state == _HWMOD_STATE_DISABLED)
2529 _shutdown(oh->parent_hwmod);
2530 else if (postsetup_state != _HWMOD_STATE_ENABLED)
2531 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
2532 oh->parent_hwmod->name, postsetup_state);
2533 }
2535 return 0;
2536 }
2538 /**
2539 * _register - register a struct omap_hwmod
2540 * @oh: struct omap_hwmod *
2541 *
2542 * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod
2543 * already has been registered by the same name; -EINVAL if the
2544 * omap_hwmod is in the wrong state, if @oh is NULL, if the
2545 * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
2546 * name, or if the omap_hwmod's class is missing a name; or 0 upon
2547 * success.
2548 *
2549 * XXX The data should be copied into bootmem, so the original data
2550 * should be marked __initdata and freed after init. This would allow
2551 * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note
2552 * that the copy process would be relatively complex due to the large number
2553 * of substructures.
2554 */
2555 static int __init _register(struct omap_hwmod *oh)
2556 {
2557 if (!oh || !oh->name || !oh->class || !oh->class->name ||
2558 (oh->_state != _HWMOD_STATE_UNKNOWN))
2559 return -EINVAL;
2561 pr_debug("omap_hwmod: %s: registering\n", oh->name);
2563 if (_lookup(oh->name))
2564 return -EEXIST;
2566 list_add_tail(&oh->node, &omap_hwmod_list);
2568 INIT_LIST_HEAD(&oh->slave_ports);
2569 spin_lock_init(&oh->_lock);
2570 lockdep_set_class(&oh->_lock, &oh->hwmod_key);
2572 oh->_state = _HWMOD_STATE_REGISTERED;
2574 /*
2575 * XXX Rather than doing a strcmp(), this should test a flag
2576 * set in the hwmod data, inserted by the autogenerator code.
2577 */
2578 if (!strcmp(oh->name, MPU_INITIATOR_NAME))
2579 mpu_oh = oh;
2581 return 0;
2582 }
2584 /**
2585 * _add_link - add an interconnect between two IP blocks
2586 * @oi: pointer to a struct omap_hwmod_ocp_if record
2587 *
2588 * Add struct omap_hwmod_link records connecting the slave IP block
2589 * specified in @oi->slave to @oi. This code is assumed to run before
2590 * preemption or SMP has been enabled, thus avoiding the need for
2591 * locking in this code. Changes to this assumption will require
2592 * additional locking. Returns 0.
2593 */
2594 static int __init _add_link(struct omap_hwmod_ocp_if *oi)
2595 {
2596 pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
2597 oi->slave->name);
2599 list_add(&oi->node, &oi->slave->slave_ports);
2600 oi->slave->slaves_cnt++;
2602 return 0;
2603 }
2605 /**
2606 * _register_link - register a struct omap_hwmod_ocp_if
2607 * @oi: struct omap_hwmod_ocp_if *
2608 *
2609 * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it
2610 * has already been registered; -EINVAL if @oi is NULL or if the
2611 * record pointed to by @oi is missing required fields; or 0 upon
2612 * success.
2613 *
2614 * XXX The data should be copied into bootmem, so the original data
2615 * should be marked __initdata and freed after init. This would allow
2616 * unneeded omap_hwmods to be freed on multi-OMAP configurations.
2617 */
2618 static int __init _register_link(struct omap_hwmod_ocp_if *oi)
2619 {
2620 if (!oi || !oi->master || !oi->slave || !oi->user)
2621 return -EINVAL;
2623 if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
2624 return -EEXIST;
2626 pr_debug("omap_hwmod: registering link from %s to %s\n",
2627 oi->master->name, oi->slave->name);
2629 /*
2630 * Register the connected hwmods, if they haven't been
2631 * registered already
2632 */
2633 if (oi->master->_state != _HWMOD_STATE_REGISTERED)
2634 _register(oi->master);
2636 if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
2637 _register(oi->slave);
2639 _add_link(oi);
2641 oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
2643 return 0;
2644 }
2646 /* Static functions intended only for use in soc_ops field function pointers */
2648 /**
2649 * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle
2650 * @oh: struct omap_hwmod *
2651 *
2652 * Wait for a module @oh to leave slave idle. Returns 0 if the module
2653 * does not have an IDLEST bit or if the module successfully leaves
2654 * slave idle; otherwise, pass along the return value of the
2655 * appropriate *_cm*_wait_module_ready() function.
2656 */
2657 static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh)
2658 {
2659 if (!oh)
2660 return -EINVAL;
2662 if (oh->flags & HWMOD_NO_IDLEST)
2663 return 0;
2665 if (!_find_mpu_rt_port(oh))
2666 return 0;
2668 /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
2670 return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs,
2671 oh->prcm.omap2.idlest_reg_id,
2672 oh->prcm.omap2.idlest_idle_bit);
2673 }
2675 /**
2676 * _omap4_wait_target_ready - wait for a module to leave slave idle
2677 * @oh: struct omap_hwmod *
2678 *
2679 * Wait for a module @oh to leave slave idle. Returns 0 if the module
2680 * does not have an IDLEST bit or if the module successfully leaves
2681 * slave idle; otherwise, pass along the return value of the
2682 * appropriate *_cm*_wait_module_ready() function.
2683 */
2684 static int _omap4_wait_target_ready(struct omap_hwmod *oh)
2685 {
2686 if (!oh)
2687 return -EINVAL;
2689 if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
2690 return 0;
2692 if (!_find_mpu_rt_port(oh))
2693 return 0;
2695 if (_omap4_clkctrl_managed_by_clkfwk(oh))
2696 return 0;
2698 if (!_omap4_has_clkctrl_clock(oh))
2699 return 0;
2701 /* XXX check module SIDLEMODE, hardreset status */
2703 return omap_cm_wait_module_ready(oh->clkdm->prcm_partition,
2704 oh->clkdm->cm_inst,
2705 oh->prcm.omap4.clkctrl_offs, 0);
2706 }
2708 /**
2709 * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2710 * @oh: struct omap_hwmod * to assert hardreset
2711 * @ohri: hardreset line data
2712 *
2713 * Call omap2_prm_assert_hardreset() with parameters extracted from
2714 * the hwmod @oh and the hardreset line data @ohri. Only intended for
2715 * use as an soc_ops function pointer. Passes along the return value
2716 * from omap2_prm_assert_hardreset(). XXX This function is scheduled
2717 * for removal when the PRM code is moved into drivers/.
2718 */
2719 static int _omap2_assert_hardreset(struct omap_hwmod *oh,
2720 struct omap_hwmod_rst_info *ohri)
2721 {
2722 return omap_prm_assert_hardreset(ohri->rst_shift, 0,
2723 oh->prcm.omap2.module_offs, 0);
2724 }
2726 /**
2727 * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2728 * @oh: struct omap_hwmod * to deassert hardreset
2729 * @ohri: hardreset line data
2730 *
2731 * Call omap2_prm_deassert_hardreset() with parameters extracted from
2732 * the hwmod @oh and the hardreset line data @ohri. Only intended for
2733 * use as an soc_ops function pointer. Passes along the return value
2734 * from omap2_prm_deassert_hardreset(). XXX This function is
2735 * scheduled for removal when the PRM code is moved into drivers/.
2736 */
2737 static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
2738 struct omap_hwmod_rst_info *ohri)
2739 {
2740 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
2741 oh->prcm.omap2.module_offs, 0, 0);
2742 }
2744 /**
2745 * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args
2746 * @oh: struct omap_hwmod * to test hardreset
2747 * @ohri: hardreset line data
2748 *
2749 * Call omap2_prm_is_hardreset_asserted() with parameters extracted
2750 * from the hwmod @oh and the hardreset line data @ohri. Only
2751 * intended for use as an soc_ops function pointer. Passes along the
2752 * return value from omap2_prm_is_hardreset_asserted(). XXX This
2753 * function is scheduled for removal when the PRM code is moved into
2754 * drivers/.
2755 */
2756 static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
2757 struct omap_hwmod_rst_info *ohri)
2758 {
2759 return omap_prm_is_hardreset_asserted(ohri->st_shift, 0,
2760 oh->prcm.omap2.module_offs, 0);
2761 }
2763 /**
2764 * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2765 * @oh: struct omap_hwmod * to assert hardreset
2766 * @ohri: hardreset line data
2767 *
2768 * Call omap4_prminst_assert_hardreset() with parameters extracted
2769 * from the hwmod @oh and the hardreset line data @ohri. Only
2770 * intended for use as an soc_ops function pointer. Passes along the
2771 * return value from omap4_prminst_assert_hardreset(). XXX This
2772 * function is scheduled for removal when the PRM code is moved into
2773 * drivers/.
2774 */
2775 static int _omap4_assert_hardreset(struct omap_hwmod *oh,
2776 struct omap_hwmod_rst_info *ohri)
2777 {
2778 if (!oh->clkdm)
2779 return -EINVAL;
2781 return omap_prm_assert_hardreset(ohri->rst_shift,
2782 oh->clkdm->pwrdm.ptr->prcm_partition,
2783 oh->clkdm->pwrdm.ptr->prcm_offs,
2784 oh->prcm.omap4.rstctrl_offs);
2785 }
2787 /**
2788 * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2789 * @oh: struct omap_hwmod * to deassert hardreset
2790 * @ohri: hardreset line data
2791 *
2792 * Call omap4_prminst_deassert_hardreset() with parameters extracted
2793 * from the hwmod @oh and the hardreset line data @ohri. Only
2794 * intended for use as an soc_ops function pointer. Passes along the
2795 * return value from omap4_prminst_deassert_hardreset(). XXX This
2796 * function is scheduled for removal when the PRM code is moved into
2797 * drivers/.
2798 */
2799 static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
2800 struct omap_hwmod_rst_info *ohri)
2801 {
2802 if (!oh->clkdm)
2803 return -EINVAL;
2805 if (ohri->st_shift)
2806 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
2807 oh->name, ohri->name);
2808 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
2809 oh->clkdm->pwrdm.ptr->prcm_partition,
2810 oh->clkdm->pwrdm.ptr->prcm_offs,
2811 oh->prcm.omap4.rstctrl_offs,
2812 oh->prcm.omap4.rstctrl_offs +
2813 OMAP4_RST_CTRL_ST_OFFSET);
2814 }
2816 /**
2817 * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args
2818 * @oh: struct omap_hwmod * to test hardreset
2819 * @ohri: hardreset line data
2820 *
2821 * Call omap4_prminst_is_hardreset_asserted() with parameters
2822 * extracted from the hwmod @oh and the hardreset line data @ohri.
2823 * Only intended for use as an soc_ops function pointer. Passes along
2824 * the return value from omap4_prminst_is_hardreset_asserted(). XXX
2825 * This function is scheduled for removal when the PRM code is moved
2826 * into drivers/.
2827 */
2828 static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
2829 struct omap_hwmod_rst_info *ohri)
2830 {
2831 if (!oh->clkdm)
2832 return -EINVAL;
2834 return omap_prm_is_hardreset_asserted(ohri->rst_shift,
2835 oh->clkdm->pwrdm.ptr->
2836 prcm_partition,
2837 oh->clkdm->pwrdm.ptr->prcm_offs,
2838 oh->prcm.omap4.rstctrl_offs);
2839 }
2841 /**
2842 * _omap4_disable_direct_prcm - disable direct PRCM control for hwmod
2843 * @oh: struct omap_hwmod * to disable control for
2844 *
2845 * Disables direct PRCM clkctrl done by hwmod core. Instead, the hwmod
2846 * will be using its main_clk to enable/disable the module. Returns
2847 * 0 if successful.
2848 */
2849 static int _omap4_disable_direct_prcm(struct omap_hwmod *oh)
2850 {
2851 if (!oh)
2852 return -EINVAL;
2854 oh->prcm.omap4.flags |= HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK;
2856 return 0;
2857 }
2859 /**
2860 * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
2861 * @oh: struct omap_hwmod * to deassert hardreset
2862 * @ohri: hardreset line data
2863 *
2864 * Call am33xx_prminst_deassert_hardreset() with parameters extracted
2865 * from the hwmod @oh and the hardreset line data @ohri. Only
2866 * intended for use as an soc_ops function pointer. Passes along the
2867 * return value from am33xx_prminst_deassert_hardreset(). XXX This
2868 * function is scheduled for removal when the PRM code is moved into
2869 * drivers/.
2870 */
2871 static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
2872 struct omap_hwmod_rst_info *ohri)
2873 {
2874 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift,
2875 oh->clkdm->pwrdm.ptr->prcm_partition,
2876 oh->clkdm->pwrdm.ptr->prcm_offs,
2877 oh->prcm.omap4.rstctrl_offs,
2878 oh->prcm.omap4.rstst_offs);
2879 }
2881 /* Public functions */
2883 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
2884 {
2885 if (oh->flags & HWMOD_16BIT_REG)
2886 return readw_relaxed(oh->_mpu_rt_va + reg_offs);
2887 else
2888 return readl_relaxed(oh->_mpu_rt_va + reg_offs);
2889 }
2891 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
2892 {
2893 if (oh->flags & HWMOD_16BIT_REG)
2894 writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
2895 else
2896 writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
2897 }
2899 /**
2900 * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
2901 * @oh: struct omap_hwmod *
2902 *
2903 * This is a public function exposed to drivers. Some drivers may need to do
2904 * some settings before and after resetting the device. Those drivers after
2905 * doing the necessary settings could use this function to start a reset by
2906 * setting the SYSCONFIG.SOFTRESET bit.
2907 */
2908 int omap_hwmod_softreset(struct omap_hwmod *oh)
2909 {
2910 u32 v;
2911 int ret;
2913 if (!oh || !(oh->_sysc_cache))
2914 return -EINVAL;
2916 v = oh->_sysc_cache;
2917 ret = _set_softreset(oh, &v);
2918 if (ret)
2919 goto error;
2920 _write_sysconfig(v, oh);
2922 ret = _clear_softreset(oh, &v);
2923 if (ret)
2924 goto error;
2925 _write_sysconfig(v, oh);
2927 error:
2928 return ret;
2929 }
2931 /**
2932 * omap_hwmod_lookup - look up a registered omap_hwmod by name
2933 * @name: name of the omap_hwmod to look up
2934 *
2935 * Given a @name of an omap_hwmod, return a pointer to the registered
2936 * struct omap_hwmod *, or NULL upon error.
2937 */
2938 struct omap_hwmod *omap_hwmod_lookup(const char *name)
2939 {
2940 struct omap_hwmod *oh;
2942 if (!name)
2943 return NULL;
2945 oh = _lookup(name);
2947 return oh;
2948 }
2950 /**
2951 * omap_hwmod_for_each - call function for each registered omap_hwmod
2952 * @fn: pointer to a callback function
2953 * @data: void * data to pass to callback function
2954 *
2955 * Call @fn for each registered omap_hwmod, passing @data to each
2956 * function. @fn must return 0 for success or any other value for
2957 * failure. If @fn returns non-zero, the iteration across omap_hwmods
2958 * will stop and the non-zero return value will be passed to the
2959 * caller of omap_hwmod_for_each(). @fn is called with
2960 * omap_hwmod_for_each() held.
2961 */
2962 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
2963 void *data)
2964 {
2965 struct omap_hwmod *temp_oh;
2966 int ret = 0;
2968 if (!fn)
2969 return -EINVAL;
2971 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
2972 ret = (*fn)(temp_oh, data);
2973 if (ret)
2974 break;
2975 }
2977 return ret;
2978 }
2980 /**
2981 * omap_hwmod_register_links - register an array of hwmod links
2982 * @ois: pointer to an array of omap_hwmod_ocp_if to register
2983 *
2984 * Intended to be called early in boot before the clock framework is
2985 * initialized. If @ois is not null, will register all omap_hwmods
2986 * listed in @ois that are valid for this chip. Returns -EINVAL if
2987 * omap_hwmod_init() hasn't been called before calling this function,
2988 * -ENOMEM if the link memory area can't be allocated, or 0 upon
2989 * success.
2990 */
2991 int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
2992 {
2993 int r, i;
2995 if (!inited)
2996 return -EINVAL;
2998 if (!ois)
2999 return 0;
3001 if (ois[0] == NULL) /* Empty list */
3002 return 0;
3004 i = 0;
3005 do {
3006 r = _register_link(ois[i]);
3007 WARN(r && r != -EEXIST,
3008 "omap_hwmod: _register_link(%s -> %s) returned %d\n",
3009 ois[i]->master->name, ois[i]->slave->name, r);
3010 } while (ois[++i]);
3012 return 0;
3013 }
3015 /**
3016 * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
3017 * @oh: pointer to the hwmod currently being set up (usually not the MPU)
3018 *
3019 * If the hwmod data corresponding to the MPU subsystem IP block
3020 * hasn't been initialized and set up yet, do so now. This must be
3021 * done first since sleep dependencies may be added from other hwmods
3022 * to the MPU. Intended to be called only by omap_hwmod_setup*(). No
3023 * return value.
3024 */
3025 static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
3026 {
3027 if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
3028 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
3029 __func__, MPU_INITIATOR_NAME);
3030 else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
3031 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
3032 }
3034 /**
3035 * omap_hwmod_setup_one - set up a single hwmod
3036 * @oh_name: const char * name of the already-registered hwmod to set up
3037 *
3038 * Initialize and set up a single hwmod. Intended to be used for a
3039 * small number of early devices, such as the timer IP blocks used for
3040 * the scheduler clock. Must be called after omap2_clk_init().
3041 * Resolves the struct clk names to struct clk pointers for each
3042 * registered omap_hwmod. Also calls _setup() on each hwmod. Returns
3043 * -EINVAL upon error or 0 upon success.
3044 */
3045 int __init omap_hwmod_setup_one(const char *oh_name)
3046 {
3047 struct omap_hwmod *oh;
3049 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
3051 oh = _lookup(oh_name);
3052 if (!oh) {
3053 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
3054 return -EINVAL;
3055 }
3057 _ensure_mpu_hwmod_is_setup(oh);
3059 _init(oh, NULL);
3060 _setup(oh, NULL);
3062 return 0;
3063 }
3065 static void omap_hwmod_check_one(struct device *dev,
3066 const char *name, s8 v1, u8 v2)
3067 {
3068 if (v1 < 0)
3069 return;
3071 if (v1 != v2)
3072 dev_warn(dev, "%s %d != %d\n", name, v1, v2);
3073 }
3075 /**
3076 * omap_hwmod_check_sysc - check sysc against platform sysc
3077 * @dev: struct device
3078 * @data: module data
3079 * @sysc_fields: new sysc configuration
3080 */
3081 static int omap_hwmod_check_sysc(struct device *dev,
3082 const struct ti_sysc_module_data *data,
3083 struct sysc_regbits *sysc_fields)
3084 {
3085 const struct sysc_regbits *regbits = data->cap->regbits;
3087 omap_hwmod_check_one(dev, "dmadisable_shift",
3088 regbits->dmadisable_shift,
3089 sysc_fields->dmadisable_shift);
3090 omap_hwmod_check_one(dev, "midle_shift",
3091 regbits->midle_shift,
3092 sysc_fields->midle_shift);
3093 omap_hwmod_check_one(dev, "sidle_shift",
3094 regbits->sidle_shift,
3095 sysc_fields->sidle_shift);
3096 omap_hwmod_check_one(dev, "clkact_shift",
3097 regbits->clkact_shift,
3098 sysc_fields->clkact_shift);
3099 omap_hwmod_check_one(dev, "enwkup_shift",
3100 regbits->enwkup_shift,
3101 sysc_fields->enwkup_shift);
3102 omap_hwmod_check_one(dev, "srst_shift",
3103 regbits->srst_shift,
3104 sysc_fields->srst_shift);
3105 omap_hwmod_check_one(dev, "autoidle_shift",
3106 regbits->autoidle_shift,
3107 sysc_fields->autoidle_shift);
3109 return 0;
3110 }
3112 /**
3113 * omap_hwmod_init_regbits - init sysconfig specific register bits
3114 * @dev: struct device
3115 * @data: module data
3116 * @sysc_fields: new sysc configuration
3117 */
3118 static int omap_hwmod_init_regbits(struct device *dev,
3119 const struct ti_sysc_module_data *data,
3120 struct sysc_regbits **sysc_fields)
3121 {
3122 *sysc_fields = NULL;
3124 switch (data->cap->type) {
3125 case TI_SYSC_OMAP2:
3126 case TI_SYSC_OMAP2_TIMER:
3127 *sysc_fields = &omap_hwmod_sysc_type1;
3128 break;
3129 case TI_SYSC_OMAP3_SHAM:
3130 *sysc_fields = &omap3_sham_sysc_fields;
3131 break;
3132 case TI_SYSC_OMAP3_AES:
3133 *sysc_fields = &omap3xxx_aes_sysc_fields;
3134 break;
3135 case TI_SYSC_OMAP4:
3136 case TI_SYSC_OMAP4_TIMER:
3137 *sysc_fields = &omap_hwmod_sysc_type2;
3138 break;
3139 case TI_SYSC_OMAP4_SIMPLE:
3140 *sysc_fields = &omap_hwmod_sysc_type3;
3141 break;
3142 case TI_SYSC_OMAP34XX_SR:
3143 *sysc_fields = &omap34xx_sr_sysc_fields;
3144 break;
3145 case TI_SYSC_OMAP36XX_SR:
3146 *sysc_fields = &omap36xx_sr_sysc_fields;
3147 break;
3148 case TI_SYSC_OMAP4_SR:
3149 *sysc_fields = &omap36xx_sr_sysc_fields;
3150 break;
3151 case TI_SYSC_OMAP4_MCASP:
3152 *sysc_fields = &omap_hwmod_sysc_type_mcasp;
3153 break;
3154 case TI_SYSC_OMAP4_USB_HOST_FS:
3155 *sysc_fields = &omap_hwmod_sysc_type_usb_host_fs;
3156 break;
3157 default:
3158 return -EINVAL;
3159 }
3161 return omap_hwmod_check_sysc(dev, data, *sysc_fields);
3162 }
3164 /**
3165 * omap_hwmod_init_reg_offs - initialize sysconfig register offsets
3166 * @dev: struct device
3167 * @data: module data
3168 * @rev_offs: revision register offset
3169 * @sysc_offs: sysc register offset
3170 * @syss_offs: syss register offset
3171 */
3172 int omap_hwmod_init_reg_offs(struct device *dev,
3173 const struct ti_sysc_module_data *data,
3174 s32 *rev_offs, s32 *sysc_offs, s32 *syss_offs)
3175 {
3176 *rev_offs = -ENODEV;
3177 *sysc_offs = 0;
3178 *syss_offs = 0;
3180 if (data->offsets[SYSC_REVISION] >= 0)
3181 *rev_offs = data->offsets[SYSC_REVISION];
3183 if (data->offsets[SYSC_SYSCONFIG] >= 0)
3184 *sysc_offs = data->offsets[SYSC_SYSCONFIG];
3186 if (data->offsets[SYSC_SYSSTATUS] >= 0)
3187 *syss_offs = data->offsets[SYSC_SYSSTATUS];
3189 return 0;
3190 }
3192 /**
3193 * omap_hwmod_init_sysc_flags - initialize sysconfig features
3194 * @dev: struct device
3195 * @data: module data
3196 * @sysc_flags: module configuration
3197 */
3198 int omap_hwmod_init_sysc_flags(struct device *dev,
3199 const struct ti_sysc_module_data *data,
3200 u32 *sysc_flags)
3201 {
3202 *sysc_flags = 0;
3204 switch (data->cap->type) {
3205 case TI_SYSC_OMAP2:
3206 case TI_SYSC_OMAP2_TIMER:
3207 /* See SYSC_OMAP2_* in include/dt-bindings/bus/ti-sysc.h */
3208 if (data->cfg->sysc_val & SYSC_OMAP2_CLOCKACTIVITY)
3209 *sysc_flags |= SYSC_HAS_CLOCKACTIVITY;
3210 if (data->cfg->sysc_val & SYSC_OMAP2_EMUFREE)
3211 *sysc_flags |= SYSC_HAS_EMUFREE;
3212 if (data->cfg->sysc_val & SYSC_OMAP2_ENAWAKEUP)
3213 *sysc_flags |= SYSC_HAS_ENAWAKEUP;
3214 if (data->cfg->sysc_val & SYSC_OMAP2_SOFTRESET)
3215 *sysc_flags |= SYSC_HAS_SOFTRESET;
3216 if (data->cfg->sysc_val & SYSC_OMAP2_AUTOIDLE)
3217 *sysc_flags |= SYSC_HAS_AUTOIDLE;
3218 break;
3219 case TI_SYSC_OMAP4:
3220 case TI_SYSC_OMAP4_TIMER:
3221 /* See SYSC_OMAP4_* in include/dt-bindings/bus/ti-sysc.h */
3222 if (data->cfg->sysc_val & SYSC_OMAP4_DMADISABLE)
3223 *sysc_flags |= SYSC_HAS_DMADISABLE;
3224 if (data->cfg->sysc_val & SYSC_OMAP4_FREEEMU)
3225 *sysc_flags |= SYSC_HAS_EMUFREE;
3226 if (data->cfg->sysc_val & SYSC_OMAP4_SOFTRESET)
3227 *sysc_flags |= SYSC_HAS_SOFTRESET;
3228 break;
3229 case TI_SYSC_OMAP34XX_SR:
3230 case TI_SYSC_OMAP36XX_SR:
3231 /* See SYSC_OMAP3_SR_* in include/dt-bindings/bus/ti-sysc.h */
3232 if (data->cfg->sysc_val & SYSC_OMAP3_SR_ENAWAKEUP)
3233 *sysc_flags |= SYSC_HAS_ENAWAKEUP;
3234 break;
3235 default:
3236 if (data->cap->regbits->emufree_shift >= 0)
3237 *sysc_flags |= SYSC_HAS_EMUFREE;
3238 if (data->cap->regbits->enwkup_shift >= 0)
3239 *sysc_flags |= SYSC_HAS_ENAWAKEUP;
3240 if (data->cap->regbits->srst_shift >= 0)
3241 *sysc_flags |= SYSC_HAS_SOFTRESET;
3242 if (data->cap->regbits->autoidle_shift >= 0)
3243 *sysc_flags |= SYSC_HAS_AUTOIDLE;
3244 break;
3245 }
3247 if (data->cap->regbits->midle_shift >= 0 &&
3248 data->cfg->midlemodes)
3249 *sysc_flags |= SYSC_HAS_MIDLEMODE;
3251 if (data->cap->regbits->sidle_shift >= 0 &&
3252 data->cfg->sidlemodes)
3253 *sysc_flags |= SYSC_HAS_SIDLEMODE;
3255 if (data->cfg->quirks & SYSC_QUIRK_UNCACHED)
3256 *sysc_flags |= SYSC_NO_CACHE;
3257 if (data->cfg->quirks & SYSC_QUIRK_RESET_STATUS)
3258 *sysc_flags |= SYSC_HAS_RESET_STATUS;
3260 if (data->cfg->syss_mask & 1)
3261 *sysc_flags |= SYSS_HAS_RESET_STATUS;
3263 return 0;
3264 }
3266 /**
3267 * omap_hwmod_init_idlemodes - initialize module idle modes
3268 * @dev: struct device
3269 * @data: module data
3270 * @idlemodes: module supported idle modes
3271 */
3272 int omap_hwmod_init_idlemodes(struct device *dev,
3273 const struct ti_sysc_module_data *data,
3274 u32 *idlemodes)
3275 {
3276 *idlemodes = 0;
3278 if (data->cfg->midlemodes & BIT(SYSC_IDLE_FORCE))
3279 *idlemodes |= MSTANDBY_FORCE;
3280 if (data->cfg->midlemodes & BIT(SYSC_IDLE_NO))
3281 *idlemodes |= MSTANDBY_NO;
3282 if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART))
3283 *idlemodes |= MSTANDBY_SMART;
3284 if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART_WKUP))
3285 *idlemodes |= MSTANDBY_SMART_WKUP;
3287 if (data->cfg->sidlemodes & BIT(SYSC_IDLE_FORCE))
3288 *idlemodes |= SIDLE_FORCE;
3289 if (data->cfg->sidlemodes & BIT(SYSC_IDLE_NO))
3290 *idlemodes |= SIDLE_NO;
3291 if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART))
3292 *idlemodes |= SIDLE_SMART;
3293 if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART_WKUP))
3294 *idlemodes |= SIDLE_SMART_WKUP;
3296 return 0;
3297 }
3299 /**
3300 * omap_hwmod_check_module - check new module against platform data
3301 * @dev: struct device
3302 * @oh: module
3303 * @data: new module data
3304 * @sysc_fields: sysc register bits
3305 * @rev_offs: revision register offset
3306 * @sysc_offs: sysconfig register offset
3307 * @syss_offs: sysstatus register offset
3308 * @sysc_flags: sysc specific flags
3309 * @idlemodes: sysc supported idlemodes
3310 */
3311 static int omap_hwmod_check_module(struct device *dev,
3312 struct omap_hwmod *oh,
3313 const struct ti_sysc_module_data *data,
3314 struct sysc_regbits *sysc_fields,
3315 s32 rev_offs, s32 sysc_offs,
3316 s32 syss_offs, u32 sysc_flags,
3317 u32 idlemodes)
3318 {
3319 if (!oh->class->sysc)
3320 return -ENODEV;
3322 if (sysc_fields != oh->class->sysc->sysc_fields)
3323 dev_warn(dev, "sysc_fields %p != %p\n", sysc_fields,
3324 oh->class->sysc->sysc_fields);
3326 if (rev_offs != oh->class->sysc->rev_offs)
3327 dev_warn(dev, "rev_offs %08x != %08x\n", rev_offs,
3328 oh->class->sysc->rev_offs);
3329 if (sysc_offs != oh->class->sysc->sysc_offs)
3330 dev_warn(dev, "sysc_offs %08x != %08x\n", sysc_offs,
3331 oh->class->sysc->sysc_offs);
3332 if (syss_offs != oh->class->sysc->syss_offs)
3333 dev_warn(dev, "syss_offs %08x != %08x\n", syss_offs,
3334 oh->class->sysc->syss_offs);
3336 if (sysc_flags != oh->class->sysc->sysc_flags)
3337 dev_warn(dev, "sysc_flags %08x != %08x\n", sysc_flags,
3338 oh->class->sysc->sysc_flags);
3340 if (idlemodes != oh->class->sysc->idlemodes)
3341 dev_warn(dev, "idlemodes %08x != %08x\n", idlemodes,
3342 oh->class->sysc->idlemodes);
3344 if (data->cfg->srst_udelay != oh->class->sysc->srst_udelay)
3345 dev_warn(dev, "srst_udelay %i != %i\n",
3346 data->cfg->srst_udelay,
3347 oh->class->sysc->srst_udelay);
3349 return 0;
3350 }
3352 /**
3353 * omap_hwmod_allocate_module - allocate new module
3354 * @dev: struct device
3355 * @oh: module
3356 * @sysc_fields: sysc register bits
3357 * @rev_offs: revision register offset
3358 * @sysc_offs: sysconfig register offset
3359 * @syss_offs: sysstatus register offset
3360 * @sysc_flags: sysc specific flags
3361 * @idlemodes: sysc supported idlemodes
3362 *
3363 * Note that the allocations here cannot use devm as ti-sysc can rebind.
3364 */
3365 int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
3366 const struct ti_sysc_module_data *data,
3367 struct sysc_regbits *sysc_fields,
3368 s32 rev_offs, s32 sysc_offs, s32 syss_offs,
3369 u32 sysc_flags, u32 idlemodes)
3370 {
3371 struct omap_hwmod_class_sysconfig *sysc;
3372 struct omap_hwmod_class *class;
3373 void __iomem *regs = NULL;
3374 unsigned long flags;
3376 sysc = kzalloc(sizeof(*sysc), GFP_KERNEL);
3377 if (!sysc)
3378 return -ENOMEM;
3380 sysc->sysc_fields = sysc_fields;
3381 sysc->rev_offs = rev_offs;
3382 sysc->sysc_offs = sysc_offs;
3383 sysc->syss_offs = syss_offs;
3384 sysc->sysc_flags = sysc_flags;
3385 sysc->idlemodes = idlemodes;
3386 sysc->srst_udelay = data->cfg->srst_udelay;
3388 if (!oh->_mpu_rt_va) {
3389 regs = ioremap(data->module_pa,
3390 data->module_size);
3391 if (!regs)
3392 return -ENOMEM;
3393 }
3395 /*
3396 * We need new oh->class as the other devices in the same class
3397 * may not yet have ioremapped their registers.
3398 */
3399 class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
3400 if (!class)
3401 return -ENOMEM;
3403 class->sysc = sysc;
3405 spin_lock_irqsave(&oh->_lock, flags);
3406 if (regs)
3407 oh->_mpu_rt_va = regs;
3408 oh->class = class;
3409 oh->_state = _HWMOD_STATE_INITIALIZED;
3410 _setup(oh, NULL);
3411 spin_unlock_irqrestore(&oh->_lock, flags);
3413 return 0;
3414 }
3416 /**
3417 * omap_hwmod_init_module - initialize new module
3418 * @dev: struct device
3419 * @data: module data
3420 * @cookie: cookie for the caller to use for later calls
3421 */
3422 int omap_hwmod_init_module(struct device *dev,
3423 const struct ti_sysc_module_data *data,
3424 struct ti_sysc_cookie *cookie)
3425 {
3426 struct omap_hwmod *oh;
3427 struct sysc_regbits *sysc_fields;
3428 s32 rev_offs, sysc_offs, syss_offs;
3429 u32 sysc_flags, idlemodes;
3430 int error;
3432 if (!dev || !data)
3433 return -EINVAL;
3435 oh = _lookup(data->name);
3436 if (!oh)
3437 return -ENODEV;
3439 cookie->data = oh;
3441 error = omap_hwmod_init_regbits(dev, data, &sysc_fields);
3442 if (error)
3443 return error;
3445 error = omap_hwmod_init_reg_offs(dev, data, &rev_offs,
3446 &sysc_offs, &syss_offs);
3447 if (error)
3448 return error;
3450 error = omap_hwmod_init_sysc_flags(dev, data, &sysc_flags);
3451 if (error)
3452 return error;
3454 error = omap_hwmod_init_idlemodes(dev, data, &idlemodes);
3455 if (error)
3456 return error;
3458 if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE_ON_INIT)
3459 oh->flags |= HWMOD_INIT_NO_IDLE;
3460 if (data->cfg->quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
3461 oh->flags |= HWMOD_INIT_NO_RESET;
3463 error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
3464 rev_offs, sysc_offs, syss_offs,
3465 sysc_flags, idlemodes);
3466 if (!error)
3467 return error;
3469 return omap_hwmod_allocate_module(dev, oh, data, sysc_fields,
3470 rev_offs, sysc_offs, syss_offs,
3471 sysc_flags, idlemodes);
3472 }
3474 /**
3475 * omap_hwmod_setup_earlycon_flags - set up flags for early console
3476 *
3477 * Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as
3478 * early concole so that hwmod core doesn't reset and keep it in idle
3479 * that specific uart.
3480 */
3481 #ifdef CONFIG_SERIAL_EARLYCON
3482 static void __init omap_hwmod_setup_earlycon_flags(void)
3483 {
3484 struct device_node *np;
3485 struct omap_hwmod *oh;
3486 const char *uart;
3488 np = of_find_node_by_path("/chosen");
3489 if (np) {
3490 uart = of_get_property(np, "stdout-path", NULL);
3491 if (uart) {
3492 np = of_find_node_by_path(uart);
3493 if (np) {
3494 uart = of_get_property(np, "ti,hwmods", NULL);
3495 oh = omap_hwmod_lookup(uart);
3496 if (!oh) {
3497 uart = of_get_property(np->parent,
3498 "ti,hwmods",
3499 NULL);
3500 oh = omap_hwmod_lookup(uart);
3501 }
3502 if (oh)
3503 oh->flags |= DEBUG_OMAPUART_FLAGS;
3504 }
3505 }
3506 }
3507 }
3508 #endif
3510 /**
3511 * omap_hwmod_setup_all - set up all registered IP blocks
3512 *
3513 * Initialize and set up all IP blocks registered with the hwmod code.
3514 * Must be called after omap2_clk_init(). Resolves the struct clk
3515 * names to struct clk pointers for each registered omap_hwmod. Also
3516 * calls _setup() on each hwmod. Returns 0 upon success.
3517 */
3518 static int __init omap_hwmod_setup_all(void)
3519 {
3520 _ensure_mpu_hwmod_is_setup(NULL);
3522 omap_hwmod_for_each(_init, NULL);
3523 #ifdef CONFIG_SERIAL_EARLYCON
3524 omap_hwmod_setup_earlycon_flags();
3525 #endif
3526 omap_hwmod_for_each(_setup, NULL);
3528 return 0;
3529 }
3530 omap_postcore_initcall(omap_hwmod_setup_all);
3532 /**
3533 * omap_hwmod_enable - enable an omap_hwmod
3534 * @oh: struct omap_hwmod *
3535 *
3536 * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable().
3537 * Returns -EINVAL on error or passes along the return value from _enable().
3538 */
3539 int omap_hwmod_enable(struct omap_hwmod *oh)
3540 {
3541 int r;
3542 unsigned long flags;
3544 if (!oh)
3545 return -EINVAL;
3547 spin_lock_irqsave(&oh->_lock, flags);
3548 r = _enable(oh);
3549 spin_unlock_irqrestore(&oh->_lock, flags);
3551 return r;
3552 }
3554 /**
3555 * omap_hwmod_idle - idle an omap_hwmod
3556 * @oh: struct omap_hwmod *
3557 *
3558 * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle().
3559 * Returns -EINVAL on error or passes along the return value from _idle().
3560 */
3561 int omap_hwmod_idle(struct omap_hwmod *oh)
3562 {
3563 int r;
3564 unsigned long flags;
3566 if (!oh)
3567 return -EINVAL;
3569 spin_lock_irqsave(&oh->_lock, flags);
3570 r = _idle(oh);
3571 spin_unlock_irqrestore(&oh->_lock, flags);
3573 return r;
3574 }
3576 /**
3577 * omap_hwmod_shutdown - shutdown an omap_hwmod
3578 * @oh: struct omap_hwmod *
3579 *
3580 * Shutdown an omap_hwmod @oh. Intended to be called by
3581 * omap_device_shutdown(). Returns -EINVAL on error or passes along
3582 * the return value from _shutdown().
3583 */
3584 int omap_hwmod_shutdown(struct omap_hwmod *oh)
3585 {
3586 int r;
3587 unsigned long flags;
3589 if (!oh)
3590 return -EINVAL;
3592 spin_lock_irqsave(&oh->_lock, flags);
3593 r = _shutdown(oh);
3594 spin_unlock_irqrestore(&oh->_lock, flags);
3596 return r;
3597 }
3599 /*
3600 * IP block data retrieval functions
3601 */
3603 /**
3604 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
3605 * @oh: struct omap_hwmod *
3606 *
3607 * Return the powerdomain pointer associated with the OMAP module
3608 * @oh's main clock. If @oh does not have a main clk, return the
3609 * powerdomain associated with the interface clock associated with the
3610 * module's MPU port. (XXX Perhaps this should use the SDMA port
3611 * instead?) Returns NULL on error, or a struct powerdomain * on
3612 * success.
3613 */
3614 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
3615 {
3616 struct clk *c;
3617 struct omap_hwmod_ocp_if *oi;
3618 struct clockdomain *clkdm;
3619 struct clk_hw_omap *clk;
3621 if (!oh)
3622 return NULL;
3624 if (oh->clkdm)
3625 return oh->clkdm->pwrdm.ptr;
3627 if (oh->_clk) {
3628 c = oh->_clk;
3629 } else {
3630 oi = _find_mpu_rt_port(oh);
3631 if (!oi)
3632 return NULL;
3633 c = oi->_clk;
3634 }
3636 clk = to_clk_hw_omap(__clk_get_hw(c));
3637 clkdm = clk->clkdm;
3638 if (!clkdm)
3639 return NULL;
3641 return clkdm->pwrdm.ptr;
3642 }
3644 /**
3645 * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
3646 * @oh: struct omap_hwmod *
3647 *
3648 * Returns the virtual address corresponding to the beginning of the
3649 * module's register target, in the address range that is intended to
3650 * be used by the MPU. Returns the virtual address upon success or NULL
3651 * upon error.
3652 */
3653 void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
3654 {
3655 if (!oh)
3656 return NULL;
3658 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
3659 return NULL;
3661 if (oh->_state == _HWMOD_STATE_UNKNOWN)
3662 return NULL;
3664 return oh->_mpu_rt_va;
3665 }
3667 /*
3668 * XXX what about functions for drivers to save/restore ocp_sysconfig
3669 * for context save/restore operations?
3670 */
3672 /**
3673 * omap_hwmod_enable_wakeup - allow device to wake up the system
3674 * @oh: struct omap_hwmod *
3675 *
3676 * Sets the module OCP socket ENAWAKEUP bit to allow the module to
3677 * send wakeups to the PRCM, and enable I/O ring wakeup events for
3678 * this IP block if it has dynamic mux entries. Eventually this
3679 * should set PRCM wakeup registers to cause the PRCM to receive
3680 * wakeup events from the module. Does not set any wakeup routing
3681 * registers beyond this point - if the module is to wake up any other
3682 * module or subsystem, that must be set separately. Called by
3683 * omap_device code. Returns -EINVAL on error or 0 upon success.
3684 */
3685 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
3686 {
3687 unsigned long flags;
3688 u32 v;
3690 spin_lock_irqsave(&oh->_lock, flags);
3692 if (oh->class->sysc &&
3693 (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
3694 v = oh->_sysc_cache;
3695 _enable_wakeup(oh, &v);
3696 _write_sysconfig(v, oh);
3697 }
3699 spin_unlock_irqrestore(&oh->_lock, flags);
3701 return 0;
3702 }
3704 /**
3705 * omap_hwmod_disable_wakeup - prevent device from waking the system
3706 * @oh: struct omap_hwmod *
3707 *
3708 * Clears the module OCP socket ENAWAKEUP bit to prevent the module
3709 * from sending wakeups to the PRCM, and disable I/O ring wakeup
3710 * events for this IP block if it has dynamic mux entries. Eventually
3711 * this should clear PRCM wakeup registers to cause the PRCM to ignore
3712 * wakeup events from the module. Does not set any wakeup routing
3713 * registers beyond this point - if the module is to wake up any other
3714 * module or subsystem, that must be set separately. Called by
3715 * omap_device code. Returns -EINVAL on error or 0 upon success.
3716 */
3717 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
3718 {
3719 unsigned long flags;
3720 u32 v;
3722 spin_lock_irqsave(&oh->_lock, flags);
3724 if (oh->class->sysc &&
3725 (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
3726 v = oh->_sysc_cache;
3727 _disable_wakeup(oh, &v);
3728 _write_sysconfig(v, oh);
3729 }
3731 spin_unlock_irqrestore(&oh->_lock, flags);
3733 return 0;
3734 }
3736 /**
3737 * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
3738 * contained in the hwmod module.
3739 * @oh: struct omap_hwmod *
3740 * @name: name of the reset line to lookup and assert
3741 *
3742 * Some IP like dsp, ipu or iva contain processor that require
3743 * an HW reset line to be assert / deassert in order to enable fully
3744 * the IP. Returns -EINVAL if @oh is null or if the operation is not
3745 * yet supported on this OMAP; otherwise, passes along the return value
3746 * from _assert_hardreset().
3747 */
3748 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
3749 {
3750 int ret;
3751 unsigned long flags;
3753 if (!oh)
3754 return -EINVAL;
3756 spin_lock_irqsave(&oh->_lock, flags);
3757 ret = _assert_hardreset(oh, name);
3758 spin_unlock_irqrestore(&oh->_lock, flags);
3760 return ret;
3761 }
3763 /**
3764 * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
3765 * contained in the hwmod module.
3766 * @oh: struct omap_hwmod *
3767 * @name: name of the reset line to look up and deassert
3768 *
3769 * Some IP like dsp, ipu or iva contain processor that require
3770 * an HW reset line to be assert / deassert in order to enable fully
3771 * the IP. Returns -EINVAL if @oh is null or if the operation is not
3772 * yet supported on this OMAP; otherwise, passes along the return value
3773 * from _deassert_hardreset().
3774 */
3775 int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
3776 {
3777 int ret;
3778 unsigned long flags;
3780 if (!oh)
3781 return -EINVAL;
3783 spin_lock_irqsave(&oh->_lock, flags);
3784 ret = _deassert_hardreset(oh, name);
3785 spin_unlock_irqrestore(&oh->_lock, flags);
3787 return ret;
3788 }
3790 /**
3791 * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
3792 * @classname: struct omap_hwmod_class name to search for
3793 * @fn: callback function pointer to call for each hwmod in class @classname
3794 * @user: arbitrary context data to pass to the callback function
3795 *
3796 * For each omap_hwmod of class @classname, call @fn.
3797 * If the callback function returns something other than
3798 * zero, the iterator is terminated, and the callback function's return
3799 * value is passed back to the caller. Returns 0 upon success, -EINVAL
3800 * if @classname or @fn are NULL, or passes back the error code from @fn.
3801 */
3802 int omap_hwmod_for_each_by_class(const char *classname,
3803 int (*fn)(struct omap_hwmod *oh,
3804 void *user),
3805 void *user)
3806 {
3807 struct omap_hwmod *temp_oh;
3808 int ret = 0;
3810 if (!classname || !fn)
3811 return -EINVAL;
3813 pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
3814 __func__, classname);
3816 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
3817 if (!strcmp(temp_oh->class->name, classname)) {
3818 pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
3819 __func__, temp_oh->name);
3820 ret = (*fn)(temp_oh, user);
3821 if (ret)
3822 break;
3823 }
3824 }
3826 if (ret)
3827 pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
3828 __func__, ret);
3830 return ret;
3831 }
3833 /**
3834 * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
3835 * @oh: struct omap_hwmod *
3836 * @state: state that _setup() should leave the hwmod in
3837 *
3838 * Sets the hwmod state that @oh will enter at the end of _setup()
3839 * (called by omap_hwmod_setup_*()). See also the documentation
3840 * for _setup_postsetup(), above. Returns 0 upon success or
3841 * -EINVAL if there is a problem with the arguments or if the hwmod is
3842 * in the wrong state.
3843 */
3844 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
3845 {
3846 int ret;
3847 unsigned long flags;
3849 if (!oh)
3850 return -EINVAL;
3852 if (state != _HWMOD_STATE_DISABLED &&
3853 state != _HWMOD_STATE_ENABLED &&
3854 state != _HWMOD_STATE_IDLE)
3855 return -EINVAL;
3857 spin_lock_irqsave(&oh->_lock, flags);
3859 if (oh->_state != _HWMOD_STATE_REGISTERED) {
3860 ret = -EINVAL;
3861 goto ohsps_unlock;
3862 }
3864 oh->_postsetup_state = state;
3865 ret = 0;
3867 ohsps_unlock:
3868 spin_unlock_irqrestore(&oh->_lock, flags);
3870 return ret;
3871 }
3873 /**
3874 * omap_hwmod_get_context_loss_count - get lost context count
3875 * @oh: struct omap_hwmod *
3876 *
3877 * Returns the context loss count of associated @oh
3878 * upon success, or zero if no context loss data is available.
3879 *
3880 * On OMAP4, this queries the per-hwmod context loss register,
3881 * assuming one exists. If not, or on OMAP2/3, this queries the
3882 * enclosing powerdomain context loss count.
3883 */
3884 int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
3885 {
3886 struct powerdomain *pwrdm;
3887 int ret = 0;
3889 if (soc_ops.get_context_lost)
3890 return soc_ops.get_context_lost(oh);
3892 pwrdm = omap_hwmod_get_pwrdm(oh);
3893 if (pwrdm)
3894 ret = pwrdm_get_context_loss_count(pwrdm);
3896 return ret;
3897 }
3899 /**
3900 * omap_hwmod_init - initialize the hwmod code
3901 *
3902 * Sets up some function pointers needed by the hwmod code to operate on the
3903 * currently-booted SoC. Intended to be called once during kernel init
3904 * before any hwmods are registered. No return value.
3905 */
3906 void __init omap_hwmod_init(void)
3907 {
3908 if (cpu_is_omap24xx()) {
3909 soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
3910 soc_ops.assert_hardreset = _omap2_assert_hardreset;
3911 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3912 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3913 } else if (cpu_is_omap34xx()) {
3914 soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
3915 soc_ops.assert_hardreset = _omap2_assert_hardreset;
3916 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3917 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3918 soc_ops.init_clkdm = _init_clkdm;
3919 } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
3920 soc_ops.enable_module = _omap4_enable_module;
3921 soc_ops.disable_module = _omap4_disable_module;
3922 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3923 soc_ops.assert_hardreset = _omap4_assert_hardreset;
3924 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
3925 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3926 soc_ops.init_clkdm = _init_clkdm;
3927 soc_ops.update_context_lost = _omap4_update_context_lost;
3928 soc_ops.get_context_lost = _omap4_get_context_lost;
3929 soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
3930 soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl;
3931 } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
3932 soc_is_am43xx()) {
3933 soc_ops.enable_module = _omap4_enable_module;
3934 soc_ops.disable_module = _omap4_disable_module;
3935 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3936 soc_ops.assert_hardreset = _omap4_assert_hardreset;
3937 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
3938 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3939 soc_ops.init_clkdm = _init_clkdm;
3940 soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
3941 soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl;
3942 } else {
3943 WARN(1, "omap_hwmod: unknown SoC type\n");
3944 }
3946 _init_clkctrl_providers();
3948 inited = true;
3949 }
3951 /**
3952 * omap_hwmod_get_main_clk - get pointer to main clock name
3953 * @oh: struct omap_hwmod *
3954 *
3955 * Returns the main clock name assocated with @oh upon success,
3956 * or NULL if @oh is NULL.
3957 */
3958 const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh)
3959 {
3960 if (!oh)
3961 return NULL;
3963 return oh->main_clk;
3964 }