1 /*
2 * omap_hwmod macros, structures
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2011-2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * Created in collaboration with (alphabetical order): Benoît Cousson,
9 * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
10 * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * These headers and macros are used to define OMAP on-chip module
17 * data and their integration with other OMAP modules and Linux.
18 * Copious documentation and references can also be found in the
19 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20 * writing).
21 *
22 * To do:
23 * - add interconnect error log structures
24 * - init_conn_id_bit (CONNID_BIT_VECTOR)
25 * - implement default hwmod SMS/SDRC flags?
26 * - move Linux-specific data ("non-ROM data") out
27 *
28 */
29 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
30 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
32 #include <linux/kernel.h>
33 #include <linux/init.h>
34 #include <linux/list.h>
35 #include <linux/ioport.h>
36 #include <linux/spinlock.h>
38 struct omap_device;
40 extern struct sysc_regbits omap_hwmod_sysc_type1;
41 extern struct sysc_regbits omap_hwmod_sysc_type2;
42 extern struct sysc_regbits omap_hwmod_sysc_type3;
43 extern struct sysc_regbits omap34xx_sr_sysc_fields;
44 extern struct sysc_regbits omap36xx_sr_sysc_fields;
45 extern struct sysc_regbits omap3_sham_sysc_fields;
46 extern struct sysc_regbits omap3xxx_aes_sysc_fields;
47 extern struct sysc_regbits omap_hwmod_sysc_type_mcasp;
48 extern struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs;
50 /*
51 * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
52 * with the original PRCM protocol defined for OMAP2420
53 */
54 #define SYSC_TYPE1_MIDLEMODE_SHIFT 12
55 #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
56 #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
57 #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
58 #define SYSC_TYPE1_SIDLEMODE_SHIFT 3
59 #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
60 #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
61 #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
62 #define SYSC_TYPE1_SOFTRESET_SHIFT 1
63 #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
64 #define SYSC_TYPE1_AUTOIDLE_SHIFT 0
65 #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
67 /*
68 * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
69 * with the new PRCM protocol defined for new OMAP4 IPs.
70 */
71 #define SYSC_TYPE2_SOFTRESET_SHIFT 0
72 #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT)
73 #define SYSC_TYPE2_SIDLEMODE_SHIFT 2
74 #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
75 #define SYSC_TYPE2_MIDLEMODE_SHIFT 4
76 #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
77 #define SYSC_TYPE2_DMADISABLE_SHIFT 16
78 #define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
80 /*
81 * OCP SYSCONFIG bit shifts/masks TYPE3.
82 * This is applicable for some IPs present in AM33XX
83 */
84 #define SYSC_TYPE3_SIDLEMODE_SHIFT 0
85 #define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
86 #define SYSC_TYPE3_MIDLEMODE_SHIFT 2
87 #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
89 /* OCP SYSSTATUS bit shifts/masks */
90 #define SYSS_RESETDONE_SHIFT 0
91 #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
93 /* Master standby/slave idle mode flags */
94 #define HWMOD_IDLEMODE_FORCE (1 << 0)
95 #define HWMOD_IDLEMODE_NO (1 << 1)
96 #define HWMOD_IDLEMODE_SMART (1 << 2)
97 #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
99 /* modulemode control type (SW or HW) */
100 #define MODULEMODE_HWCTRL 1
101 #define MODULEMODE_SWCTRL 2
103 #define DEBUG_OMAP2UART1_FLAGS 0
104 #define DEBUG_OMAP2UART2_FLAGS 0
105 #define DEBUG_OMAP2UART3_FLAGS 0
106 #define DEBUG_OMAP3UART3_FLAGS 0
107 #define DEBUG_OMAP3UART4_FLAGS 0
108 #define DEBUG_OMAP4UART3_FLAGS 0
109 #define DEBUG_OMAP4UART4_FLAGS 0
110 #define DEBUG_TI81XXUART1_FLAGS 0
111 #define DEBUG_TI81XXUART2_FLAGS 0
112 #define DEBUG_TI81XXUART3_FLAGS 0
113 #define DEBUG_AM33XXUART1_FLAGS 0
115 #define DEBUG_OMAPUART_FLAGS (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET)
117 #ifdef CONFIG_OMAP_GPMC_DEBUG
118 #define DEBUG_OMAP_GPMC_HWMOD_FLAGS HWMOD_INIT_NO_RESET
119 #else
120 #define DEBUG_OMAP_GPMC_HWMOD_FLAGS 0
121 #endif
123 #if defined(CONFIG_DEBUG_OMAP2UART1)
124 #undef DEBUG_OMAP2UART1_FLAGS
125 #define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS
126 #elif defined(CONFIG_DEBUG_OMAP2UART2)
127 #undef DEBUG_OMAP2UART2_FLAGS
128 #define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS
129 #elif defined(CONFIG_DEBUG_OMAP2UART3)
130 #undef DEBUG_OMAP2UART3_FLAGS
131 #define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS
132 #elif defined(CONFIG_DEBUG_OMAP3UART3)
133 #undef DEBUG_OMAP3UART3_FLAGS
134 #define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS
135 #elif defined(CONFIG_DEBUG_OMAP3UART4)
136 #undef DEBUG_OMAP3UART4_FLAGS
137 #define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS
138 #elif defined(CONFIG_DEBUG_OMAP4UART3)
139 #undef DEBUG_OMAP4UART3_FLAGS
140 #define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS
141 #elif defined(CONFIG_DEBUG_OMAP4UART4)
142 #undef DEBUG_OMAP4UART4_FLAGS
143 #define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS
144 #elif defined(CONFIG_DEBUG_TI81XXUART1)
145 #undef DEBUG_TI81XXUART1_FLAGS
146 #define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
147 #elif defined(CONFIG_DEBUG_TI81XXUART2)
148 #undef DEBUG_TI81XXUART2_FLAGS
149 #define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS
150 #elif defined(CONFIG_DEBUG_TI81XXUART3)
151 #undef DEBUG_TI81XXUART3_FLAGS
152 #define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS
153 #elif defined(CONFIG_DEBUG_AM33XXUART1)
154 #undef DEBUG_AM33XXUART1_FLAGS
155 #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
156 #endif
158 /**
159 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
160 * @name: name of the reset line (module local name)
161 * @rst_shift: Offset of the reset bit
162 * @st_shift: Offset of the reset status bit (OMAP2/3 only)
163 *
164 * @name should be something short, e.g., "cpu0" or "rst". It is defined
165 * locally to the hwmod.
166 */
167 struct omap_hwmod_rst_info {
168 const char *name;
169 u8 rst_shift;
170 u8 st_shift;
171 };
173 /**
174 * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
175 * @role: "sys", "32k", "tv", etc -- for use in clk_get()
176 * @clk: opt clock: OMAP clock name
177 * @_clk: pointer to the struct clk (filled in at runtime)
178 *
179 * The module's interface clock and main functional clock should not
180 * be added as optional clocks.
181 */
182 struct omap_hwmod_opt_clk {
183 const char *role;
184 const char *clk;
185 struct clk *_clk;
186 };
189 /* omap_hwmod_omap2_firewall.flags bits */
190 #define OMAP_FIREWALL_L3 (1 << 0)
191 #define OMAP_FIREWALL_L4 (1 << 1)
193 /**
194 * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
195 * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
196 * @l4_fw_region: L4 firewall region ID
197 * @l4_prot_group: L4 protection group ID
198 * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
199 */
200 struct omap_hwmod_omap2_firewall {
201 u8 l3_perm_bit;
202 u8 l4_fw_region;
203 u8 l4_prot_group;
204 u8 flags;
205 };
207 /*
208 * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
209 * interface to interact with the hwmod. Used to add sleep dependencies
210 * when the module is enabled or disabled.
211 */
212 #define OCP_USER_MPU (1 << 0)
213 #define OCP_USER_SDMA (1 << 1)
214 #define OCP_USER_DSP (1 << 2)
215 #define OCP_USER_IVA (1 << 3)
217 /* omap_hwmod_ocp_if.flags bits */
218 #define OCPIF_SWSUP_IDLE (1 << 0)
219 #define OCPIF_CAN_BURST (1 << 1)
221 /* omap_hwmod_ocp_if._int_flags possibilities */
222 #define _OCPIF_INT_FLAGS_REGISTERED (1 << 0)
225 /**
226 * struct omap_hwmod_ocp_if - OCP interface data
227 * @master: struct omap_hwmod that initiates OCP transactions on this link
228 * @slave: struct omap_hwmod that responds to OCP transactions on this link
229 * @addr: address space associated with this link
230 * @clk: interface clock: OMAP clock name
231 * @_clk: pointer to the interface struct clk (filled in at runtime)
232 * @fw: interface firewall data
233 * @width: OCP data width
234 * @user: initiators using this interface (see OCP_USER_* macros above)
235 * @flags: OCP interface flags (see OCPIF_* macros above)
236 * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
237 *
238 * It may also be useful to add a tag_cnt field for OCP2.x devices.
239 *
240 * Parameter names beginning with an underscore are managed internally by
241 * the omap_hwmod code and should not be set during initialization.
242 */
243 struct omap_hwmod_ocp_if {
244 struct omap_hwmod *master;
245 struct omap_hwmod *slave;
246 struct omap_hwmod_addr_space *addr;
247 const char *clk;
248 struct clk *_clk;
249 struct list_head node;
250 union {
251 struct omap_hwmod_omap2_firewall omap2;
252 } fw;
253 u8 width;
254 u8 user;
255 u8 flags;
256 u8 _int_flags;
257 };
260 /* Macros for use in struct omap_hwmod_sysconfig */
262 /* Flags for use in omap_hwmod_sysconfig.idlemodes */
263 #define MASTER_STANDBY_SHIFT 4
264 #define SLAVE_IDLE_SHIFT 0
265 #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
266 #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
267 #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
268 #define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
269 #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
270 #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
271 #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
272 #define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
274 /* omap_hwmod_sysconfig.sysc_flags capability flags */
275 #define SYSC_HAS_AUTOIDLE (1 << 0)
276 #define SYSC_HAS_SOFTRESET (1 << 1)
277 #define SYSC_HAS_ENAWAKEUP (1 << 2)
278 #define SYSC_HAS_EMUFREE (1 << 3)
279 #define SYSC_HAS_CLOCKACTIVITY (1 << 4)
280 #define SYSC_HAS_SIDLEMODE (1 << 5)
281 #define SYSC_HAS_MIDLEMODE (1 << 6)
282 #define SYSS_HAS_RESET_STATUS (1 << 7)
283 #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
284 #define SYSC_HAS_RESET_STATUS (1 << 9)
285 #define SYSC_HAS_DMADISABLE (1 << 10)
287 /* omap_hwmod_sysconfig.clockact flags */
288 #define CLOCKACT_TEST_BOTH 0x0
289 #define CLOCKACT_TEST_MAIN 0x1
290 #define CLOCKACT_TEST_ICLK 0x2
291 #define CLOCKACT_TEST_NONE 0x3
293 /**
294 * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
295 * @rev_offs: IP block revision register offset (from module base addr)
296 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
297 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
298 * @srst_udelay: Delay needed after doing a softreset in usecs
299 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
300 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
301 * @clockact: the default value of the module CLOCKACTIVITY bits
302 *
303 * @clockact describes to the module which clocks are likely to be
304 * disabled when the PRCM issues its idle request to the module. Some
305 * modules have separate clockdomains for the interface clock and main
306 * functional clock, and can check whether they should acknowledge the
307 * idle request based on the internal module functionality that has
308 * been associated with the clocks marked in @clockact. This field is
309 * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
310 *
311 * @sysc_fields: structure containing the offset positions of various bits in
312 * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
313 * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
314 * whether the device ip is compliant with the original PRCM protocol
315 * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
316 * If the device follows a different scheme for the sysconfig register ,
317 * then this field has to be populated with the correct offset structure.
318 */
319 struct omap_hwmod_class_sysconfig {
320 s32 rev_offs;
321 s32 sysc_offs;
322 s32 syss_offs;
323 u16 sysc_flags;
324 struct sysc_regbits *sysc_fields;
325 u8 srst_udelay;
326 u8 idlemodes;
327 };
329 /**
330 * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
331 * @module_offs: PRCM submodule offset from the start of the PRM/CM
332 * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
333 * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
334 *
335 * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
336 * WKEN, GRPSEL registers. In an ideal world, no extra information
337 * would be needed for IDLEST information, but alas, there are some
338 * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
339 * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
340 */
341 struct omap_hwmod_omap2_prcm {
342 s16 module_offs;
343 u8 idlest_reg_id;
344 u8 idlest_idle_bit;
345 };
347 /*
348 * Possible values for struct omap_hwmod_omap4_prcm.flags
349 *
350 * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
351 * module-level context loss register associated with them; this
352 * flag bit should be set in those cases
353 * HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL
354 * offset of zero; this flag bit should be set in those cases to
355 * distinguish from hwmods that have no clkctrl offset.
356 * HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK: Module clockctrl clock is managed
357 * by the common clock framework and not hwmod.
358 */
359 #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0)
360 #define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1)
361 #define HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK (1 << 2)
363 /**
364 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
365 * @clkctrl_offs: offset of the PRCM clock control register
366 * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM
367 * @context_offs: offset of the RM_*_CONTEXT register
368 * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
369 * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
370 * @submodule_wkdep_bit: bit shift of the WKDEP range
371 * @flags: PRCM register capabilities for this IP block
372 * @modulemode: allowable modulemodes
373 * @context_lost_counter: Count of module level context lost
374 *
375 * If @lostcontext_mask is not defined, context loss check code uses
376 * whole register without masking. @lostcontext_mask should only be
377 * defined in cases where @context_offs register is shared by two or
378 * more hwmods.
379 */
380 struct omap_hwmod_omap4_prcm {
381 u16 clkctrl_offs;
382 u16 rstctrl_offs;
383 u16 rstst_offs;
384 u16 context_offs;
385 u32 lostcontext_mask;
386 u8 submodule_wkdep_bit;
387 u8 modulemode;
388 u8 flags;
389 int context_lost_counter;
390 };
393 /*
394 * omap_hwmod.flags definitions
395 *
396 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
397 * of idle, rather than relying on module smart-idle
398 * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
399 * out of standby, rather than relying on module smart-standby
400 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
401 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
402 * XXX Should be HWMOD_SETUP_NO_RESET
403 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
404 * controller, etc. XXX probably belongs outside the main hwmod file
405 * XXX Should be HWMOD_SETUP_NO_IDLE
406 * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
407 * when module is enabled, rather than the default, which is to
408 * enable autoidle
409 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
410 * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
411 * only for few initiator modules on OMAP2 & 3.
412 * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
413 * This is needed for devices like DSS that require optional clocks enabled
414 * in order to complete the reset. Optional clocks will be disabled
415 * again after the reset.
416 * HWMOD_16BIT_REG: Module has 16bit registers
417 * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for
418 * this IP block comes from an off-chip source and is not always
419 * enabled. This prevents the hwmod code from being able to
420 * enable and reset the IP block early. XXX Eventually it should
421 * be possible to query the clock framework for this information.
422 * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work
423 * correctly if the MPU is allowed to go idle while the
424 * peripherals are active. This is apparently true for the I2C on
425 * OMAP2420, and also the EMAC on AM3517/3505. It's unlikely that
426 * this is really true -- we're probably not configuring something
427 * correctly, or this is being abused to deal with some PM latency
428 * issues -- but we're currently suffering from a shortage of
429 * folks who are able to track these issues down properly.
430 * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
431 * is kept in force-standby mode. Failing to do so causes PM problems
432 * with musb on OMAP3630 at least. Note that musb has a dedicated register
433 * to control MSTANDBY signal when MIDLEMODE is set to force-standby.
434 * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
435 * out of idle, but rely on smart-idle to the put it back in idle,
436 * so the wakeups are still functional (Only known case for now is UART)
437 * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up
438 * events by calling _reconfigure_io_chain() when a device is enabled
439 * or idled.
440 * HWMOD_OPT_CLKS_NEEDED: The optional clocks are needed for the module to
441 * operate and they need to be handled at the same time as the main_clk.
442 * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain
443 * IPs like CPSW on DRA7, where clocks to this module cannot be disabled.
444 * HWMOD_CLKDM_NOAUTO: Allows the hwmod's clockdomain to be prevented from
445 * entering HW_AUTO while hwmod is active. This is needed to workaround
446 * some modules which don't function correctly with HW_AUTO. For example,
447 * DCAN on DRA7x SoC needs this to workaround errata i893.
448 */
449 #define HWMOD_SWSUP_SIDLE (1 << 0)
450 #define HWMOD_SWSUP_MSTANDBY (1 << 1)
451 #define HWMOD_INIT_NO_RESET (1 << 2)
452 #define HWMOD_INIT_NO_IDLE (1 << 3)
453 #define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
454 #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
455 #define HWMOD_NO_IDLEST (1 << 6)
456 #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
457 #define HWMOD_16BIT_REG (1 << 8)
458 #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
459 #define HWMOD_BLOCK_WFI (1 << 10)
460 #define HWMOD_FORCE_MSTANDBY (1 << 11)
461 #define HWMOD_SWSUP_SIDLE_ACT (1 << 12)
462 #define HWMOD_RECONFIG_IO_CHAIN (1 << 13)
463 #define HWMOD_OPT_CLKS_NEEDED (1 << 14)
464 #define HWMOD_NO_IDLE (1 << 15)
465 #define HWMOD_CLKDM_NOAUTO (1 << 16)
467 /*
468 * omap_hwmod._int_flags definitions
469 * These are for internal use only and are managed by the omap_hwmod code.
470 *
471 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
472 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
473 * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
474 * causes the first call to _enable() to only update the pinmux
475 */
476 #define _HWMOD_NO_MPU_PORT (1 << 0)
477 #define _HWMOD_SYSCONFIG_LOADED (1 << 1)
478 #define _HWMOD_SKIP_ENABLE (1 << 2)
480 /*
481 * omap_hwmod._state definitions
482 *
483 * INITIALIZED: reset (optionally), initialized, enabled, disabled
484 * (optionally)
485 *
486 *
487 */
488 #define _HWMOD_STATE_UNKNOWN 0
489 #define _HWMOD_STATE_REGISTERED 1
490 #define _HWMOD_STATE_CLKS_INITED 2
491 #define _HWMOD_STATE_INITIALIZED 3
492 #define _HWMOD_STATE_ENABLED 4
493 #define _HWMOD_STATE_IDLE 5
494 #define _HWMOD_STATE_DISABLED 6
496 /**
497 * struct omap_hwmod_class - the type of an IP block
498 * @name: name of the hwmod_class
499 * @sysc: device SYSCONFIG/SYSSTATUS register data
500 * @rev: revision of the IP class
501 * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
502 * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
503 * @enable_preprogram: ptr to fn to be executed during device enable
504 * @lock: ptr to fn to be executed to lock IP registers
505 * @unlock: ptr to fn to be executed to unlock IP registers
506 *
507 * Represent the class of a OMAP hardware "modules" (e.g. timer,
508 * smartreflex, gpio, uart...)
509 *
510 * @pre_shutdown is a function that will be run immediately before
511 * hwmod clocks are disabled, etc. It is intended for use for hwmods
512 * like the MPU watchdog, which cannot be disabled with the standard
513 * omap_hwmod_shutdown(). The function should return 0 upon success,
514 * or some negative error upon failure. Returning an error will cause
515 * omap_hwmod_shutdown() to abort the device shutdown and return an
516 * error.
517 *
518 * If @reset is defined, then the function it points to will be
519 * executed in place of the standard hwmod _reset() code in
520 * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have
521 * unusual reset sequences - usually processor IP blocks like the IVA.
522 */
523 struct omap_hwmod_class {
524 const char *name;
525 struct omap_hwmod_class_sysconfig *sysc;
526 u32 rev;
527 int (*pre_shutdown)(struct omap_hwmod *oh);
528 int (*reset)(struct omap_hwmod *oh);
529 int (*enable_preprogram)(struct omap_hwmod *oh);
530 void (*lock)(struct omap_hwmod *oh);
531 void (*unlock)(struct omap_hwmod *oh);
532 };
534 /**
535 * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
536 * @name: name of the hwmod
537 * @class: struct omap_hwmod_class * to the class of this hwmod
538 * @od: struct omap_device currently associated with this hwmod (internal use)
539 * @prcm: PRCM data pertaining to this hwmod
540 * @main_clk: main clock: OMAP clock name
541 * @_clk: pointer to the main struct clk (filled in at runtime)
542 * @opt_clks: other device clocks that drivers can request (0..*)
543 * @voltdm: pointer to voltage domain (filled in at runtime)
544 * @dev_attr: arbitrary device attributes that can be passed to the driver
545 * @_sysc_cache: internal-use hwmod flags
546 * @mpu_rt_idx: index of device address space for register target (for DT boot)
547 * @_mpu_rt_va: cached register target start address (internal use)
548 * @_mpu_port: cached MPU register target slave (internal use)
549 * @opt_clks_cnt: number of @opt_clks
550 * @master_cnt: number of @master entries
551 * @slaves_cnt: number of @slave entries
552 * @response_lat: device OCP response latency (in interface clock cycles)
553 * @_int_flags: internal-use hwmod flags
554 * @_state: internal-use hwmod state
555 * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
556 * @flags: hwmod flags (documented below)
557 * @_lock: spinlock serializing operations on this hwmod
558 * @node: list node for hwmod list (internal use)
559 * @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod
560 *
561 * @main_clk refers to this module's "main clock," which for our
562 * purposes is defined as "the functional clock needed for register
563 * accesses to complete." Modules may not have a main clock if the
564 * interface clock also serves as a main clock.
565 *
566 * Parameter names beginning with an underscore are managed internally by
567 * the omap_hwmod code and should not be set during initialization.
568 *
569 * @masters and @slaves are now deprecated.
570 *
571 * @parent_hwmod is temporary; there should be no need for it, as this
572 * information should already be expressed in the OCP interface
573 * structures. @parent_hwmod is present as a workaround until we improve
574 * handling for hwmods with multiple parents (e.g., OMAP4+ DSS with
575 * multiple register targets across different interconnects).
576 */
577 struct omap_hwmod {
578 const char *name;
579 struct omap_hwmod_class *class;
580 struct omap_device *od;
581 struct omap_hwmod_rst_info *rst_lines;
582 union {
583 struct omap_hwmod_omap2_prcm omap2;
584 struct omap_hwmod_omap4_prcm omap4;
585 } prcm;
586 const char *main_clk;
587 struct clk *_clk;
588 struct omap_hwmod_opt_clk *opt_clks;
589 const char *clkdm_name;
590 struct clockdomain *clkdm;
591 struct list_head slave_ports; /* connect to *_TA */
592 void *dev_attr;
593 u32 _sysc_cache;
594 void __iomem *_mpu_rt_va;
595 spinlock_t _lock;
596 struct lock_class_key hwmod_key; /* unique lock class */
597 struct list_head node;
598 struct omap_hwmod_ocp_if *_mpu_port;
599 u32 flags;
600 u8 mpu_rt_idx;
601 u8 response_lat;
602 u8 rst_lines_cnt;
603 u8 opt_clks_cnt;
604 u8 slaves_cnt;
605 u8 hwmods_cnt;
606 u8 _int_flags;
607 u8 _state;
608 u8 _postsetup_state;
609 struct omap_hwmod *parent_hwmod;
610 };
612 struct device_node;
614 struct omap_hwmod *omap_hwmod_lookup(const char *name);
615 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
616 void *data);
618 int __init omap_hwmod_setup_one(const char *name);
619 int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
620 struct device_node *np,
621 struct resource *res);
623 struct ti_sysc_module_data;
624 struct ti_sysc_cookie;
626 int omap_hwmod_init_module(struct device *dev,
627 const struct ti_sysc_module_data *data,
628 struct ti_sysc_cookie *cookie);
630 int omap_hwmod_enable(struct omap_hwmod *oh);
631 int omap_hwmod_idle(struct omap_hwmod *oh);
632 int omap_hwmod_shutdown(struct omap_hwmod *oh);
634 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
635 int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
637 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
638 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
639 int omap_hwmod_softreset(struct omap_hwmod *oh);
641 int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
642 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
643 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
644 const char *name, struct resource *res);
646 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
647 void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
649 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
650 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
652 int omap_hwmod_for_each_by_class(const char *classname,
653 int (*fn)(struct omap_hwmod *oh,
654 void *user),
655 void *user);
657 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
658 int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
660 extern void __init omap_hwmod_init(void);
662 const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
664 /*
665 *
666 */
668 extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
669 void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
670 void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
672 /*
673 * Chip variant-specific hwmod init routines - XXX should be converted
674 * to use initcalls once the initial boot ordering is straightened out
675 */
676 extern int omap2420_hwmod_init(void);
677 extern int omap2430_hwmod_init(void);
678 extern int omap3xxx_hwmod_init(void);
679 extern int omap44xx_hwmod_init(void);
680 extern int omap54xx_hwmod_init(void);
681 extern int am33xx_hwmod_init(void);
682 extern int dm814x_hwmod_init(void);
683 extern int dm816x_hwmod_init(void);
684 extern int dra7xx_hwmod_init(void);
685 int am43xx_hwmod_init(void);
687 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
689 #endif