1 /*
2 *
3 * Copyright (C) 2013 Texas Instruments Incorporated
4 *
5 * Hwmod common for AM335x and AM43x
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/types.h>
19 #include <linux/platform_data/hsmmc-omap.h>
20 #include "omap_hwmod.h"
21 #include "i2c.h"
22 #include "wd_timer.h"
23 #include "cm33xx.h"
24 #include "prm33xx.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
26 #include "prcm43xx.h"
27 #include "common.h"
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
32 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
34 /*
35 * 'l3' class
36 * instance(s): l3_main, l3_s, l3_instr
37 */
38 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
39 .name = "l3",
40 };
42 struct omap_hwmod am33xx_l3_main_hwmod = {
43 .name = "l3_main",
44 .class = &am33xx_l3_hwmod_class,
45 .clkdm_name = "l3_clkdm",
46 .flags = HWMOD_INIT_NO_IDLE,
47 .main_clk = "l3_gclk",
48 .prcm = {
49 .omap4 = {
50 .modulemode = MODULEMODE_SWCTRL,
51 },
52 },
53 };
55 /* l3_s */
56 struct omap_hwmod am33xx_l3_s_hwmod = {
57 .name = "l3_s",
58 .class = &am33xx_l3_hwmod_class,
59 .clkdm_name = "l3s_clkdm",
60 };
62 /* l3_instr */
63 struct omap_hwmod am33xx_l3_instr_hwmod = {
64 .name = "l3_instr",
65 .class = &am33xx_l3_hwmod_class,
66 .clkdm_name = "l3_clkdm",
67 .flags = HWMOD_INIT_NO_IDLE,
68 .main_clk = "l3_gclk",
69 .prcm = {
70 .omap4 = {
71 .modulemode = MODULEMODE_SWCTRL,
72 },
73 },
74 };
76 /*
77 * 'l4' class
78 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
79 */
80 struct omap_hwmod_class am33xx_l4_hwmod_class = {
81 .name = "l4",
82 };
84 /* l4_ls */
85 struct omap_hwmod am33xx_l4_ls_hwmod = {
86 .name = "l4_ls",
87 .class = &am33xx_l4_hwmod_class,
88 .clkdm_name = "l4ls_clkdm",
89 .flags = HWMOD_INIT_NO_IDLE,
90 .main_clk = "l4ls_gclk",
91 .prcm = {
92 .omap4 = {
93 .modulemode = MODULEMODE_SWCTRL,
94 },
95 },
96 };
98 /* l4_wkup */
99 struct omap_hwmod am33xx_l4_wkup_hwmod = {
100 .name = "l4_wkup",
101 .class = &am33xx_l4_hwmod_class,
102 .clkdm_name = "l4_wkup_clkdm",
103 .flags = HWMOD_INIT_NO_IDLE,
104 .prcm = {
105 .omap4 = {
106 .modulemode = MODULEMODE_SWCTRL,
107 },
108 },
109 };
111 /*
112 * 'mpu' class
113 */
114 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
115 .name = "mpu",
116 };
118 struct omap_hwmod am33xx_mpu_hwmod = {
119 .name = "mpu",
120 .class = &am33xx_mpu_hwmod_class,
121 .clkdm_name = "mpu_clkdm",
122 .flags = HWMOD_INIT_NO_IDLE,
123 .main_clk = "dpll_mpu_m2_ck",
124 .prcm = {
125 .omap4 = {
126 .modulemode = MODULEMODE_SWCTRL,
127 },
128 },
129 };
131 /*
132 * 'wakeup m3' class
133 * Wakeup controller sub-system under wakeup domain
134 */
135 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
136 .name = "wkup_m3",
137 };
139 /*
140 * 'pru-icss' class
141 * Programmable Real-Time Unit and Industrial Communication Subsystem
142 */
143 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
144 .name = "pruss",
145 };
147 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
148 { .name = "pruss", .rst_shift = 1 },
149 };
151 /* pru-icss */
152 /* Pseudo hwmod for reset control purpose only */
153 struct omap_hwmod am33xx_pruss_hwmod = {
154 .name = "pruss",
155 .class = &am33xx_pruss_hwmod_class,
156 .clkdm_name = "pruss_ocp_clkdm",
157 .main_clk = "pruss_ocp_gclk",
158 .prcm = {
159 .omap4 = {
160 .modulemode = MODULEMODE_SWCTRL,
161 },
162 },
163 .rst_lines = am33xx_pruss_resets,
164 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
165 };
167 /* gfx */
168 /* Pseudo hwmod for reset control purpose only */
169 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
170 .name = "gfx",
171 };
173 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
174 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
175 };
177 struct omap_hwmod am33xx_gfx_hwmod = {
178 .name = "gfx",
179 .class = &am33xx_gfx_hwmod_class,
180 .clkdm_name = "gfx_l3_clkdm",
181 .main_clk = "gfx_fck_div_ck",
182 .prcm = {
183 .omap4 = {
184 .modulemode = MODULEMODE_SWCTRL,
185 },
186 },
187 .rst_lines = am33xx_gfx_resets,
188 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
189 };
191 /*
192 * 'prcm' class
193 * power and reset manager (whole prcm infrastructure)
194 */
195 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
196 .name = "prcm",
197 };
199 /* prcm */
200 struct omap_hwmod am33xx_prcm_hwmod = {
201 .name = "prcm",
202 .class = &am33xx_prcm_hwmod_class,
203 .clkdm_name = "l4_wkup_clkdm",
204 };
206 /*
207 * 'emif' class
208 * instance(s): emif
209 */
210 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
211 .rev_offs = 0x0000,
212 };
214 struct omap_hwmod_class am33xx_emif_hwmod_class = {
215 .name = "emif",
216 .sysc = &am33xx_emif_sysc,
217 };
219 /*
220 * 'aes0' class
221 */
222 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
223 .rev_offs = 0x80,
224 .sysc_offs = 0x84,
225 .syss_offs = 0x88,
226 .sysc_flags = SYSS_HAS_RESET_STATUS,
227 };
229 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
230 .name = "aes0",
231 .sysc = &am33xx_aes0_sysc,
232 };
234 struct omap_hwmod am33xx_aes0_hwmod = {
235 .name = "aes",
236 .class = &am33xx_aes0_hwmod_class,
237 .clkdm_name = "l3_clkdm",
238 .main_clk = "aes0_fck",
239 .prcm = {
240 .omap4 = {
241 .modulemode = MODULEMODE_SWCTRL,
242 },
243 },
244 };
246 /* sha0 HIB2 (the 'P' (public) device) */
247 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
248 .rev_offs = 0x100,
249 .sysc_offs = 0x110,
250 .syss_offs = 0x114,
251 .sysc_flags = SYSS_HAS_RESET_STATUS,
252 };
254 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
255 .name = "sha0",
256 .sysc = &am33xx_sha0_sysc,
257 };
259 struct omap_hwmod am33xx_sha0_hwmod = {
260 .name = "sham",
261 .class = &am33xx_sha0_hwmod_class,
262 .clkdm_name = "l3_clkdm",
263 .main_clk = "l3_gclk",
264 .prcm = {
265 .omap4 = {
266 .modulemode = MODULEMODE_SWCTRL,
267 },
268 },
269 };
271 /* rng */
272 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
273 .rev_offs = 0x1fe0,
274 .sysc_offs = 0x1fe4,
275 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
276 .idlemodes = SIDLE_FORCE | SIDLE_NO,
277 .sysc_fields = &omap_hwmod_sysc_type1,
278 };
280 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
281 .name = "rng",
282 .sysc = &am33xx_rng_sysc,
283 };
285 struct omap_hwmod am33xx_rng_hwmod = {
286 .name = "rng",
287 .class = &am33xx_rng_hwmod_class,
288 .clkdm_name = "l4ls_clkdm",
289 .flags = HWMOD_SWSUP_SIDLE,
290 .main_clk = "rng_fck",
291 .prcm = {
292 .omap4 = {
293 .modulemode = MODULEMODE_SWCTRL,
294 },
295 },
296 };
298 /* ocmcram */
299 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
300 .name = "ocmcram",
301 };
303 struct omap_hwmod am33xx_ocmcram_hwmod = {
304 .name = "ocmcram",
305 .class = &am33xx_ocmcram_hwmod_class,
306 .clkdm_name = "l3_clkdm",
307 .flags = HWMOD_INIT_NO_IDLE,
308 .main_clk = "l3_gclk",
309 .prcm = {
310 .omap4 = {
311 .modulemode = MODULEMODE_SWCTRL,
312 },
313 },
314 };
316 /* 'smartreflex' class */
317 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
318 .name = "smartreflex",
319 };
321 /* smartreflex0 */
322 struct omap_hwmod am33xx_smartreflex0_hwmod = {
323 .name = "smartreflex0",
324 .class = &am33xx_smartreflex_hwmod_class,
325 .clkdm_name = "l4_wkup_clkdm",
326 .main_clk = "smartreflex0_fck",
327 .prcm = {
328 .omap4 = {
329 .modulemode = MODULEMODE_SWCTRL,
330 },
331 },
332 };
334 /* smartreflex1 */
335 struct omap_hwmod am33xx_smartreflex1_hwmod = {
336 .name = "smartreflex1",
337 .class = &am33xx_smartreflex_hwmod_class,
338 .clkdm_name = "l4_wkup_clkdm",
339 .main_clk = "smartreflex1_fck",
340 .prcm = {
341 .omap4 = {
342 .modulemode = MODULEMODE_SWCTRL,
343 },
344 },
345 };
347 /*
348 * 'control' module class
349 */
350 struct omap_hwmod_class am33xx_control_hwmod_class = {
351 .name = "control",
352 };
354 /*
355 * 'cpgmac' class
356 * cpsw/cpgmac sub system
357 */
358 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
359 .rev_offs = 0x0,
360 .sysc_offs = 0x8,
361 .syss_offs = 0x4,
362 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
363 SYSS_HAS_RESET_STATUS),
364 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
365 MSTANDBY_NO),
366 .sysc_fields = &omap_hwmod_sysc_type3,
367 };
369 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
370 .name = "cpgmac0",
371 .sysc = &am33xx_cpgmac_sysc,
372 };
374 struct omap_hwmod am33xx_cpgmac0_hwmod = {
375 .name = "cpgmac0",
376 .class = &am33xx_cpgmac0_hwmod_class,
377 .clkdm_name = "cpsw_125mhz_clkdm",
378 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
379 HWMOD_NEEDS_REIDLE,
380 .main_clk = "cpsw_125mhz_gclk",
381 .mpu_rt_idx = 1,
382 .prcm = {
383 .omap4 = {
384 .modulemode = MODULEMODE_SWCTRL,
385 },
386 },
387 };
389 /*
390 * mdio class
391 */
392 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
393 .name = "davinci_mdio",
394 };
396 struct omap_hwmod am33xx_mdio_hwmod = {
397 .name = "davinci_mdio",
398 .class = &am33xx_mdio_hwmod_class,
399 .clkdm_name = "cpsw_125mhz_clkdm",
400 .main_clk = "cpsw_125mhz_gclk",
401 };
403 /*
404 * dcan class
405 */
406 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
407 .name = "d_can",
408 };
410 /* dcan0 */
411 struct omap_hwmod am33xx_dcan0_hwmod = {
412 .name = "d_can0",
413 .class = &am33xx_dcan_hwmod_class,
414 .clkdm_name = "l4ls_clkdm",
415 .main_clk = "dcan0_fck",
416 .prcm = {
417 .omap4 = {
418 .modulemode = MODULEMODE_SWCTRL,
419 },
420 },
421 };
423 /* dcan1 */
424 struct omap_hwmod am33xx_dcan1_hwmod = {
425 .name = "d_can1",
426 .class = &am33xx_dcan_hwmod_class,
427 .clkdm_name = "l4ls_clkdm",
428 .main_clk = "dcan1_fck",
429 .prcm = {
430 .omap4 = {
431 .modulemode = MODULEMODE_SWCTRL,
432 },
433 },
434 };
436 /* elm */
437 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
438 .rev_offs = 0x0000,
439 .sysc_offs = 0x0010,
440 .syss_offs = 0x0014,
441 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
442 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
443 SYSS_HAS_RESET_STATUS),
444 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
445 .sysc_fields = &omap_hwmod_sysc_type1,
446 };
448 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
449 .name = "elm",
450 .sysc = &am33xx_elm_sysc,
451 };
453 struct omap_hwmod am33xx_elm_hwmod = {
454 .name = "elm",
455 .class = &am33xx_elm_hwmod_class,
456 .clkdm_name = "l4ls_clkdm",
457 .main_clk = "l4ls_gclk",
458 .prcm = {
459 .omap4 = {
460 .modulemode = MODULEMODE_SWCTRL,
461 },
462 },
463 };
465 /* pwmss */
466 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
467 .rev_offs = 0x0,
468 .sysc_offs = 0x4,
469 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
470 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
471 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
472 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
473 .sysc_fields = &omap_hwmod_sysc_type2,
474 };
476 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
477 .name = "epwmss",
478 .sysc = &am33xx_epwmss_sysc,
479 };
481 /* epwmss0 */
482 struct omap_hwmod am33xx_epwmss0_hwmod = {
483 .name = "epwmss0",
484 .class = &am33xx_epwmss_hwmod_class,
485 .clkdm_name = "l4ls_clkdm",
486 .main_clk = "l4ls_gclk",
487 .prcm = {
488 .omap4 = {
489 .modulemode = MODULEMODE_SWCTRL,
490 },
491 },
492 };
494 /* epwmss1 */
495 struct omap_hwmod am33xx_epwmss1_hwmod = {
496 .name = "epwmss1",
497 .class = &am33xx_epwmss_hwmod_class,
498 .clkdm_name = "l4ls_clkdm",
499 .main_clk = "l4ls_gclk",
500 .prcm = {
501 .omap4 = {
502 .modulemode = MODULEMODE_SWCTRL,
503 },
504 },
505 };
507 /* epwmss2 */
508 struct omap_hwmod am33xx_epwmss2_hwmod = {
509 .name = "epwmss2",
510 .class = &am33xx_epwmss_hwmod_class,
511 .clkdm_name = "l4ls_clkdm",
512 .main_clk = "l4ls_gclk",
513 .prcm = {
514 .omap4 = {
515 .modulemode = MODULEMODE_SWCTRL,
516 },
517 },
518 };
520 /*
521 * 'gpio' class: for gpio 0,1,2,3
522 */
523 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
524 .rev_offs = 0x0000,
525 .sysc_offs = 0x0010,
526 .syss_offs = 0x0114,
527 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
528 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
529 SYSS_HAS_RESET_STATUS),
530 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
531 SIDLE_SMART_WKUP),
532 .sysc_fields = &omap_hwmod_sysc_type1,
533 };
535 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
536 .name = "gpio",
537 .sysc = &am33xx_gpio_sysc,
538 .rev = 2,
539 };
541 /* gpio1 */
542 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
543 { .role = "dbclk", .clk = "gpio1_dbclk" },
544 };
546 struct omap_hwmod am33xx_gpio1_hwmod = {
547 .name = "gpio2",
548 .class = &am33xx_gpio_hwmod_class,
549 .clkdm_name = "l4ls_clkdm",
550 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
551 .main_clk = "l4ls_gclk",
552 .prcm = {
553 .omap4 = {
554 .modulemode = MODULEMODE_SWCTRL,
555 },
556 },
557 .opt_clks = gpio1_opt_clks,
558 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
559 };
561 /* gpio2 */
562 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
563 { .role = "dbclk", .clk = "gpio2_dbclk" },
564 };
566 struct omap_hwmod am33xx_gpio2_hwmod = {
567 .name = "gpio3",
568 .class = &am33xx_gpio_hwmod_class,
569 .clkdm_name = "l4ls_clkdm",
570 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
571 .main_clk = "l4ls_gclk",
572 .prcm = {
573 .omap4 = {
574 .modulemode = MODULEMODE_SWCTRL,
575 },
576 },
577 .opt_clks = gpio2_opt_clks,
578 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
579 };
581 /* gpio3 */
582 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
583 { .role = "dbclk", .clk = "gpio3_dbclk" },
584 };
586 struct omap_hwmod am33xx_gpio3_hwmod = {
587 .name = "gpio4",
588 .class = &am33xx_gpio_hwmod_class,
589 .clkdm_name = "l4ls_clkdm",
590 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
591 .main_clk = "l4ls_gclk",
592 .prcm = {
593 .omap4 = {
594 .modulemode = MODULEMODE_SWCTRL,
595 },
596 },
597 .opt_clks = gpio3_opt_clks,
598 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
599 };
601 /* gpmc */
602 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
603 .rev_offs = 0x0,
604 .sysc_offs = 0x10,
605 .syss_offs = 0x14,
606 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
607 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
608 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
609 .sysc_fields = &omap_hwmod_sysc_type1,
610 };
612 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
613 .name = "gpmc",
614 .sysc = &gpmc_sysc,
615 };
617 struct omap_hwmod am33xx_gpmc_hwmod = {
618 .name = "gpmc",
619 .class = &am33xx_gpmc_hwmod_class,
620 .clkdm_name = "l3s_clkdm",
621 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
622 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS | HWMOD_NEEDS_REIDLE,
623 .main_clk = "l3s_gclk",
624 .prcm = {
625 .omap4 = {
626 .modulemode = MODULEMODE_SWCTRL,
627 },
628 },
629 };
631 /* 'i2c' class */
632 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
633 .rev_offs = 0,
634 .sysc_offs = 0x0010,
635 .syss_offs = 0x0090,
636 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
637 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
638 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
639 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
640 SIDLE_SMART_WKUP),
641 .sysc_fields = &omap_hwmod_sysc_type1,
642 };
644 static struct omap_hwmod_class i2c_class = {
645 .name = "i2c",
646 .sysc = &am33xx_i2c_sysc,
647 .rev = OMAP_I2C_IP_VERSION_2,
648 .reset = &omap_i2c_reset,
649 };
651 /* i2c1 */
652 struct omap_hwmod am33xx_i2c1_hwmod = {
653 .name = "i2c1",
654 .class = &i2c_class,
655 .clkdm_name = "l4_wkup_clkdm",
656 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
657 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
658 .prcm = {
659 .omap4 = {
660 .modulemode = MODULEMODE_SWCTRL,
661 },
662 },
663 };
665 /* i2c1 */
666 struct omap_hwmod am33xx_i2c2_hwmod = {
667 .name = "i2c2",
668 .class = &i2c_class,
669 .clkdm_name = "l4ls_clkdm",
670 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
671 .main_clk = "dpll_per_m2_div4_ck",
672 .prcm = {
673 .omap4 = {
674 .modulemode = MODULEMODE_SWCTRL,
675 },
676 },
677 };
679 /* i2c3 */
680 struct omap_hwmod am33xx_i2c3_hwmod = {
681 .name = "i2c3",
682 .class = &i2c_class,
683 .clkdm_name = "l4ls_clkdm",
684 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
685 .main_clk = "dpll_per_m2_div4_ck",
686 .prcm = {
687 .omap4 = {
688 .modulemode = MODULEMODE_SWCTRL,
689 },
690 },
691 };
693 /*
694 * 'mailbox' class
695 * mailbox module allowing communication between the on-chip processors using a
696 * queued mailbox-interrupt mechanism.
697 */
698 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
699 .rev_offs = 0x0000,
700 .sysc_offs = 0x0010,
701 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
702 SYSC_HAS_SOFTRESET),
703 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
704 .sysc_fields = &omap_hwmod_sysc_type2,
705 };
707 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
708 .name = "mailbox",
709 .sysc = &am33xx_mailbox_sysc,
710 };
712 struct omap_hwmod am33xx_mailbox_hwmod = {
713 .name = "mailbox",
714 .class = &am33xx_mailbox_hwmod_class,
715 .clkdm_name = "l4ls_clkdm",
716 .main_clk = "l4ls_gclk",
717 .prcm = {
718 .omap4 = {
719 .modulemode = MODULEMODE_SWCTRL,
720 },
721 },
722 };
724 /*
725 * 'mcasp' class
726 */
727 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
728 .rev_offs = 0x0,
729 .sysc_offs = 0x4,
730 .sysc_flags = SYSC_HAS_SIDLEMODE,
731 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
732 .sysc_fields = &omap_hwmod_sysc_type3,
733 };
735 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
736 .name = "mcasp",
737 .sysc = &am33xx_mcasp_sysc,
738 };
740 /* mcasp0 */
741 struct omap_hwmod am33xx_mcasp0_hwmod = {
742 .name = "mcasp0",
743 .class = &am33xx_mcasp_hwmod_class,
744 .clkdm_name = "l3s_clkdm",
745 .main_clk = "mcasp0_fck",
746 .prcm = {
747 .omap4 = {
748 .modulemode = MODULEMODE_SWCTRL,
749 },
750 },
751 };
753 /* mcasp1 */
754 struct omap_hwmod am33xx_mcasp1_hwmod = {
755 .name = "mcasp1",
756 .class = &am33xx_mcasp_hwmod_class,
757 .clkdm_name = "l3s_clkdm",
758 .main_clk = "mcasp1_fck",
759 .prcm = {
760 .omap4 = {
761 .modulemode = MODULEMODE_SWCTRL,
762 },
763 },
764 };
766 /* 'mmc' class */
767 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
768 .rev_offs = 0x2fc,
769 .sysc_offs = 0x110,
770 .syss_offs = 0x114,
771 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
772 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
773 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
774 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
775 .sysc_fields = &omap_hwmod_sysc_type1,
776 };
778 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
779 .name = "mmc",
780 .sysc = &am33xx_mmc_sysc,
781 };
783 /* mmc0 */
784 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
785 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
786 };
788 struct omap_hwmod am33xx_mmc0_hwmod = {
789 .name = "mmc1",
790 .class = &am33xx_mmc_hwmod_class,
791 .clkdm_name = "l4ls_clkdm",
792 .main_clk = "mmc_clk",
793 .prcm = {
794 .omap4 = {
795 .modulemode = MODULEMODE_SWCTRL,
796 },
797 },
798 .dev_attr = &am33xx_mmc0_dev_attr,
799 };
801 /* mmc1 */
802 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
803 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
804 };
806 struct omap_hwmod am33xx_mmc1_hwmod = {
807 .name = "mmc2",
808 .class = &am33xx_mmc_hwmod_class,
809 .clkdm_name = "l4ls_clkdm",
810 .main_clk = "mmc_clk",
811 .prcm = {
812 .omap4 = {
813 .modulemode = MODULEMODE_SWCTRL,
814 },
815 },
816 .dev_attr = &am33xx_mmc1_dev_attr,
817 };
819 /* mmc2 */
820 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
821 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
822 };
823 struct omap_hwmod am33xx_mmc2_hwmod = {
824 .name = "mmc3",
825 .class = &am33xx_mmc_hwmod_class,
826 .clkdm_name = "l3s_clkdm",
827 .main_clk = "mmc_clk",
828 .prcm = {
829 .omap4 = {
830 .modulemode = MODULEMODE_SWCTRL,
831 },
832 },
833 .dev_attr = &am33xx_mmc2_dev_attr,
834 };
836 /*
837 * 'rtc' class
838 * rtc subsystem
839 */
840 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
841 .rev_offs = 0x0074,
842 .sysc_offs = 0x0078,
843 .sysc_flags = SYSC_HAS_SIDLEMODE,
844 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
845 SIDLE_SMART | SIDLE_SMART_WKUP),
846 .sysc_fields = &omap_hwmod_sysc_type3,
847 };
849 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
850 .name = "rtc",
851 .sysc = &am33xx_rtc_sysc,
852 .unlock = &omap_hwmod_rtc_unlock,
853 .lock = &omap_hwmod_rtc_lock,
854 };
856 struct omap_hwmod am33xx_rtc_hwmod = {
857 .name = "rtc",
858 .class = &am33xx_rtc_hwmod_class,
859 .clkdm_name = "l4_rtc_clkdm",
860 .main_clk = "clk_32768_ck",
861 .prcm = {
862 .omap4 = {
863 .modulemode = MODULEMODE_SWCTRL,
864 },
865 },
866 };
868 /* 'spi' class */
869 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
870 .rev_offs = 0x0000,
871 .sysc_offs = 0x0110,
872 .syss_offs = 0x0114,
873 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
874 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
875 SYSS_HAS_RESET_STATUS),
876 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
877 .sysc_fields = &omap_hwmod_sysc_type1,
878 };
880 struct omap_hwmod_class am33xx_spi_hwmod_class = {
881 .name = "mcspi",
882 .sysc = &am33xx_mcspi_sysc,
883 };
885 /* spi0 */
886 struct omap_hwmod am33xx_spi0_hwmod = {
887 .name = "spi0",
888 .class = &am33xx_spi_hwmod_class,
889 .clkdm_name = "l4ls_clkdm",
890 .main_clk = "dpll_per_m2_div4_ck",
891 .prcm = {
892 .omap4 = {
893 .modulemode = MODULEMODE_SWCTRL,
894 },
895 },
896 };
898 /* spi1 */
899 struct omap_hwmod am33xx_spi1_hwmod = {
900 .name = "spi1",
901 .class = &am33xx_spi_hwmod_class,
902 .clkdm_name = "l4ls_clkdm",
903 .main_clk = "dpll_per_m2_div4_ck",
904 .prcm = {
905 .omap4 = {
906 .modulemode = MODULEMODE_SWCTRL,
907 },
908 },
909 };
911 /*
912 * 'spinlock' class
913 * spinlock provides hardware assistance for synchronizing the
914 * processes running on multiple processors
915 */
917 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
918 .rev_offs = 0x0000,
919 .sysc_offs = 0x0010,
920 .syss_offs = 0x0014,
921 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
922 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
923 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
924 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
925 .sysc_fields = &omap_hwmod_sysc_type1,
926 };
928 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
929 .name = "spinlock",
930 .sysc = &am33xx_spinlock_sysc,
931 };
933 struct omap_hwmod am33xx_spinlock_hwmod = {
934 .name = "spinlock",
935 .class = &am33xx_spinlock_hwmod_class,
936 .clkdm_name = "l4ls_clkdm",
937 .main_clk = "l4ls_gclk",
938 .prcm = {
939 .omap4 = {
940 .modulemode = MODULEMODE_SWCTRL,
941 },
942 },
943 };
945 /* 'timer 2-7' class */
946 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .syss_offs = 0x0014,
950 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954 };
956 struct omap_hwmod_class am33xx_timer_hwmod_class = {
957 .name = "timer",
958 .sysc = &am33xx_timer_sysc,
959 };
961 /* timer1 1ms */
962 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
963 .rev_offs = 0x0000,
964 .sysc_offs = 0x0010,
965 .syss_offs = 0x0014,
966 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
967 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
968 SYSS_HAS_RESET_STATUS),
969 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
970 .sysc_fields = &omap_hwmod_sysc_type1,
971 };
973 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
974 .name = "timer",
975 .sysc = &am33xx_timer1ms_sysc,
976 };
978 struct omap_hwmod am33xx_timer1_hwmod = {
979 .name = "timer1",
980 .class = &am33xx_timer1ms_hwmod_class,
981 .clkdm_name = "l4_wkup_clkdm",
982 .main_clk = "timer1_fck",
983 .prcm = {
984 .omap4 = {
985 .modulemode = MODULEMODE_SWCTRL,
986 },
987 },
988 };
990 struct omap_hwmod am33xx_timer2_hwmod = {
991 .name = "timer2",
992 .class = &am33xx_timer_hwmod_class,
993 .clkdm_name = "l4ls_clkdm",
994 .main_clk = "timer2_fck",
995 .prcm = {
996 .omap4 = {
997 .modulemode = MODULEMODE_SWCTRL,
998 },
999 },
1000 };
1002 struct omap_hwmod am33xx_timer3_hwmod = {
1003 .name = "timer3",
1004 .class = &am33xx_timer_hwmod_class,
1005 .clkdm_name = "l4ls_clkdm",
1006 .main_clk = "timer3_fck",
1007 .prcm = {
1008 .omap4 = {
1009 .modulemode = MODULEMODE_SWCTRL,
1010 },
1011 },
1012 };
1014 struct omap_hwmod am33xx_timer4_hwmod = {
1015 .name = "timer4",
1016 .class = &am33xx_timer_hwmod_class,
1017 .clkdm_name = "l4ls_clkdm",
1018 .main_clk = "timer4_fck",
1019 .prcm = {
1020 .omap4 = {
1021 .modulemode = MODULEMODE_SWCTRL,
1022 },
1023 },
1024 };
1026 struct omap_hwmod am33xx_timer5_hwmod = {
1027 .name = "timer5",
1028 .class = &am33xx_timer_hwmod_class,
1029 .clkdm_name = "l4ls_clkdm",
1030 .main_clk = "timer5_fck",
1031 .prcm = {
1032 .omap4 = {
1033 .modulemode = MODULEMODE_SWCTRL,
1034 },
1035 },
1036 };
1038 struct omap_hwmod am33xx_timer6_hwmod = {
1039 .name = "timer6",
1040 .class = &am33xx_timer_hwmod_class,
1041 .clkdm_name = "l4ls_clkdm",
1042 .main_clk = "timer6_fck",
1043 .prcm = {
1044 .omap4 = {
1045 .modulemode = MODULEMODE_SWCTRL,
1046 },
1047 },
1048 };
1050 struct omap_hwmod am33xx_timer7_hwmod = {
1051 .name = "timer7",
1052 .class = &am33xx_timer_hwmod_class,
1053 .clkdm_name = "l4ls_clkdm",
1054 .main_clk = "timer7_fck",
1055 .prcm = {
1056 .omap4 = {
1057 .modulemode = MODULEMODE_SWCTRL,
1058 },
1059 },
1060 };
1062 /* tpcc */
1063 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1064 .name = "tpcc",
1065 };
1067 struct omap_hwmod am33xx_tpcc_hwmod = {
1068 .name = "tpcc",
1069 .class = &am33xx_tpcc_hwmod_class,
1070 .clkdm_name = "l3_clkdm",
1071 .main_clk = "l3_gclk",
1072 .prcm = {
1073 .omap4 = {
1074 .modulemode = MODULEMODE_SWCTRL,
1075 },
1076 },
1077 };
1079 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1080 .rev_offs = 0x0,
1081 .sysc_offs = 0x10,
1082 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1083 SYSC_HAS_MIDLEMODE),
1084 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1085 .sysc_fields = &omap_hwmod_sysc_type2,
1086 };
1088 /* 'tptc' class */
1089 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1090 .name = "tptc",
1091 .sysc = &am33xx_tptc_sysc,
1092 };
1094 /* tptc0 */
1095 struct omap_hwmod am33xx_tptc0_hwmod = {
1096 .name = "tptc0",
1097 .class = &am33xx_tptc_hwmod_class,
1098 .clkdm_name = "l3_clkdm",
1099 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1100 HWMOD_NEEDS_REIDLE,
1101 .main_clk = "l3_gclk",
1102 .prcm = {
1103 .omap4 = {
1104 .modulemode = MODULEMODE_SWCTRL,
1105 },
1106 },
1107 };
1109 /* tptc1 */
1110 struct omap_hwmod am33xx_tptc1_hwmod = {
1111 .name = "tptc1",
1112 .class = &am33xx_tptc_hwmod_class,
1113 .clkdm_name = "l3_clkdm",
1114 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1115 HWMOD_NEEDS_REIDLE,
1116 .main_clk = "l3_gclk",
1117 .prcm = {
1118 .omap4 = {
1119 .modulemode = MODULEMODE_SWCTRL,
1120 },
1121 },
1122 };
1124 /* tptc2 */
1125 struct omap_hwmod am33xx_tptc2_hwmod = {
1126 .name = "tptc2",
1127 .class = &am33xx_tptc_hwmod_class,
1128 .clkdm_name = "l3_clkdm",
1129 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1130 HWMOD_NEEDS_REIDLE,
1131 .main_clk = "l3_gclk",
1132 .prcm = {
1133 .omap4 = {
1134 .modulemode = MODULEMODE_SWCTRL,
1135 },
1136 },
1137 };
1139 /* 'uart' class */
1140 static struct omap_hwmod_class_sysconfig uart_sysc = {
1141 .rev_offs = 0x50,
1142 .sysc_offs = 0x54,
1143 .syss_offs = 0x58,
1144 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1145 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1146 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1147 SIDLE_SMART_WKUP),
1148 .sysc_fields = &omap_hwmod_sysc_type1,
1149 };
1151 static struct omap_hwmod_class uart_class = {
1152 .name = "uart",
1153 .sysc = &uart_sysc,
1154 };
1156 struct omap_hwmod am33xx_uart1_hwmod = {
1157 .name = "uart1",
1158 .class = &uart_class,
1159 .clkdm_name = "l4_wkup_clkdm",
1160 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1161 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1162 .prcm = {
1163 .omap4 = {
1164 .modulemode = MODULEMODE_SWCTRL,
1165 },
1166 },
1167 };
1169 struct omap_hwmod am33xx_uart2_hwmod = {
1170 .name = "uart2",
1171 .class = &uart_class,
1172 .clkdm_name = "l4ls_clkdm",
1173 .flags = HWMOD_SWSUP_SIDLE_ACT,
1174 .main_clk = "dpll_per_m2_div4_ck",
1175 .prcm = {
1176 .omap4 = {
1177 .modulemode = MODULEMODE_SWCTRL,
1178 },
1179 },
1180 };
1182 /* uart3 */
1183 struct omap_hwmod am33xx_uart3_hwmod = {
1184 .name = "uart3",
1185 .class = &uart_class,
1186 .clkdm_name = "l4ls_clkdm",
1187 .flags = HWMOD_SWSUP_SIDLE_ACT,
1188 .main_clk = "dpll_per_m2_div4_ck",
1189 .prcm = {
1190 .omap4 = {
1191 .modulemode = MODULEMODE_SWCTRL,
1192 },
1193 },
1194 };
1196 struct omap_hwmod am33xx_uart4_hwmod = {
1197 .name = "uart4",
1198 .class = &uart_class,
1199 .clkdm_name = "l4ls_clkdm",
1200 .flags = HWMOD_SWSUP_SIDLE_ACT,
1201 .main_clk = "dpll_per_m2_div4_ck",
1202 .prcm = {
1203 .omap4 = {
1204 .modulemode = MODULEMODE_SWCTRL,
1205 },
1206 },
1207 };
1209 struct omap_hwmod am33xx_uart5_hwmod = {
1210 .name = "uart5",
1211 .class = &uart_class,
1212 .clkdm_name = "l4ls_clkdm",
1213 .flags = HWMOD_SWSUP_SIDLE_ACT,
1214 .main_clk = "dpll_per_m2_div4_ck",
1215 .prcm = {
1216 .omap4 = {
1217 .modulemode = MODULEMODE_SWCTRL,
1218 },
1219 },
1220 };
1222 struct omap_hwmod am33xx_uart6_hwmod = {
1223 .name = "uart6",
1224 .class = &uart_class,
1225 .clkdm_name = "l4ls_clkdm",
1226 .flags = HWMOD_SWSUP_SIDLE_ACT,
1227 .main_clk = "dpll_per_m2_div4_ck",
1228 .prcm = {
1229 .omap4 = {
1230 .modulemode = MODULEMODE_SWCTRL,
1231 },
1232 },
1233 };
1235 /* 'wd_timer' class */
1236 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1237 .rev_offs = 0x0,
1238 .sysc_offs = 0x10,
1239 .syss_offs = 0x14,
1240 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1241 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1242 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1243 SIDLE_SMART_WKUP),
1244 .sysc_fields = &omap_hwmod_sysc_type1,
1245 };
1247 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1248 .name = "wd_timer",
1249 .sysc = &wdt_sysc,
1250 .pre_shutdown = &omap2_wd_timer_disable,
1251 };
1253 /*
1254 * XXX: device.c file uses hardcoded name for watchdog timer
1255 * driver "wd_timer2, so we are also using same name as of now...
1256 */
1257 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1258 .name = "wd_timer2",
1259 .class = &am33xx_wd_timer_hwmod_class,
1260 .clkdm_name = "l4_wkup_clkdm",
1261 .flags = HWMOD_SWSUP_SIDLE,
1262 .main_clk = "wdt1_fck",
1263 .prcm = {
1264 .omap4 = {
1265 .modulemode = MODULEMODE_SWCTRL,
1266 },
1267 },
1268 };
1270 static void omap_hwmod_am33xx_clkctrl(void)
1271 {
1272 CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1273 CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1274 CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1275 CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1276 CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1277 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1278 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1279 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1280 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1281 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1282 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1283 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1284 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1285 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1286 CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1287 CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1288 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1289 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1290 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1291 CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1292 CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1293 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1294 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1295 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1296 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1297 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1298 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1299 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1300 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1301 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1302 CLKCTRL(am33xx_smartreflex0_hwmod,
1303 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1304 CLKCTRL(am33xx_smartreflex1_hwmod,
1305 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1306 CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1307 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1308 CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1309 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1310 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1311 PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1312 CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1313 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1314 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1315 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1316 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1317 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1318 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1319 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1320 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1321 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1322 CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1323 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1324 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1325 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1326 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1327 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1328 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1329 CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1330 }
1332 static void omap_hwmod_am33xx_rst(void)
1333 {
1334 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1335 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1336 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1337 }
1339 void omap_hwmod_am33xx_reg(void)
1340 {
1341 omap_hwmod_am33xx_clkctrl();
1342 omap_hwmod_am33xx_rst();
1343 }
1345 static void omap_hwmod_am43xx_clkctrl(void)
1346 {
1347 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1348 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1349 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1350 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1351 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1352 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1353 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1354 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1355 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1356 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1357 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1358 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1359 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1360 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1361 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1362 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1363 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1364 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1365 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1366 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1367 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1368 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1369 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1370 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1371 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1372 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1373 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1374 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1375 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1376 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1377 CLKCTRL(am33xx_smartreflex0_hwmod,
1378 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1379 CLKCTRL(am33xx_smartreflex1_hwmod,
1380 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1381 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1382 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1383 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1384 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1385 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1386 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1387 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1388 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1389 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1390 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1391 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1392 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1393 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1394 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1395 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1396 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1397 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1398 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1399 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1400 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1401 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1402 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1403 CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1404 }
1406 static void omap_hwmod_am43xx_rst(void)
1407 {
1408 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1409 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1410 RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1411 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1412 }
1414 void omap_hwmod_am43xx_reg(void)
1415 {
1416 omap_hwmod_am43xx_clkctrl();
1417 omap_hwmod_am43xx_rst();
1418 }