ARM: OMAP2+: omap_hwmod: Introduce HWMOD_NEEDS_REIDLE
[rpmsg/hwspinlock.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3  *
4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This file is automatically generated from the AM33XX hardware databases.
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
17 #include <linux/platform_data/i2c-omap.h>
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_common_data.h"
22 #include "control.h"
23 #include "cm33xx.h"
24 #include "prm33xx.h"
25 #include "prm-regbits-33xx.h"
26 #include "i2c.h"
27 #include "wd_timer.h"
28 #include "omap_hwmod_33xx_43xx_common_data.h"
30 /*
31  * IP blocks
32  */
34 /* emif */
35 static struct omap_hwmod am33xx_emif_hwmod = {
36         .name           = "emif",
37         .class          = &am33xx_emif_hwmod_class,
38         .clkdm_name     = "l3_clkdm",
39         .flags          = HWMOD_INIT_NO_IDLE,
40         .main_clk       = "dpll_ddr_m2_div2_ck",
41         .prcm           = {
42                 .omap4  = {
43                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
44                         .modulemode     = MODULEMODE_SWCTRL,
45                 },
46         },
47 };
49 /* l4_hs */
50 static struct omap_hwmod am33xx_l4_hs_hwmod = {
51         .name           = "l4_hs",
52         .class          = &am33xx_l4_hwmod_class,
53         .clkdm_name     = "l4hs_clkdm",
54         .flags          = HWMOD_INIT_NO_IDLE,
55         .main_clk       = "l4hs_gclk",
56         .prcm           = {
57                 .omap4  = {
58                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
59                         .modulemode     = MODULEMODE_SWCTRL,
60                 },
61         },
62 };
64 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
65         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
66 };
68 /* wkup_m3  */
69 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
70         .name           = "wkup_m3",
71         .class          = &am33xx_wkup_m3_hwmod_class,
72         .clkdm_name     = "l4_wkup_aon_clkdm",
73         /* Keep hardreset asserted */
74         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
75         .main_clk       = "dpll_core_m4_div2_ck",
76         .prcm           = {
77                 .omap4  = {
78                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
79                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
80                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
81                         .modulemode     = MODULEMODE_SWCTRL,
82                 },
83         },
84         .rst_lines      = am33xx_wkup_m3_resets,
85         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
86 };
88 /*
89  * 'adc/tsc' class
90  * TouchScreen Controller (Anolog-To-Digital Converter)
91  */
92 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
93         .rev_offs       = 0x00,
94         .sysc_offs      = 0x10,
95         .sysc_flags     = SYSC_HAS_SIDLEMODE,
96         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
97                         SIDLE_SMART_WKUP),
98         .sysc_fields    = &omap_hwmod_sysc_type2,
99 };
101 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
102         .name           = "adc_tsc",
103         .sysc           = &am33xx_adc_tsc_sysc,
104 };
106 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
107         .name           = "adc_tsc",
108         .class          = &am33xx_adc_tsc_hwmod_class,
109         .clkdm_name     = "l4_wkup_clkdm",
110         .main_clk       = "adc_tsc_fck",
111         .prcm           = {
112                 .omap4  = {
113                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
114                         .modulemode     = MODULEMODE_SWCTRL,
115                 },
116         },
117 };
119 /*
120  * Modules omap_hwmod structures
121  *
122  * The following IPs are excluded for the moment because:
123  * - They do not need an explicit SW control using omap_hwmod API.
124  * - They still need to be validated with the driver
125  *   properly adapted to omap_hwmod / omap_device
126  *
127  *    - cEFUSE (doesn't fall under any ocp_if)
128  *    - clkdiv32k
129  *    - ocp watch point
130  */
131 #if 0
132 /*
133  * 'cefuse' class
134  */
135 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
136         .name           = "cefuse",
137 };
139 static struct omap_hwmod am33xx_cefuse_hwmod = {
140         .name           = "cefuse",
141         .class          = &am33xx_cefuse_hwmod_class,
142         .clkdm_name     = "l4_cefuse_clkdm",
143         .main_clk       = "cefuse_fck",
144         .prcm           = {
145                 .omap4  = {
146                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
147                         .modulemode     = MODULEMODE_SWCTRL,
148                 },
149         },
150 };
152 /*
153  * 'clkdiv32k' class
154  */
155 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
156         .name           = "clkdiv32k",
157 };
159 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
160         .name           = "clkdiv32k",
161         .class          = &am33xx_clkdiv32k_hwmod_class,
162         .clkdm_name     = "clk_24mhz_clkdm",
163         .main_clk       = "clkdiv32k_ick",
164         .prcm           = {
165                 .omap4  = {
166                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
167                         .modulemode     = MODULEMODE_SWCTRL,
168                 },
169         },
170 };
172 /* ocpwp */
173 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
174         .name           = "ocpwp",
175 };
177 static struct omap_hwmod am33xx_ocpwp_hwmod = {
178         .name           = "ocpwp",
179         .class          = &am33xx_ocpwp_hwmod_class,
180         .clkdm_name     = "l4ls_clkdm",
181         .main_clk       = "l4ls_gclk",
182         .prcm           = {
183                 .omap4  = {
184                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
185                         .modulemode     = MODULEMODE_SWCTRL,
186                 },
187         },
188 };
189 #endif
191 /*
192  * 'debugss' class
193  * debug sub system
194  */
195 static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
196         { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
197         { .role = "dbg_clka", .clk = "dbg_clka_ck" },
198 };
200 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
201         .name           = "debugss",
202 };
204 static struct omap_hwmod am33xx_debugss_hwmod = {
205         .name           = "debugss",
206         .class          = &am33xx_debugss_hwmod_class,
207         .clkdm_name     = "l3_aon_clkdm",
208         .main_clk       = "trace_clk_div_ck",
209         .prcm           = {
210                 .omap4  = {
211                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
212                         .modulemode     = MODULEMODE_SWCTRL,
213                 },
214         },
215         .opt_clks       = debugss_opt_clks,
216         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
217 };
219 static struct omap_hwmod am33xx_control_hwmod = {
220         .name           = "control",
221         .class          = &am33xx_control_hwmod_class,
222         .clkdm_name     = "l4_wkup_clkdm",
223         .flags          = HWMOD_INIT_NO_IDLE,
224         .main_clk       = "dpll_core_m4_div2_ck",
225         .prcm           = {
226                 .omap4  = {
227                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
228                         .modulemode     = MODULEMODE_SWCTRL,
229                 },
230         },
231 };
233 /* gpio0 */
234 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
235         { .role = "dbclk", .clk = "gpio0_dbclk" },
236 };
238 static struct omap_hwmod am33xx_gpio0_hwmod = {
239         .name           = "gpio1",
240         .class          = &am33xx_gpio_hwmod_class,
241         .clkdm_name     = "l4_wkup_clkdm",
242         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
243         .main_clk       = "dpll_core_m4_div2_ck",
244         .prcm           = {
245                 .omap4  = {
246                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
247                         .modulemode     = MODULEMODE_SWCTRL,
248                 },
249         },
250         .opt_clks       = gpio0_opt_clks,
251         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
252 };
254 /* lcdc */
255 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
256         .rev_offs       = 0x0,
257         .sysc_offs      = 0x54,
258         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
259         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
260         .sysc_fields    = &omap_hwmod_sysc_type2,
261 };
263 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
264         .name           = "lcdc",
265         .sysc           = &lcdc_sysc,
266 };
268 static struct omap_hwmod am33xx_lcdc_hwmod = {
269         .name           = "lcdc",
270         .class          = &am33xx_lcdc_hwmod_class,
271         .clkdm_name     = "lcdc_clkdm",
272         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
273         .main_clk       = "lcd_gclk",
274         .prcm           = {
275                 .omap4  = {
276                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
277                         .modulemode     = MODULEMODE_SWCTRL,
278                 },
279         },
280 };
282 /*
283  * 'usb_otg' class
284  * high-speed on-the-go universal serial bus (usb_otg) controller
285  */
286 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
287         .rev_offs       = 0x0,
288         .sysc_offs      = 0x10,
289         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
290         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
291                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
292         .sysc_fields    = &omap_hwmod_sysc_type2,
293 };
295 static struct omap_hwmod_class am33xx_usbotg_class = {
296         .name           = "usbotg",
297         .sysc           = &am33xx_usbhsotg_sysc,
298 };
300 static struct omap_hwmod am33xx_usbss_hwmod = {
301         .name           = "usb_otg_hs",
302         .class          = &am33xx_usbotg_class,
303         .clkdm_name     = "l3s_clkdm",
304         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
305                           HWMOD_NEEDS_REIDLE,
306         .main_clk       = "usbotg_fck",
307         .prcm           = {
308                 .omap4  = {
309                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
310                         .modulemode     = MODULEMODE_SWCTRL,
311                 },
312         },
313 };
316 /*
317  * Interfaces
318  */
320 /* l3 main -> emif */
321 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
322         .master         = &am33xx_l3_main_hwmod,
323         .slave          = &am33xx_emif_hwmod,
324         .clk            = "dpll_core_m4_ck",
325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
326 };
328 /* l3 main -> l4 hs */
329 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
330         .master         = &am33xx_l3_main_hwmod,
331         .slave          = &am33xx_l4_hs_hwmod,
332         .clk            = "l3s_gclk",
333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
334 };
336 /* wkup m3 -> l4 wkup */
337 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
338         .master         = &am33xx_wkup_m3_hwmod,
339         .slave          = &am33xx_l4_wkup_hwmod,
340         .clk            = "dpll_core_m4_div2_ck",
341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
342 };
344 /* l4 wkup -> wkup m3 */
345 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
346         .master         = &am33xx_l4_wkup_hwmod,
347         .slave          = &am33xx_wkup_m3_hwmod,
348         .clk            = "dpll_core_m4_div2_ck",
349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
350 };
352 /* l4 hs -> pru-icss */
353 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
354         .master         = &am33xx_l4_hs_hwmod,
355         .slave          = &am33xx_pruss_hwmod,
356         .clk            = "dpll_core_m4_ck",
357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
358 };
360 /* l3_main -> debugss */
361 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
362         .master         = &am33xx_l3_main_hwmod,
363         .slave          = &am33xx_debugss_hwmod,
364         .clk            = "dpll_core_m4_ck",
365         .user           = OCP_USER_MPU,
366 };
368 /* l4 wkup -> smartreflex0 */
369 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
370         .master         = &am33xx_l4_wkup_hwmod,
371         .slave          = &am33xx_smartreflex0_hwmod,
372         .clk            = "dpll_core_m4_div2_ck",
373         .user           = OCP_USER_MPU,
374 };
376 /* l4 wkup -> smartreflex1 */
377 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
378         .master         = &am33xx_l4_wkup_hwmod,
379         .slave          = &am33xx_smartreflex1_hwmod,
380         .clk            = "dpll_core_m4_div2_ck",
381         .user           = OCP_USER_MPU,
382 };
384 /* l4 wkup -> control */
385 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
386         .master         = &am33xx_l4_wkup_hwmod,
387         .slave          = &am33xx_control_hwmod,
388         .clk            = "dpll_core_m4_div2_ck",
389         .user           = OCP_USER_MPU,
390 };
392 /* L4 WKUP -> I2C1 */
393 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
394         .master         = &am33xx_l4_wkup_hwmod,
395         .slave          = &am33xx_i2c1_hwmod,
396         .clk            = "dpll_core_m4_div2_ck",
397         .user           = OCP_USER_MPU,
398 };
400 /* L4 WKUP -> GPIO1 */
401 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
402         .master         = &am33xx_l4_wkup_hwmod,
403         .slave          = &am33xx_gpio0_hwmod,
404         .clk            = "dpll_core_m4_div2_ck",
405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
406 };
408 /* L4 WKUP -> ADC_TSC */
409 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
410         .master         = &am33xx_l4_wkup_hwmod,
411         .slave          = &am33xx_adc_tsc_hwmod,
412         .clk            = "dpll_core_m4_div2_ck",
413         .user           = OCP_USER_MPU,
414 };
416 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
417         .master         = &am33xx_l4_hs_hwmod,
418         .slave          = &am33xx_cpgmac0_hwmod,
419         .clk            = "cpsw_125mhz_gclk",
420         .user           = OCP_USER_MPU,
421 };
423 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
424         .master         = &am33xx_l3_main_hwmod,
425         .slave          = &am33xx_lcdc_hwmod,
426         .clk            = "dpll_core_m4_ck",
427         .user           = OCP_USER_MPU,
428 };
430 /* l4 wkup -> timer1 */
431 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
432         .master         = &am33xx_l4_wkup_hwmod,
433         .slave          = &am33xx_timer1_hwmod,
434         .clk            = "dpll_core_m4_div2_ck",
435         .user           = OCP_USER_MPU,
436 };
438 /* l4 wkup -> uart1 */
439 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
440         .master         = &am33xx_l4_wkup_hwmod,
441         .slave          = &am33xx_uart1_hwmod,
442         .clk            = "dpll_core_m4_div2_ck",
443         .user           = OCP_USER_MPU,
444 };
446 /* l4 wkup -> wd_timer1 */
447 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
448         .master         = &am33xx_l4_wkup_hwmod,
449         .slave          = &am33xx_wd_timer1_hwmod,
450         .clk            = "dpll_core_m4_div2_ck",
451         .user           = OCP_USER_MPU,
452 };
454 /* usbss */
455 /* l3 s -> USBSS interface */
456 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
457         .master         = &am33xx_l3_s_hwmod,
458         .slave          = &am33xx_usbss_hwmod,
459         .clk            = "l3s_gclk",
460         .user           = OCP_USER_MPU,
461         .flags          = OCPIF_SWSUP_IDLE,
462 };
464 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
465         &am33xx_l3_main__emif,
466         &am33xx_mpu__l3_main,
467         &am33xx_mpu__prcm,
468         &am33xx_l3_s__l4_ls,
469         &am33xx_l3_s__l4_wkup,
470         &am33xx_l3_main__l4_hs,
471         &am33xx_l3_main__l3_s,
472         &am33xx_l3_main__l3_instr,
473         &am33xx_l3_main__gfx,
474         &am33xx_l3_s__l3_main,
475         &am33xx_pruss__l3_main,
476         &am33xx_wkup_m3__l4_wkup,
477         &am33xx_gfx__l3_main,
478         &am33xx_l3_main__debugss,
479         &am33xx_l4_wkup__wkup_m3,
480         &am33xx_l4_wkup__control,
481         &am33xx_l4_wkup__smartreflex0,
482         &am33xx_l4_wkup__smartreflex1,
483         &am33xx_l4_wkup__uart1,
484         &am33xx_l4_wkup__timer1,
485         &am33xx_l4_wkup__rtc,
486         &am33xx_l4_wkup__i2c1,
487         &am33xx_l4_wkup__gpio0,
488         &am33xx_l4_wkup__adc_tsc,
489         &am33xx_l4_wkup__wd_timer1,
490         &am33xx_l4_hs__pruss,
491         &am33xx_l4_per__dcan0,
492         &am33xx_l4_per__dcan1,
493         &am33xx_l4_per__gpio1,
494         &am33xx_l4_per__gpio2,
495         &am33xx_l4_per__gpio3,
496         &am33xx_l4_per__i2c2,
497         &am33xx_l4_per__i2c3,
498         &am33xx_l4_per__mailbox,
499         &am33xx_l4_ls__mcasp0,
500         &am33xx_l4_ls__mcasp1,
501         &am33xx_l4_ls__mmc0,
502         &am33xx_l4_ls__mmc1,
503         &am33xx_l3_s__mmc2,
504         &am33xx_l4_ls__timer2,
505         &am33xx_l4_ls__timer3,
506         &am33xx_l4_ls__timer4,
507         &am33xx_l4_ls__timer5,
508         &am33xx_l4_ls__timer6,
509         &am33xx_l4_ls__timer7,
510         &am33xx_l3_main__tpcc,
511         &am33xx_l4_ls__uart2,
512         &am33xx_l4_ls__uart3,
513         &am33xx_l4_ls__uart4,
514         &am33xx_l4_ls__uart5,
515         &am33xx_l4_ls__uart6,
516         &am33xx_l4_ls__spinlock,
517         &am33xx_l4_ls__elm,
518         &am33xx_l4_ls__epwmss0,
519         &am33xx_l4_ls__epwmss1,
520         &am33xx_l4_ls__epwmss2,
521         &am33xx_l3_s__gpmc,
522         &am33xx_l3_main__lcdc,
523         &am33xx_l4_ls__mcspi0,
524         &am33xx_l4_ls__mcspi1,
525         &am33xx_l3_main__tptc0,
526         &am33xx_l3_main__tptc1,
527         &am33xx_l3_main__tptc2,
528         &am33xx_l3_main__ocmc,
529         &am33xx_l3_s__usbss,
530         &am33xx_l4_hs__cpgmac0,
531         &am33xx_cpgmac0__mdio,
532         &am33xx_l3_main__sha0,
533         &am33xx_l3_main__aes0,
534         &am33xx_l4_per__rng,
535         NULL,
536 };
538 int __init am33xx_hwmod_init(void)
540         omap_hwmod_am33xx_reg();
541         omap_hwmod_init();
542         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);