1 /*
2 * TI Clock driver internal definitions
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16 #ifndef __DRIVERS_CLK_TI_CLOCK__
17 #define __DRIVERS_CLK_TI_CLOCK__
19 struct clk_omap_divider {
20 struct clk_hw hw;
21 struct clk_omap_reg reg;
22 u8 shift;
23 u8 width;
24 u8 flags;
25 s8 latch;
26 const struct clk_div_table *table;
27 u32 context;
28 };
30 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
32 struct clk_omap_mux {
33 struct clk_hw hw;
34 struct clk_omap_reg reg;
35 u32 *table;
36 u32 mask;
37 u8 shift;
38 s8 latch;
39 u8 flags;
40 u8 saved_parent;
41 };
43 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
45 enum {
46 TI_CLK_FIXED,
47 TI_CLK_MUX,
48 TI_CLK_DIVIDER,
49 TI_CLK_COMPOSITE,
50 TI_CLK_FIXED_FACTOR,
51 TI_CLK_GATE,
52 TI_CLK_DPLL,
53 };
55 /* Global flags */
56 #define CLKF_INDEX_POWER_OF_TWO (1 << 0)
57 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
58 #define CLKF_SET_RATE_PARENT (1 << 2)
59 #define CLKF_OMAP3 (1 << 3)
60 #define CLKF_AM35XX (1 << 4)
62 /* Gate flags */
63 #define CLKF_SET_BIT_TO_DISABLE (1 << 5)
64 #define CLKF_INTERFACE (1 << 6)
65 #define CLKF_SSI (1 << 7)
66 #define CLKF_DSS (1 << 8)
67 #define CLKF_HSOTGUSB (1 << 9)
68 #define CLKF_WAIT (1 << 10)
69 #define CLKF_NO_WAIT (1 << 11)
70 #define CLKF_HSDIV (1 << 12)
71 #define CLKF_CLKDM (1 << 13)
73 /* DPLL flags */
74 #define CLKF_LOW_POWER_STOP (1 << 5)
75 #define CLKF_LOCK (1 << 6)
76 #define CLKF_LOW_POWER_BYPASS (1 << 7)
77 #define CLKF_PER (1 << 8)
78 #define CLKF_CORE (1 << 9)
79 #define CLKF_J_TYPE (1 << 10)
81 /* CLKCTRL flags */
82 #define CLKF_SW_SUP BIT(5)
83 #define CLKF_HW_SUP BIT(6)
84 #define CLKF_NO_IDLEST BIT(7)
86 #define CLK(dev, con, ck) \
87 { \
88 .lk = { \
89 .dev_id = dev, \
90 .con_id = con, \
91 }, \
92 .clk = ck, \
93 }
95 struct ti_clk {
96 const char *name;
97 const char *clkdm_name;
98 int type;
99 void *data;
100 struct ti_clk *patch;
101 struct clk *clk;
102 };
104 struct ti_clk_mux {
105 u8 bit_shift;
106 int num_parents;
107 u16 reg;
108 u8 module;
109 const char * const *parents;
110 u16 flags;
111 };
113 struct ti_clk_divider {
114 const char *parent;
115 u8 bit_shift;
116 u16 max_div;
117 u16 reg;
118 u8 module;
119 int *dividers;
120 int num_dividers;
121 u16 flags;
122 };
124 struct ti_clk_gate {
125 const char *parent;
126 u8 bit_shift;
127 u16 reg;
128 u8 module;
129 u16 flags;
130 };
132 /* Composite clock component types */
133 enum {
134 CLK_COMPONENT_TYPE_GATE = 0,
135 CLK_COMPONENT_TYPE_DIVIDER,
136 CLK_COMPONENT_TYPE_MUX,
137 CLK_COMPONENT_TYPE_MAX,
138 };
140 /**
141 * struct ti_dt_clk - OMAP DT clock alias declarations
142 * @lk: clock lookup definition
143 * @node_name: clock DT node to map to
144 */
145 struct ti_dt_clk {
146 struct clk_lookup lk;
147 char *node_name;
148 };
150 #define DT_CLK(dev, con, name) \
151 { \
152 .lk = { \
153 .dev_id = dev, \
154 .con_id = con, \
155 }, \
156 .node_name = name, \
157 }
159 /* CLKCTRL type definitions */
160 struct omap_clkctrl_div_data {
161 const int *dividers;
162 int max_div;
163 u32 flags;
164 };
166 struct omap_clkctrl_bit_data {
167 u8 bit;
168 u8 type;
169 const char * const *parents;
170 const void *data;
171 };
173 struct omap_clkctrl_reg_data {
174 u16 offset;
175 const struct omap_clkctrl_bit_data *bit_data;
176 u16 flags;
177 const char *parent;
178 const char *clkdm_name;
179 };
181 struct omap_clkctrl_data {
182 u32 addr;
183 const struct omap_clkctrl_reg_data *regs;
184 };
186 extern const struct omap_clkctrl_data omap4_clkctrl_data[];
187 extern const struct omap_clkctrl_data omap5_clkctrl_data[];
188 extern const struct omap_clkctrl_data dra7_clkctrl_data[];
189 extern const struct omap_clkctrl_data am3_clkctrl_data[];
190 extern const struct omap_clkctrl_data am4_clkctrl_data[];
191 extern const struct omap_clkctrl_data am438x_clkctrl_data[];
192 extern const struct omap_clkctrl_data dm814_clkctrl_data[];
193 extern const struct omap_clkctrl_data dm816_clkctrl_data[];
195 typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
197 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
198 const char *con);
199 int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
200 void ti_clk_add_aliases(void);
202 void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
204 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
206 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
207 u8 flags, u8 *width,
208 const struct clk_div_table **table);
210 int ti_clk_get_reg_addr(struct device_node *node, int index,
211 struct clk_omap_reg *reg);
212 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
213 int ti_clk_retry_init(struct device_node *node, void *user,
214 ti_of_clk_init_cb_t func);
215 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
217 void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
218 int of_ti_clk_autoidle_setup(struct device_node *node);
219 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
221 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
222 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
223 extern const struct clk_hw_omap_ops clkhwops_wait;
224 extern const struct clk_hw_omap_ops clkhwops_iclk;
225 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
226 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
227 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
228 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
229 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
230 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
231 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
232 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
234 extern const struct clk_ops ti_clk_divider_ops;
235 extern const struct clk_ops ti_clk_mux_ops;
236 extern const struct clk_ops omap_gate_clk_ops;
238 void omap2_init_clk_clkdm(struct clk_hw *hw);
239 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
240 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
242 int omap2_dflt_clk_enable(struct clk_hw *hw);
243 void omap2_dflt_clk_disable(struct clk_hw *hw);
244 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
245 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
246 struct clk_omap_reg *other_reg,
247 u8 *other_bit);
248 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
249 struct clk_omap_reg *idlest_reg,
250 u8 *idlest_bit, u8 *idlest_val);
252 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
253 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
255 u8 omap2_init_dpll_parent(struct clk_hw *hw);
256 int omap3_noncore_dpll_enable(struct clk_hw *hw);
257 void omap3_noncore_dpll_disable(struct clk_hw *hw);
258 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
259 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
260 unsigned long parent_rate);
261 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
262 unsigned long rate,
263 unsigned long parent_rate,
264 u8 index);
265 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
266 struct clk_rate_request *req);
267 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
268 unsigned long *parent_rate);
269 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
270 unsigned long parent_rate);
272 /*
273 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
274 * that are sourced by DPLL5, and both of these require this clock
275 * to be at 120 MHz for proper operation.
276 */
277 #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
279 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
280 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
281 unsigned long parent_rate);
282 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
283 unsigned long parent_rate, u8 index);
284 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
285 unsigned long parent_rate);
286 void omap3_clk_lock_dpll5(void);
288 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
289 unsigned long parent_rate);
290 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
291 unsigned long target_rate,
292 unsigned long *parent_rate);
293 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
294 struct clk_rate_request *req);
296 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
298 #endif