clk: ti: Add functions to save/restore clk context
[rpmsg/hwspinlock.git] / drivers / clk / ti / divider.c
1 /*
2  * TI Divider Clock
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * Tero Kristo <t-kristo@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
24 #include "clock.h"
26 #undef pr_fmt
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define div_mask(d)     ((1 << ((d)->width)) - 1)
31 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
32 {
33         unsigned int maxdiv = 0;
34         const struct clk_div_table *clkt;
36         for (clkt = table; clkt->div; clkt++)
37                 if (clkt->div > maxdiv)
38                         maxdiv = clkt->div;
39         return maxdiv;
40 }
42 static unsigned int _get_maxdiv(struct clk_omap_divider *divider)
43 {
44         if (divider->flags & CLK_DIVIDER_ONE_BASED)
45                 return div_mask(divider);
46         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
47                 return 1 << div_mask(divider);
48         if (divider->table)
49                 return _get_table_maxdiv(divider->table);
50         return div_mask(divider) + 1;
51 }
53 static unsigned int _get_table_div(const struct clk_div_table *table,
54                                    unsigned int val)
55 {
56         const struct clk_div_table *clkt;
58         for (clkt = table; clkt->div; clkt++)
59                 if (clkt->val == val)
60                         return clkt->div;
61         return 0;
62 }
64 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
65 {
66         if (divider->flags & CLK_DIVIDER_ONE_BASED)
67                 return val;
68         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
69                 return 1 << val;
70         if (divider->table)
71                 return _get_table_div(divider->table, val);
72         return val + 1;
73 }
75 static unsigned int _get_table_val(const struct clk_div_table *table,
76                                    unsigned int div)
77 {
78         const struct clk_div_table *clkt;
80         for (clkt = table; clkt->div; clkt++)
81                 if (clkt->div == div)
82                         return clkt->val;
83         return 0;
84 }
86 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
87 {
88         if (divider->flags & CLK_DIVIDER_ONE_BASED)
89                 return div;
90         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
91                 return __ffs(div);
92         if (divider->table)
93                 return  _get_table_val(divider->table, div);
94         return div - 1;
95 }
97 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
98                                                 unsigned long parent_rate)
99 {
100         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
101         unsigned int div, val;
103         val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
104         val &= div_mask(divider);
106         div = _get_div(divider, val);
107         if (!div) {
108                 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
109                      "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
110                      clk_hw_get_name(hw));
111                 return parent_rate;
112         }
114         return DIV_ROUND_UP(parent_rate, div);
117 /*
118  * The reverse of DIV_ROUND_UP: The maximum number which
119  * divided by m is r
120  */
121 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
123 static bool _is_valid_table_div(const struct clk_div_table *table,
124                                 unsigned int div)
126         const struct clk_div_table *clkt;
128         for (clkt = table; clkt->div; clkt++)
129                 if (clkt->div == div)
130                         return true;
131         return false;
134 static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
136         if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
137                 return is_power_of_2(div);
138         if (divider->table)
139                 return _is_valid_table_div(divider->table, div);
140         return true;
143 static int _div_round_up(const struct clk_div_table *table,
144                          unsigned long parent_rate, unsigned long rate)
146         const struct clk_div_table *clkt;
147         int up = INT_MAX;
148         int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
150         for (clkt = table; clkt->div; clkt++) {
151                 if (clkt->div == div)
152                         return clkt->div;
153                 else if (clkt->div < div)
154                         continue;
156                 if ((clkt->div - div) < (up - div))
157                         up = clkt->div;
158         }
160         return up;
163 static int _div_round(const struct clk_div_table *table,
164                       unsigned long parent_rate, unsigned long rate)
166         if (!table)
167                 return DIV_ROUND_UP(parent_rate, rate);
169         return _div_round_up(table, parent_rate, rate);
172 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
173                                   unsigned long *best_parent_rate)
175         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
176         int i, bestdiv = 0;
177         unsigned long parent_rate, best = 0, now, maxdiv;
178         unsigned long parent_rate_saved = *best_parent_rate;
180         if (!rate)
181                 rate = 1;
183         maxdiv = _get_maxdiv(divider);
185         if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
186                 parent_rate = *best_parent_rate;
187                 bestdiv = _div_round(divider->table, parent_rate, rate);
188                 bestdiv = bestdiv == 0 ? 1 : bestdiv;
189                 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
190                 return bestdiv;
191         }
193         /*
194          * The maximum divider we can use without overflowing
195          * unsigned long in rate * i below
196          */
197         maxdiv = min(ULONG_MAX / rate, maxdiv);
199         for (i = 1; i <= maxdiv; i++) {
200                 if (!_is_valid_div(divider, i))
201                         continue;
202                 if (rate * i == parent_rate_saved) {
203                         /*
204                          * It's the most ideal case if the requested rate can be
205                          * divided from parent clock without needing to change
206                          * parent rate, so return the divider immediately.
207                          */
208                         *best_parent_rate = parent_rate_saved;
209                         return i;
210                 }
211                 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
212                                 MULT_ROUND_UP(rate, i));
213                 now = DIV_ROUND_UP(parent_rate, i);
214                 if (now <= rate && now > best) {
215                         bestdiv = i;
216                         best = now;
217                         *best_parent_rate = parent_rate;
218                 }
219         }
221         if (!bestdiv) {
222                 bestdiv = _get_maxdiv(divider);
223                 *best_parent_rate =
224                         clk_hw_round_rate(clk_hw_get_parent(hw), 1);
225         }
227         return bestdiv;
230 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
231                                       unsigned long *prate)
233         int div;
234         div = ti_clk_divider_bestdiv(hw, rate, prate);
236         return DIV_ROUND_UP(*prate, div);
239 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
240                                    unsigned long parent_rate)
242         struct clk_omap_divider *divider;
243         unsigned int div, value;
244         u32 val;
246         if (!hw || !rate)
247                 return -EINVAL;
249         divider = to_clk_omap_divider(hw);
251         div = DIV_ROUND_UP(parent_rate, rate);
252         value = _get_val(divider, div);
254         if (value > div_mask(divider))
255                 value = div_mask(divider);
257         if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
258                 val = div_mask(divider) << (divider->shift + 16);
259         } else {
260                 val = ti_clk_ll_ops->clk_readl(&divider->reg);
261                 val &= ~(div_mask(divider) << divider->shift);
262         }
263         val |= value << divider->shift;
264         ti_clk_ll_ops->clk_writel(val, &divider->reg);
266         ti_clk_latch(&divider->reg, divider->latch);
268         return 0;
271 /**
272  * clk_divider_save_context - Save the divider value
273  * @hw: pointer  struct clk_hw
274  *
275  * Save the divider value
276  */
277 static int clk_divider_save_context(struct clk_hw *hw)
279         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
280         u32 val;
282         val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
283         divider->context = val & div_mask(divider);
285         return 0;
288 /**
289  * clk_divider_restore_context - restore the saved the divider value
290  * @hw: pointer  struct clk_hw
291  *
292  * Restore the saved the divider value
293  */
294 static void clk_divider_restore_context(struct clk_hw *hw)
296         struct clk_omap_divider *divider = to_clk_omap_divider(hw);
297         u32 val;
299         val = ti_clk_ll_ops->clk_readl(&divider->reg);
300         val &= ~(div_mask(divider) << divider->shift);
301         val |= divider->context << divider->shift;
302         ti_clk_ll_ops->clk_writel(val, &divider->reg);
305 const struct clk_ops ti_clk_divider_ops = {
306         .recalc_rate = ti_clk_divider_recalc_rate,
307         .round_rate = ti_clk_divider_round_rate,
308         .set_rate = ti_clk_divider_set_rate,
309         .save_context = clk_divider_save_context,
310         .restore_context = clk_divider_restore_context,
311 };
313 static struct clk *_register_divider(struct device *dev, const char *name,
314                                      const char *parent_name,
315                                      unsigned long flags,
316                                      struct clk_omap_reg *reg,
317                                      u8 shift, u8 width, s8 latch,
318                                      u8 clk_divider_flags,
319                                      const struct clk_div_table *table)
321         struct clk_omap_divider *div;
322         struct clk *clk;
323         struct clk_init_data init;
325         if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
326                 if (width + shift > 16) {
327                         pr_warn("divider value exceeds LOWORD field\n");
328                         return ERR_PTR(-EINVAL);
329                 }
330         }
332         /* allocate the divider */
333         div = kzalloc(sizeof(*div), GFP_KERNEL);
334         if (!div)
335                 return ERR_PTR(-ENOMEM);
337         init.name = name;
338         init.ops = &ti_clk_divider_ops;
339         init.flags = flags | CLK_IS_BASIC;
340         init.parent_names = (parent_name ? &parent_name : NULL);
341         init.num_parents = (parent_name ? 1 : 0);
343         /* struct clk_divider assignments */
344         memcpy(&div->reg, reg, sizeof(*reg));
345         div->shift = shift;
346         div->width = width;
347         div->latch = latch;
348         div->flags = clk_divider_flags;
349         div->hw.init = &init;
350         div->table = table;
352         /* register the clock */
353         clk = ti_clk_register(dev, &div->hw, name);
355         if (IS_ERR(clk))
356                 kfree(div);
358         return clk;
361 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
362                               u8 flags, u8 *width,
363                               const struct clk_div_table **table)
365         int valid_div = 0;
366         u32 val;
367         int div;
368         int i;
369         struct clk_div_table *tmp;
371         if (!div_table) {
372                 if (flags & CLKF_INDEX_STARTS_AT_ONE)
373                         val = 1;
374                 else
375                         val = 0;
377                 div = 1;
379                 while (div < max_div) {
380                         if (flags & CLKF_INDEX_POWER_OF_TWO)
381                                 div <<= 1;
382                         else
383                                 div++;
384                         val++;
385                 }
387                 *width = fls(val);
388                 *table = NULL;
390                 return 0;
391         }
393         i = 0;
395         while (!num_dividers || i < num_dividers) {
396                 if (div_table[i] == -1)
397                         break;
398                 if (div_table[i])
399                         valid_div++;
400                 i++;
401         }
403         num_dividers = i;
405         tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
406         if (!tmp)
407                 return -ENOMEM;
409         valid_div = 0;
410         *width = 0;
412         for (i = 0; i < num_dividers; i++)
413                 if (div_table[i] > 0) {
414                         tmp[valid_div].div = div_table[i];
415                         tmp[valid_div].val = i;
416                         valid_div++;
417                         *width = i;
418                 }
420         *width = fls(*width);
421         *table = tmp;
423         return 0;
426 static const struct clk_div_table *
427 _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
429         const struct clk_div_table *table = NULL;
431         ti_clk_parse_divider_data(setup->dividers, setup->num_dividers,
432                                   setup->max_div, setup->flags, width,
433                                   &table);
435         return table;
438 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
440         struct clk_omap_divider *div;
441         struct clk_omap_reg *reg;
443         if (!setup)
444                 return NULL;
446         div = kzalloc(sizeof(*div), GFP_KERNEL);
447         if (!div)
448                 return ERR_PTR(-ENOMEM);
450         reg = (struct clk_omap_reg *)&div->reg;
451         reg->index = setup->module;
452         reg->offset = setup->reg;
454         if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
455                 div->flags |= CLK_DIVIDER_ONE_BASED;
457         if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
458                 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
460         div->table = _get_div_table_from_setup(setup, &div->width);
462         div->shift = setup->bit_shift;
463         div->latch = -EINVAL;
465         return &div->hw;
468 struct clk *ti_clk_register_divider(struct ti_clk *setup)
470         struct ti_clk_divider *div = setup->data;
471         struct clk_omap_reg reg = {
472                 .index = div->module,
473                 .offset = div->reg,
474         };
475         u8 width;
476         u32 flags = 0;
477         u8 div_flags = 0;
478         const struct clk_div_table *table;
479         struct clk *clk;
481         if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
482                 div_flags |= CLK_DIVIDER_ONE_BASED;
484         if (div->flags & CLKF_INDEX_POWER_OF_TWO)
485                 div_flags |= CLK_DIVIDER_POWER_OF_TWO;
487         if (div->flags & CLKF_SET_RATE_PARENT)
488                 flags |= CLK_SET_RATE_PARENT;
490         table = _get_div_table_from_setup(div, &width);
491         if (IS_ERR(table))
492                 return (struct clk *)table;
494         clk = _register_divider(NULL, setup->name, div->parent,
495                                 flags, &reg, div->bit_shift,
496                                 width, -EINVAL, div_flags, table);
498         if (IS_ERR(clk))
499                 kfree(table);
501         return clk;
504 static struct clk_div_table *
505 __init ti_clk_get_div_table(struct device_node *node)
507         struct clk_div_table *table;
508         const __be32 *divspec;
509         u32 val;
510         u32 num_div;
511         u32 valid_div;
512         int i;
514         divspec = of_get_property(node, "ti,dividers", &num_div);
516         if (!divspec)
517                 return NULL;
519         num_div /= 4;
521         valid_div = 0;
523         /* Determine required size for divider table */
524         for (i = 0; i < num_div; i++) {
525                 of_property_read_u32_index(node, "ti,dividers", i, &val);
526                 if (val)
527                         valid_div++;
528         }
530         if (!valid_div) {
531                 pr_err("no valid dividers for %s table\n", node->name);
532                 return ERR_PTR(-EINVAL);
533         }
535         table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
537         if (!table)
538                 return ERR_PTR(-ENOMEM);
540         valid_div = 0;
542         for (i = 0; i < num_div; i++) {
543                 of_property_read_u32_index(node, "ti,dividers", i, &val);
544                 if (val) {
545                         table[valid_div].div = val;
546                         table[valid_div].val = i;
547                         valid_div++;
548                 }
549         }
551         return table;
554 static int _get_divider_width(struct device_node *node,
555                               const struct clk_div_table *table,
556                               u8 flags)
558         u32 min_div;
559         u32 max_div;
560         u32 val = 0;
561         u32 div;
563         if (!table) {
564                 /* Clk divider table not provided, determine min/max divs */
565                 if (of_property_read_u32(node, "ti,min-div", &min_div))
566                         min_div = 1;
568                 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
569                         pr_err("no max-div for %s!\n", node->name);
570                         return -EINVAL;
571                 }
573                 /* Determine bit width for the field */
574                 if (flags & CLK_DIVIDER_ONE_BASED)
575                         val = 1;
577                 div = min_div;
579                 while (div < max_div) {
580                         if (flags & CLK_DIVIDER_POWER_OF_TWO)
581                                 div <<= 1;
582                         else
583                                 div++;
584                         val++;
585                 }
586         } else {
587                 div = 0;
589                 while (table[div].div) {
590                         val = table[div].val;
591                         div++;
592                 }
593         }
595         return fls(val);
598 static int __init ti_clk_divider_populate(struct device_node *node,
599         struct clk_omap_reg *reg, const struct clk_div_table **table,
600         u32 *flags, u8 *div_flags, u8 *width, u8 *shift, s8 *latch)
602         u32 val;
603         int ret;
605         ret = ti_clk_get_reg_addr(node, 0, reg);
606         if (ret)
607                 return ret;
609         if (!of_property_read_u32(node, "ti,bit-shift", &val))
610                 *shift = val;
611         else
612                 *shift = 0;
614         if (latch) {
615                 if (!of_property_read_u32(node, "ti,latch-bit", &val))
616                         *latch = val;
617                 else
618                         *latch = -EINVAL;
619         }
621         *flags = 0;
622         *div_flags = 0;
624         if (of_property_read_bool(node, "ti,index-starts-at-one"))
625                 *div_flags |= CLK_DIVIDER_ONE_BASED;
627         if (of_property_read_bool(node, "ti,index-power-of-two"))
628                 *div_flags |= CLK_DIVIDER_POWER_OF_TWO;
630         if (of_property_read_bool(node, "ti,set-rate-parent"))
631                 *flags |= CLK_SET_RATE_PARENT;
633         *table = ti_clk_get_div_table(node);
635         if (IS_ERR(*table))
636                 return PTR_ERR(*table);
638         *width = _get_divider_width(node, *table, *div_flags);
640         return 0;
643 /**
644  * of_ti_divider_clk_setup - Setup function for simple div rate clock
645  * @node: device node for this clock
646  *
647  * Sets up a basic divider clock.
648  */
649 static void __init of_ti_divider_clk_setup(struct device_node *node)
651         struct clk *clk;
652         const char *parent_name;
653         struct clk_omap_reg reg;
654         u8 clk_divider_flags = 0;
655         u8 width = 0;
656         u8 shift = 0;
657         s8 latch = -EINVAL;
658         const struct clk_div_table *table = NULL;
659         u32 flags = 0;
661         parent_name = of_clk_get_parent_name(node, 0);
663         if (ti_clk_divider_populate(node, &reg, &table, &flags,
664                                     &clk_divider_flags, &width, &shift, &latch))
665                 goto cleanup;
667         clk = _register_divider(NULL, node->name, parent_name, flags, &reg,
668                                 shift, width, latch, clk_divider_flags, table);
670         if (!IS_ERR(clk)) {
671                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
672                 of_ti_clk_autoidle_setup(node);
673                 return;
674         }
676 cleanup:
677         kfree(table);
679 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
681 static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
683         struct clk_omap_divider *div;
684         u32 val;
686         div = kzalloc(sizeof(*div), GFP_KERNEL);
687         if (!div)
688                 return;
690         if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
691                                     &div->flags, &div->width, &div->shift,
692                                     NULL) < 0)
693                 goto cleanup;
695         if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
696                 return;
698 cleanup:
699         kfree(div->table);
700         kfree(div);
702 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
703                of_ti_composite_divider_clk_setup);