clk: ti: Add functions to save/restore clk context
[rpmsg/hwspinlock.git] / drivers / clk / ti / gate.c
1 /*
2  * OMAP gate clock support
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * Tero Kristo <t-kristo@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
25 #include "clock.h"
27 #undef pr_fmt
28 #define pr_fmt(fmt) "%s: " fmt, __func__
30 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
32 static const struct clk_ops omap_gate_clkdm_clk_ops = {
33         .init           = &omap2_init_clk_clkdm,
34         .enable         = &omap2_clkops_enable_clkdm,
35         .disable        = &omap2_clkops_disable_clkdm,
36         .restore_context = clk_gate_restore_context,
37 };
39 const struct clk_ops omap_gate_clk_ops = {
40         .init           = &omap2_init_clk_clkdm,
41         .enable         = &omap2_dflt_clk_enable,
42         .disable        = &omap2_dflt_clk_disable,
43         .is_enabled     = &omap2_dflt_clk_is_enabled,
44         .restore_context = clk_gate_restore_context,
45 };
47 static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
48         .init           = &omap2_init_clk_clkdm,
49         .enable         = &omap36xx_gate_clk_enable_with_hsdiv_restore,
50         .disable        = &omap2_dflt_clk_disable,
51         .is_enabled     = &omap2_dflt_clk_is_enabled,
52         .restore_context = clk_gate_restore_context,
53 };
55 /**
56  * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
57  *         from HSDivider PWRDN problem Implements Errata ID: i556.
58  * @clk: DPLL output struct clk
59  *
60  * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
61  * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
62  * valueafter their respective PWRDN bits are set.  Any dummy write
63  * (Any other value different from the Read value) to the
64  * corresponding CM_CLKSEL register will refresh the dividers.
65  */
66 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
67 {
68         struct clk_omap_divider *parent;
69         struct clk_hw *parent_hw;
70         u32 dummy_v, orig_v;
71         int ret;
73         /* Clear PWRDN bit of HSDIVIDER */
74         ret = omap2_dflt_clk_enable(hw);
76         /* Parent is the x2 node, get parent of parent for the m2 div */
77         parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
78         parent = to_clk_omap_divider(parent_hw);
80         /* Restore the dividers */
81         if (!ret) {
82                 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
83                 dummy_v = orig_v;
85                 /* Write any other value different from the Read value */
86                 dummy_v ^= (1 << parent->shift);
87                 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
89                 /* Write the original divider */
90                 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
91         }
93         return ret;
94 }
96 static struct clk *_register_gate(struct device *dev, const char *name,
97                                   const char *parent_name, unsigned long flags,
98                                   struct clk_omap_reg *reg, u8 bit_idx,
99                                   u8 clk_gate_flags, const struct clk_ops *ops,
100                                   const struct clk_hw_omap_ops *hw_ops)
102         struct clk_init_data init = { NULL };
103         struct clk_hw_omap *clk_hw;
104         struct clk *clk;
106         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
107         if (!clk_hw)
108                 return ERR_PTR(-ENOMEM);
110         clk_hw->hw.init = &init;
112         init.name = name;
113         init.ops = ops;
115         memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
116         clk_hw->enable_bit = bit_idx;
117         clk_hw->ops = hw_ops;
119         clk_hw->flags = clk_gate_flags;
121         init.parent_names = &parent_name;
122         init.num_parents = 1;
124         init.flags = flags;
126         clk = ti_clk_register(NULL, &clk_hw->hw, name);
128         if (IS_ERR(clk))
129                 kfree(clk_hw);
131         return clk;
134 struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
136         struct clk_hw_omap *gate;
137         struct clk_omap_reg *reg;
138         const struct clk_hw_omap_ops *ops = &clkhwops_wait;
140         if (!setup)
141                 return NULL;
143         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
144         if (!gate)
145                 return ERR_PTR(-ENOMEM);
147         reg = (struct clk_omap_reg *)&gate->enable_reg;
148         reg->index = setup->module;
149         reg->offset = setup->reg;
151         gate->enable_bit = setup->bit_shift;
153         if (setup->flags & CLKF_NO_WAIT)
154                 ops = NULL;
156         if (setup->flags & CLKF_INTERFACE)
157                 ops = &clkhwops_iclk_wait;
159         gate->ops = ops;
161         return &gate->hw;
164 static void __init _of_ti_gate_clk_setup(struct device_node *node,
165                                          const struct clk_ops *ops,
166                                          const struct clk_hw_omap_ops *hw_ops)
168         struct clk *clk;
169         const char *parent_name;
170         struct clk_omap_reg reg;
171         u8 enable_bit = 0;
172         u32 val;
173         u32 flags = 0;
174         u8 clk_gate_flags = 0;
176         if (ops != &omap_gate_clkdm_clk_ops) {
177                 if (ti_clk_get_reg_addr(node, 0, &reg))
178                         return;
180                 if (!of_property_read_u32(node, "ti,bit-shift", &val))
181                         enable_bit = val;
182         }
184         if (of_clk_get_parent_count(node) != 1) {
185                 pr_err("%s must have 1 parent\n", node->name);
186                 return;
187         }
189         parent_name = of_clk_get_parent_name(node, 0);
191         if (of_property_read_bool(node, "ti,set-rate-parent"))
192                 flags |= CLK_SET_RATE_PARENT;
194         if (of_property_read_bool(node, "ti,set-bit-to-disable"))
195                 clk_gate_flags |= INVERT_ENABLE;
197         clk = _register_gate(NULL, node->name, parent_name, flags, &reg,
198                              enable_bit, clk_gate_flags, ops, hw_ops);
200         if (!IS_ERR(clk))
201                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
204 static void __init
205 _of_ti_composite_gate_clk_setup(struct device_node *node,
206                                 const struct clk_hw_omap_ops *hw_ops)
208         struct clk_hw_omap *gate;
209         u32 val = 0;
211         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
212         if (!gate)
213                 return;
215         if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
216                 goto cleanup;
218         of_property_read_u32(node, "ti,bit-shift", &val);
220         gate->enable_bit = val;
221         gate->ops = hw_ops;
223         if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
224                 return;
226 cleanup:
227         kfree(gate);
230 static void __init
231 of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
233         _of_ti_composite_gate_clk_setup(node, NULL);
235 CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
236                of_ti_composite_no_wait_gate_clk_setup);
238 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
239 static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
241         _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
243 CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
244                of_ti_composite_interface_clk_setup);
245 #endif
247 static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
249         _of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
251 CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
252                of_ti_composite_gate_clk_setup);
255 static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
257         _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
259 CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
260                of_ti_clkdm_gate_clk_setup);
262 static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
264         _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
265                               &clkhwops_wait);
267 CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
268                of_ti_hsdiv_gate_clk_setup);
270 static void __init of_ti_gate_clk_setup(struct device_node *node)
272         _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
274 CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
276 static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
278         _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
280 CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
281                of_ti_wait_gate_clk_setup);
283 #ifdef CONFIG_ARCH_OMAP3
284 static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
286         _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
287                               &clkhwops_am35xx_ipss_module_wait);
289 CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
290                of_ti_am35xx_gate_clk_setup);
292 static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
294         _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
295                               &clkhwops_omap3430es2_dss_usbhost_wait);
297 CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
298                of_ti_dss_gate_clk_setup);
299 #endif