rtc: omap: Cut down the shutdown time from 2 seconds to 1 sec
[rpmsg/hwspinlock.git] / drivers / rtc / rtc-omap.c
1 /*
2  * TI OMAP Real Time Clock interface for Linux
3  *
4  * Copyright (C) 2003 MontaVista Software, Inc.
5  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
6  *
7  * Copyright (C) 2006 David Brownell (new RTC framework)
8  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version
13  * 2 of the License, or (at your option) any later version.
14  */
16 #include <dt-bindings/gpio/gpio.h>
17 #include <linux/bcd.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/rtc.h>
34 /*
35  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
36  * with century-range alarm matching, driven by the 32kHz clock.
37  *
38  * The main user-visible ways it differs from PC RTCs are by omitting
39  * "don't care" alarm fields and sub-second periodic IRQs, and having
40  * an autoadjust mechanism to calibrate to the true oscillator rate.
41  *
42  * Board-specific wiring options include using split power mode with
43  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
44  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
45  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
46  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
47  */
49 /* RTC registers */
50 #define OMAP_RTC_SECONDS_REG            0x00
51 #define OMAP_RTC_MINUTES_REG            0x04
52 #define OMAP_RTC_HOURS_REG              0x08
53 #define OMAP_RTC_DAYS_REG               0x0C
54 #define OMAP_RTC_MONTHS_REG             0x10
55 #define OMAP_RTC_YEARS_REG              0x14
56 #define OMAP_RTC_WEEKS_REG              0x18
58 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
59 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
60 #define OMAP_RTC_ALARM_HOURS_REG        0x28
61 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
62 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
63 #define OMAP_RTC_ALARM_YEARS_REG        0x34
65 #define OMAP_RTC_CTRL_REG               0x40
66 #define OMAP_RTC_STATUS_REG             0x44
67 #define OMAP_RTC_INTERRUPTS_REG         0x48
69 #define OMAP_RTC_COMP_LSB_REG           0x4c
70 #define OMAP_RTC_COMP_MSB_REG           0x50
71 #define OMAP_RTC_OSC_REG                0x54
73 #define OMAP_RTC_SCRATCH0_REG           0x60
74 #define OMAP_RTC_SCRATCH1_REG           0x64
75 #define OMAP_RTC_SCRATCH2_REG           0x68
77 #define OMAP_RTC_KICK0_REG              0x6c
78 #define OMAP_RTC_KICK1_REG              0x70
80 #define OMAP_RTC_IRQWAKEEN              0x7c
82 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
83 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
84 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
85 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
86 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
87 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
89 #define OMAP_RTC_PMIC_REG               0x98
91 /* OMAP_RTC_CTRL_REG bit fields: */
92 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
93 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
94 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
95 #define OMAP_RTC_CTRL_TEST              BIT(4)
96 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
97 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
98 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
99 #define OMAP_RTC_CTRL_STOP              BIT(0)
101 /* OMAP_RTC_STATUS_REG bit fields: */
102 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
103 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
104 #define OMAP_RTC_STATUS_ALARM           BIT(6)
105 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
106 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
107 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
108 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
109 #define OMAP_RTC_STATUS_RUN             BIT(1)
110 #define OMAP_RTC_STATUS_BUSY            BIT(0)
112 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
113 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
114 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
115 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
117 /* OMAP_RTC_OSC_REG bit fields: */
118 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
119 #define OMAP_RTC_OSC_SEL_32KCLK_SRC     BIT(3)
120 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE  BIT(4)
122 /* OMAP_RTC_IRQWAKEEN bit fields: */
123 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
125 /* OMAP_RTC_PMIC bit fields: */
126 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
127 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x)    BIT(x)
128 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x)   BIT(4 + x)
130 /* OMAP_RTC_KICKER values */
131 #define KICK0_VALUE                     0x83e70b13
132 #define KICK1_VALUE                     0x95a4f1e0
134 struct omap_rtc;
136 struct omap_rtc_device_type {
137         bool has_32kclk_en;
138         bool has_irqwakeen;
139         bool has_pmic_mode;
140         bool has_power_up_reset;
141         void (*lock)(struct omap_rtc *rtc);
142         void (*unlock)(struct omap_rtc *rtc);
143 };
145 struct omap_rtc {
146         struct rtc_device *rtc;
147         void __iomem *base;
148         struct clk *clk;
149         int irq_alarm;
150         int irq_timer;
151         u8 interrupts_reg;
152         bool is_pmic_controller;
153         bool has_ext_clk;
154         bool is_suspending;
155         const struct omap_rtc_device_type *type;
156         struct pinctrl_dev *pctldev;
157 };
159 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
161         return readb(rtc->base + reg);
164 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
166         return readl(rtc->base + reg);
169 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
171         writeb(val, rtc->base + reg);
174 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
176         writel(val, rtc->base + reg);
179 static void am3352_rtc_unlock(struct omap_rtc *rtc)
181         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
182         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
185 static void am3352_rtc_lock(struct omap_rtc *rtc)
187         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
188         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
191 static void default_rtc_unlock(struct omap_rtc *rtc)
195 static void default_rtc_lock(struct omap_rtc *rtc)
199 /*
200  * We rely on the rtc framework to handle locking (rtc->ops_lock),
201  * so the only other requirement is that register accesses which
202  * require BUSY to be clear are made with IRQs locally disabled
203  */
204 static void rtc_wait_not_busy(struct omap_rtc *rtc)
206         int count;
207         u8 status;
209         /* BUSY may stay active for 1/32768 second (~30 usec) */
210         for (count = 0; count < 50; count++) {
211                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
212                 if (!(status & OMAP_RTC_STATUS_BUSY))
213                         break;
214                 udelay(1);
215         }
216         /* now we have ~15 usec to read/write various registers */
219 static irqreturn_t rtc_irq(int irq, void *dev_id)
221         struct omap_rtc *rtc = dev_id;
222         unsigned long events = 0;
223         u8 irq_data;
225         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
227         /* alarm irq? */
228         if (irq_data & OMAP_RTC_STATUS_ALARM) {
229                 rtc->type->unlock(rtc);
230                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
231                 rtc->type->lock(rtc);
232                 events |= RTC_IRQF | RTC_AF;
233         }
235         /* 1/sec periodic/update irq? */
236         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
237                 events |= RTC_IRQF | RTC_UF;
239         rtc_update_irq(rtc->rtc, 1, events);
241         return IRQ_HANDLED;
244 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
246         struct omap_rtc *rtc = dev_get_drvdata(dev);
247         u8 reg, irqwake_reg = 0;
249         local_irq_disable();
250         rtc_wait_not_busy(rtc);
251         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
252         if (rtc->type->has_irqwakeen)
253                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
255         if (enabled) {
256                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
257                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
258         } else {
259                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
260                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
261         }
262         rtc_wait_not_busy(rtc);
263         rtc->type->unlock(rtc);
264         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
265         if (rtc->type->has_irqwakeen)
266                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
267         rtc->type->lock(rtc);
268         local_irq_enable();
270         return 0;
273 /* this hardware doesn't support "don't care" alarm fields */
274 static int tm2bcd(struct rtc_time *tm)
276         tm->tm_sec = bin2bcd(tm->tm_sec);
277         tm->tm_min = bin2bcd(tm->tm_min);
278         tm->tm_hour = bin2bcd(tm->tm_hour);
279         tm->tm_mday = bin2bcd(tm->tm_mday);
281         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
283         /* epoch == 1900 */
284         if (tm->tm_year < 100 || tm->tm_year > 199)
285                 return -EINVAL;
286         tm->tm_year = bin2bcd(tm->tm_year - 100);
288         return 0;
291 static void bcd2tm(struct rtc_time *tm)
293         tm->tm_sec = bcd2bin(tm->tm_sec);
294         tm->tm_min = bcd2bin(tm->tm_min);
295         tm->tm_hour = bcd2bin(tm->tm_hour);
296         tm->tm_mday = bcd2bin(tm->tm_mday);
297         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
298         /* epoch == 1900 */
299         tm->tm_year = bcd2bin(tm->tm_year) + 100;
302 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
304         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
305         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
306         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
307         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
308         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
309         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
312 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
314         struct omap_rtc *rtc = dev_get_drvdata(dev);
316         /* we don't report wday/yday/isdst ... */
317         local_irq_disable();
318         rtc_wait_not_busy(rtc);
319         omap_rtc_read_time_raw(rtc, tm);
320         local_irq_enable();
322         bcd2tm(tm);
324         return 0;
327 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
329         struct omap_rtc *rtc = dev_get_drvdata(dev);
331         if (tm2bcd(tm) < 0)
332                 return -EINVAL;
334         local_irq_disable();
335         rtc_wait_not_busy(rtc);
337         rtc->type->unlock(rtc);
338         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
339         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
340         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
341         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
342         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
343         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
344         rtc->type->lock(rtc);
346         local_irq_enable();
348         return 0;
351 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
353         struct omap_rtc *rtc = dev_get_drvdata(dev);
354         u8 interrupts;
356         local_irq_disable();
357         rtc_wait_not_busy(rtc);
359         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
360         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
361         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
362         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
363         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
364         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
366         local_irq_enable();
368         bcd2tm(&alm->time);
370         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
371         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
373         return 0;
376 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
378         struct omap_rtc *rtc = dev_get_drvdata(dev);
379         u8 reg, irqwake_reg = 0;
381         if (tm2bcd(&alm->time) < 0)
382                 return -EINVAL;
384         local_irq_disable();
385         rtc_wait_not_busy(rtc);
387         rtc->type->unlock(rtc);
388         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
389         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
390         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
391         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
392         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
393         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
395         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
396         if (rtc->type->has_irqwakeen)
397                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
399         if (alm->enabled) {
400                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
401                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
402         } else {
403                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
404                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
405         }
406         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
407         if (rtc->type->has_irqwakeen)
408                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
409         rtc->type->lock(rtc);
411         local_irq_enable();
413         return 0;
416 static struct omap_rtc *omap_rtc_power_off_rtc;
418 /*
419  * omap_rtc_poweroff: RTC-controlled power off
420  *
421  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
422  * which can be configured to transition to OFF on ALARM2 events.
423  *
424  * Called with local interrupts disabled.
425  */
426 static void omap_rtc_power_off(void)
428         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
429         struct rtc_time tm;
430         unsigned long now;
431         int seconds;
432         u32 val;
434         rtc->type->unlock(rtc);
435         /* enable pmic_power_en control */
436         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
437         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
439 again:
440         /* set alarm one second from now */
441         omap_rtc_read_time_raw(rtc, &tm);
442         seconds = tm.tm_sec;
443         bcd2tm(&tm);
444         rtc_tm_to_time(&tm, &now);
445         rtc_time_to_tm(now + 1, &tm);
447         if (tm2bcd(&tm) < 0) {
448                 dev_err(&rtc->rtc->dev, "power off failed\n");
449                 rtc->type->lock(rtc);
450                 return;
451         }
453         rtc_wait_not_busy(rtc);
455         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
456         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
457         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
458         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
459         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
460         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
462         /*
463          * enable ALARM2 interrupt
464          *
465          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
466          */
467         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
468         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
469                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
471         /* Retry in case roll over happened before alarm was armed. */
472         if (rtc_read(rtc, OMAP_RTC_SECONDS_REG) != seconds) {
473                 val = rtc_read(rtc, OMAP_RTC_STATUS_REG);
474                 if (!(val & OMAP_RTC_STATUS_ALARM2))
475                         goto again;
476         }
478         rtc->type->lock(rtc);
480         /*
481          * Wait for alarm to trigger (within one second) and external PMIC to
482          * power off the system. Add a 500 ms margin for external latencies
483          * (e.g. debounce circuits).
484          */
485         mdelay(1500);
488 static const struct rtc_class_ops omap_rtc_ops = {
489         .read_time      = omap_rtc_read_time,
490         .set_time       = omap_rtc_set_time,
491         .read_alarm     = omap_rtc_read_alarm,
492         .set_alarm      = omap_rtc_set_alarm,
493         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
494 };
496 static const struct omap_rtc_device_type omap_rtc_default_type = {
497         .has_power_up_reset = true,
498         .lock           = default_rtc_lock,
499         .unlock         = default_rtc_unlock,
500 };
502 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
503         .has_32kclk_en  = true,
504         .has_irqwakeen  = true,
505         .has_pmic_mode  = true,
506         .lock           = am3352_rtc_lock,
507         .unlock         = am3352_rtc_unlock,
508 };
510 static const struct omap_rtc_device_type omap_rtc_da830_type = {
511         .lock           = am3352_rtc_lock,
512         .unlock         = am3352_rtc_unlock,
513 };
515 static const struct platform_device_id omap_rtc_id_table[] = {
516         {
517                 .name   = "omap_rtc",
518                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
519         }, {
520                 .name   = "am3352-rtc",
521                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
522         }, {
523                 .name   = "da830-rtc",
524                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
525         }, {
526                 /* sentinel */
527         }
528 };
529 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
531 static const struct of_device_id omap_rtc_of_match[] = {
532         {
533                 .compatible     = "ti,am3352-rtc",
534                 .data           = &omap_rtc_am3352_type,
535         }, {
536                 .compatible     = "ti,da830-rtc",
537                 .data           = &omap_rtc_da830_type,
538         }, {
539                 /* sentinel */
540         }
541 };
542 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
544 static const struct pinctrl_pin_desc rtc_pins_desc[] = {
545         PINCTRL_PIN(0, "ext_wakeup0"),
546         PINCTRL_PIN(1, "ext_wakeup1"),
547         PINCTRL_PIN(2, "ext_wakeup2"),
548         PINCTRL_PIN(3, "ext_wakeup3"),
549 };
551 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
553         return 0;
556 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
557                                         unsigned int group)
559         return NULL;
562 static const struct pinctrl_ops rtc_pinctrl_ops = {
563         .get_groups_count = rtc_pinctrl_get_groups_count,
564         .get_group_name = rtc_pinctrl_get_group_name,
565         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
566         .dt_free_map = pinconf_generic_dt_free_map,
567 };
569 enum rtc_pin_config_param {
570         PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1,
571 };
573 static const struct pinconf_generic_params rtc_params[] = {
574         {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
575 };
577 #ifdef CONFIG_DEBUG_FS
578 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
579         PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
580 };
581 #endif
583 static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
584                         unsigned int pin, unsigned long *config)
586         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
587         unsigned int param = pinconf_to_config_param(*config);
588         u32 val;
589         u16 arg = 0;
591         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
593         switch (param) {
594         case PIN_CONFIG_INPUT_ENABLE:
595                 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
596                         return -EINVAL;
597                 break;
598         case PIN_CONFIG_ACTIVE_HIGH:
599                 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
600                         return -EINVAL;
601                 break;
602         default:
603                 return -ENOTSUPP;
604         };
606         *config = pinconf_to_config_packed(param, arg);
608         return 0;
611 static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
612                         unsigned int pin, unsigned long *configs,
613                         unsigned int num_configs)
615         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
616         u32 val;
617         unsigned int param;
618         u32 param_val;
619         int i;
621         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
623         /* active low by default */
624         val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
626         for (i = 0; i < num_configs; i++) {
627                 param = pinconf_to_config_param(configs[i]);
628                 param_val = pinconf_to_config_argument(configs[i]);
630                 switch (param) {
631                 case PIN_CONFIG_INPUT_ENABLE:
632                         if (param_val)
633                                 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
634                         else
635                                 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
636                         break;
637                 case PIN_CONFIG_ACTIVE_HIGH:
638                         val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
639                         break;
640                 default:
641                         dev_err(&rtc->rtc->dev, "Property %u not supported\n",
642                                 param);
643                         return -ENOTSUPP;
644                 }
645         }
647         rtc->type->unlock(rtc);
648         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
649         rtc->type->lock(rtc);
651         return 0;
654 static const struct pinconf_ops rtc_pinconf_ops = {
655         .is_generic = true,
656         .pin_config_get = rtc_pinconf_get,
657         .pin_config_set = rtc_pinconf_set,
658 };
660 static struct pinctrl_desc rtc_pinctrl_desc = {
661         .pins = rtc_pins_desc,
662         .npins = ARRAY_SIZE(rtc_pins_desc),
663         .pctlops = &rtc_pinctrl_ops,
664         .confops = &rtc_pinconf_ops,
665         .custom_params = rtc_params,
666         .num_custom_params = ARRAY_SIZE(rtc_params),
667 #ifdef CONFIG_DEBUG_FS
668         .custom_conf_items = rtc_conf_items,
669 #endif
670         .owner = THIS_MODULE,
671 };
673 static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
674                                  size_t bytes)
676         struct omap_rtc *rtc = priv;
677         u32 *val = _val;
678         int i;
680         for (i = 0; i < bytes / 4; i++)
681                 val[i] = rtc_readl(rtc,
682                                    OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
684         return 0;
687 static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
688                                   size_t bytes)
690         struct omap_rtc *rtc = priv;
691         u32 *val = _val;
692         int i;
694         rtc->type->unlock(rtc);
695         for (i = 0; i < bytes / 4; i++)
696                 rtc_writel(rtc,
697                            OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
698         rtc->type->lock(rtc);
700         return 0;
703 static struct nvmem_config omap_rtc_nvmem_config = {
704         .name = "omap_rtc_scratch",
705         .word_size = 4,
706         .stride = 4,
707         .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
708         .reg_read = omap_rtc_scratch_read,
709         .reg_write = omap_rtc_scratch_write,
710 };
712 static int omap_rtc_probe(struct platform_device *pdev)
714         struct omap_rtc *rtc;
715         struct resource *res;
716         u8 reg, mask, new_ctrl;
717         const struct platform_device_id *id_entry;
718         const struct of_device_id *of_id;
719         int ret;
721         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
722         if (!rtc)
723                 return -ENOMEM;
725         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
726         if (of_id) {
727                 rtc->type = of_id->data;
728                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
729                         of_device_is_system_power_controller(pdev->dev.of_node);
730         } else {
731                 id_entry = platform_get_device_id(pdev);
732                 rtc->type = (void *)id_entry->driver_data;
733         }
735         rtc->irq_timer = platform_get_irq(pdev, 0);
736         if (rtc->irq_timer <= 0)
737                 return -ENOENT;
739         rtc->irq_alarm = platform_get_irq(pdev, 1);
740         if (rtc->irq_alarm <= 0)
741                 return -ENOENT;
743         rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
744         if (!IS_ERR(rtc->clk))
745                 rtc->has_ext_clk = true;
746         else
747                 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
749         if (!IS_ERR(rtc->clk))
750                 clk_prepare_enable(rtc->clk);
752         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
753         rtc->base = devm_ioremap_resource(&pdev->dev, res);
754         if (IS_ERR(rtc->base)) {
755                 clk_disable_unprepare(rtc->clk);
756                 return PTR_ERR(rtc->base);
757         }
759         platform_set_drvdata(pdev, rtc);
761         /* Enable the clock/module so that we can access the registers */
762         pm_runtime_enable(&pdev->dev);
763         pm_runtime_get_sync(&pdev->dev);
765         rtc->type->unlock(rtc);
767         /*
768          * disable interrupts
769          *
770          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
771          */
772         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
774         /* enable RTC functional clock */
775         if (rtc->type->has_32kclk_en) {
776                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
777                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
778                                 reg | OMAP_RTC_OSC_32KCLK_EN);
779         }
781         /* clear old status */
782         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
784         mask = OMAP_RTC_STATUS_ALARM;
786         if (rtc->type->has_pmic_mode)
787                 mask |= OMAP_RTC_STATUS_ALARM2;
789         if (rtc->type->has_power_up_reset) {
790                 mask |= OMAP_RTC_STATUS_POWER_UP;
791                 if (reg & OMAP_RTC_STATUS_POWER_UP)
792                         dev_info(&pdev->dev, "RTC power up reset detected\n");
793         }
795         if (reg & mask)
796                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
798         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
799         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
800         if (reg & OMAP_RTC_CTRL_STOP)
801                 dev_info(&pdev->dev, "already running\n");
803         /* force to 24 hour mode */
804         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
805         new_ctrl |= OMAP_RTC_CTRL_STOP;
807         /*
808          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
809          *
810          *  - Device wake-up capability setting should come through chip
811          *    init logic. OMAP1 boards should initialize the "wakeup capable"
812          *    flag in the platform device if the board is wired right for
813          *    being woken up by RTC alarm. For OMAP-L138, this capability
814          *    is built into the SoC by the "Deep Sleep" capability.
815          *
816          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
817          *    rather than nPWRON_RESET, should forcibly enable split
818          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
819          *    is write-only, and always reads as zero...)
820          */
822         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
823                 dev_info(&pdev->dev, "split power mode\n");
825         if (reg != new_ctrl)
826                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
828         /*
829          * If we have the external clock then switch to it so we can keep
830          * ticking across suspend.
831          */
832         if (rtc->has_ext_clk) {
833                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
834                 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
835                 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
836                 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
837         }
839         rtc->type->lock(rtc);
841         device_init_wakeup(&pdev->dev, true);
843         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
844         if (IS_ERR(rtc->rtc)) {
845                 ret = PTR_ERR(rtc->rtc);
846                 goto err;
847         }
849         rtc->rtc->ops = &omap_rtc_ops;
850         omap_rtc_nvmem_config.priv = rtc;
852         /* handle periodic and alarm irqs */
853         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
854                         dev_name(&rtc->rtc->dev), rtc);
855         if (ret)
856                 goto err;
858         if (rtc->irq_timer != rtc->irq_alarm) {
859                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
860                                 dev_name(&rtc->rtc->dev), rtc);
861                 if (ret)
862                         goto err;
863         }
865         /* Support ext_wakeup pinconf */
866         rtc_pinctrl_desc.name = dev_name(&pdev->dev);
868         rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
869         if (IS_ERR(rtc->pctldev)) {
870                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
871                 ret = PTR_ERR(rtc->pctldev);
872                 goto err;
873         }
875         ret = rtc_register_device(rtc->rtc);
876         if (ret)
877                 goto err_deregister_pinctrl;
879         rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
881         if (rtc->is_pmic_controller) {
882                 if (!pm_power_off) {
883                         omap_rtc_power_off_rtc = rtc;
884                         pm_power_off = omap_rtc_power_off;
885                 }
886         }
888         return 0;
890 err_deregister_pinctrl:
891         pinctrl_unregister(rtc->pctldev);
892 err:
893         clk_disable_unprepare(rtc->clk);
894         device_init_wakeup(&pdev->dev, false);
895         rtc->type->lock(rtc);
896         pm_runtime_put_sync(&pdev->dev);
897         pm_runtime_disable(&pdev->dev);
899         return ret;
902 static int omap_rtc_remove(struct platform_device *pdev)
904         struct omap_rtc *rtc = platform_get_drvdata(pdev);
905         u8 reg;
907         if (pm_power_off == omap_rtc_power_off &&
908                         omap_rtc_power_off_rtc == rtc) {
909                 pm_power_off = NULL;
910                 omap_rtc_power_off_rtc = NULL;
911         }
913         device_init_wakeup(&pdev->dev, 0);
915         if (!IS_ERR(rtc->clk))
916                 clk_disable_unprepare(rtc->clk);
918         rtc->type->unlock(rtc);
919         /* leave rtc running, but disable irqs */
920         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
922         if (rtc->has_ext_clk) {
923                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
924                 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
925                 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
926         }
928         rtc->type->lock(rtc);
930         /* Disable the clock/module */
931         pm_runtime_put_sync(&pdev->dev);
932         pm_runtime_disable(&pdev->dev);
934         /* Remove ext_wakeup pinconf */
935         pinctrl_unregister(rtc->pctldev);
937         return 0;
940 static int __maybe_unused omap_rtc_suspend(struct device *dev)
942         struct omap_rtc *rtc = dev_get_drvdata(dev);
944         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
946         rtc->type->unlock(rtc);
947         /*
948          * FIXME: the RTC alarm is not currently acting as a wakeup event
949          * source on some platforms, and in fact this enable() call is just
950          * saving a flag that's never used...
951          */
952         if (device_may_wakeup(dev))
953                 enable_irq_wake(rtc->irq_alarm);
954         else
955                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
956         rtc->type->lock(rtc);
958         rtc->is_suspending = true;
960         return 0;
963 static int __maybe_unused omap_rtc_resume(struct device *dev)
965         struct omap_rtc *rtc = dev_get_drvdata(dev);
967         rtc->type->unlock(rtc);
968         if (device_may_wakeup(dev))
969                 disable_irq_wake(rtc->irq_alarm);
970         else
971                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
972         rtc->type->lock(rtc);
974         rtc->is_suspending = false;
976         return 0;
979 static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
981         struct omap_rtc *rtc = dev_get_drvdata(dev);
983         if (rtc->is_suspending && !rtc->has_ext_clk)
984                 return -EBUSY;
986         return 0;
989 static const struct dev_pm_ops omap_rtc_pm_ops = {
990         SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
991         SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
992 };
994 static void omap_rtc_shutdown(struct platform_device *pdev)
996         struct omap_rtc *rtc = platform_get_drvdata(pdev);
997         u8 mask;
999         /*
1000          * Keep the ALARM interrupt enabled to allow the system to power up on
1001          * alarm events.
1002          */
1003         rtc->type->unlock(rtc);
1004         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
1005         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
1006         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
1007         rtc->type->lock(rtc);
1010 static struct platform_driver omap_rtc_driver = {
1011         .probe          = omap_rtc_probe,
1012         .remove         = omap_rtc_remove,
1013         .shutdown       = omap_rtc_shutdown,
1014         .driver         = {
1015                 .name   = "omap_rtc",
1016                 .pm     = &omap_rtc_pm_ops,
1017                 .of_match_table = omap_rtc_of_match,
1018         },
1019         .id_table       = omap_rtc_id_table,
1020 };
1022 module_platform_driver(omap_rtc_driver);
1024 MODULE_ALIAS("platform:omap_rtc");
1025 MODULE_AUTHOR("George G. Davis (and others)");
1026 MODULE_LICENSE("GPL");