wkup_m3_ipc: Add support for toggling VTT regulator
[rpmsg/hwspinlock.git] / drivers / soc / ti / wkup_m3_ipc.c
1 /*
2  * AMx3 Wkup M3 IPC driver
3  *
4  * Copyright (C) 2015 Texas Instruments, Inc.
5  *
6  * Dave Gerlach <d-gerlach@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
18 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/omap-mailbox.h>
26 #include <linux/platform_device.h>
27 #include <linux/remoteproc.h>
28 #include <linux/suspend.h>
29 #include <linux/wkup_m3_ipc.h>
31 #define AM33XX_CTRL_IPC_REG_COUNT       0x8
32 #define AM33XX_CTRL_IPC_REG_OFFSET(m)   (0x4 + 4 * (m))
34 /* AM33XX M3_TXEV_EOI register */
35 #define AM33XX_CONTROL_M3_TXEV_EOI      0x00
37 #define AM33XX_M3_TXEV_ACK              (0x1 << 0)
38 #define AM33XX_M3_TXEV_ENABLE           (0x0 << 0)
40 #define IPC_CMD_DS0                     0x4
41 #define IPC_CMD_STANDBY                 0xc
42 #define IPC_CMD_IDLE                    0x10
43 #define IPC_CMD_RESET                   0xe
44 #define DS_IPC_DEFAULT                  0xffffffff
45 #define M3_VERSION_UNKNOWN              0x0000ffff
46 #define M3_BASELINE_VERSION             0x191
47 #define M3_STATUS_RESP_MASK             (0xffff << 16)
48 #define M3_FW_VERSION_MASK              0xffff
49 #define M3_WAKE_SRC_MASK                0xff
51 #define IPC_MEM_TYPE_SHIFT              (0x0)
52 #define IPC_MEM_TYPE_MASK               (0x7 << 0)
53 #define IPC_VTT_STAT_SHIFT              (0x3)
54 #define IPC_VTT_STAT_MASK               (0x1 << 3)
55 #define IPC_VTT_GPIO_PIN_SHIFT          (0x4)
56 #define IPC_VTT_GPIO_PIN_MASK           (0x3f << 4)
58 #define M3_STATE_UNKNOWN                0
59 #define M3_STATE_RESET                  1
60 #define M3_STATE_INITED                 2
61 #define M3_STATE_MSG_FOR_LP             3
62 #define M3_STATE_MSG_FOR_RESET          4
64 static struct wkup_m3_ipc *m3_ipc_state;
66 static const struct wkup_m3_wakeup_src wakeups[] = {
67         {.irq_nr = 35,  .src = "USB0_PHY"},
68         {.irq_nr = 36,  .src = "USB1_PHY"},
69         {.irq_nr = 40,  .src = "I2C0"},
70         {.irq_nr = 41,  .src = "RTC Timer"},
71         {.irq_nr = 42,  .src = "RTC Alarm"},
72         {.irq_nr = 43,  .src = "Timer0"},
73         {.irq_nr = 44,  .src = "Timer1"},
74         {.irq_nr = 45,  .src = "UART"},
75         {.irq_nr = 46,  .src = "GPIO0"},
76         {.irq_nr = 48,  .src = "MPU_WAKE"},
77         {.irq_nr = 49,  .src = "WDT0"},
78         {.irq_nr = 50,  .src = "WDT1"},
79         {.irq_nr = 51,  .src = "ADC_TSC"},
80         {.irq_nr = 0,   .src = "Unknown"},
81 };
83 static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
84 {
85         writel(AM33XX_M3_TXEV_ACK,
86                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
87 }
89 static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
90 {
91         writel(AM33XX_M3_TXEV_ENABLE,
92                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
93 }
95 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
96                                    u32 val, int ipc_reg_num)
97 {
98         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
99                  "ipc register operation out of range"))
100                 return;
102         writel(val, m3_ipc->ipc_mem_base +
103                AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
106 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
107                                           int ipc_reg_num)
109         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
110                  "ipc register operation out of range"))
111                 return 0;
113         return readl(m3_ipc->ipc_mem_base +
114                      AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
117 static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
119         int val;
121         val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
123         return val & M3_FW_VERSION_MASK;
126 static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
128         struct wkup_m3_ipc *m3_ipc = ipc_data;
129         struct device *dev = m3_ipc->dev;
130         int ver = 0;
132         am33xx_txev_eoi(m3_ipc);
134         switch (m3_ipc->state) {
135         case M3_STATE_RESET:
136                 ver = wkup_m3_fw_version_read(m3_ipc);
138                 if (ver == M3_VERSION_UNKNOWN ||
139                     ver < M3_BASELINE_VERSION) {
140                         dev_warn(dev, "CM3 Firmware Version %x not supported\n",
141                                  ver);
142                 } else {
143                         dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
144                 }
146                 m3_ipc->state = M3_STATE_INITED;
147                 complete(&m3_ipc->sync_complete);
148                 break;
149         case M3_STATE_MSG_FOR_RESET:
150                 m3_ipc->state = M3_STATE_INITED;
151                 complete(&m3_ipc->sync_complete);
152                 break;
153         case M3_STATE_MSG_FOR_LP:
154                 complete(&m3_ipc->sync_complete);
155                 break;
156         case M3_STATE_UNKNOWN:
157                 dev_warn(dev, "Unknown CM3 State\n");
158         }
160         am33xx_txev_enable(m3_ipc);
162         return IRQ_HANDLED;
165 static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
167         struct device *dev = m3_ipc->dev;
168         mbox_msg_t dummy_msg = 0;
169         int ret;
171         if (!m3_ipc->mbox) {
172                 dev_err(dev,
173                         "No IPC channel to communicate with wkup_m3!\n");
174                 return -EIO;
175         }
177         /*
178          * Write a dummy message to the mailbox in order to trigger the RX
179          * interrupt to alert the M3 that data is available in the IPC
180          * registers. We must enable the IRQ here and disable it after in
181          * the RX callback to avoid multiple interrupts being received
182          * by the CM3.
183          */
184         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
185         if (ret < 0) {
186                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
187                         __func__, ret);
188                 return ret;
189         }
191         ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
192                                           msecs_to_jiffies(500));
193         if (!ret) {
194                 dev_err(dev, "MPU<->CM3 sync failure\n");
195                 m3_ipc->state = M3_STATE_UNKNOWN;
196                 return -EIO;
197         }
199         mbox_client_txdone(m3_ipc->mbox, 0);
200         return 0;
203 static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
205         struct device *dev = m3_ipc->dev;
206         mbox_msg_t dummy_msg = 0;
207         int ret;
209         if (!m3_ipc->mbox) {
210                 dev_err(dev,
211                         "No IPC channel to communicate with wkup_m3!\n");
212                 return -EIO;
213         }
215         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
216         if (ret < 0) {
217                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
218                         __func__, ret);
219                 return ret;
220         }
222         mbox_client_txdone(m3_ipc->mbox, 0);
223         return 0;
226 static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
228         return ((m3_ipc->state != M3_STATE_RESET) &&
229                 (m3_ipc->state != M3_STATE_UNKNOWN));
232 static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m3_ipc, int gpio)
234         m3_ipc->vtt_conf = (1 << IPC_VTT_STAT_SHIFT) |
235                             (gpio << IPC_VTT_GPIO_PIN_SHIFT);
238 /* Public functions */
239 /**
240  * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
241  * @mem_type: memory type value read directly from emif
242  *
243  * wkup_m3 must know what memory type is in use to properly suspend
244  * and resume.
245  */
246 static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
248         m3_ipc->mem_type = mem_type;
251 /**
252  * wkup_m3_set_resume_address - Pass wkup_m3 resume address
253  * @addr: Physical address from which resume code should execute
254  */
255 static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
257         m3_ipc->resume_addr = (unsigned long)addr;
260 /**
261  * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
262  *
263  * Returns code representing the status of a low power mode transition.
264  *      0 - Successful transition
265  *      1 - Failure to transition to low power state
266  */
267 static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
269         unsigned int i;
270         int val;
272         val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
274         i = M3_STATUS_RESP_MASK & val;
275         i >>= __ffs(M3_STATUS_RESP_MASK);
277         return i;
280 /**
281  * wkup_m3_prepare_low_power - Request preparation for transition to
282  *                             low power state
283  * @state: A kernel suspend state to enter, either MEM or STANDBY
284  *
285  * Returns 0 if preparation was successful, otherwise returns error code
286  */
287 static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
289         struct device *dev = m3_ipc->dev;
290         int m3_power_state;
291         int ret = 0;
293         if (!wkup_m3_is_available(m3_ipc))
294                 return -ENODEV;
296         switch (state) {
297         case WKUP_M3_DEEPSLEEP:
298                 m3_power_state = IPC_CMD_DS0;
299                 break;
300         case WKUP_M3_STANDBY:
301                 m3_power_state = IPC_CMD_STANDBY;
302                 break;
303         case WKUP_M3_IDLE:
304                 m3_power_state = IPC_CMD_IDLE;
305                 break;
306         default:
307                 return 1;
308         }
310         /* Program each required IPC register then write defaults to others */
311         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
312         wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
313         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type |
314                                m3_ipc->vtt_conf, 4);
316         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
317         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
318         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
319         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
320         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
322         m3_ipc->state = M3_STATE_MSG_FOR_LP;
324         if (state == WKUP_M3_IDLE)
325                 ret = wkup_m3_ping_noirq(m3_ipc);
326         else
327                 ret = wkup_m3_ping(m3_ipc);
329         if (ret) {
330                 dev_err(dev, "Unable to ping CM3\n");
331                 return ret;
332         }
334         return 0;
337 /**
338  * wkup_m3_finish_low_power - Return m3 to reset state
339  *
340  * Returns 0 if reset was successful, otherwise returns error code
341  */
342 static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
344         struct device *dev = m3_ipc->dev;
345         int ret = 0;
347         if (!wkup_m3_is_available(m3_ipc))
348                 return -ENODEV;
350         wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
351         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
353         m3_ipc->state = M3_STATE_MSG_FOR_RESET;
355         ret = wkup_m3_ping(m3_ipc);
356         if (ret) {
357                 dev_err(dev, "Unable to ping CM3\n");
358                 return ret;
359         }
361         return 0;
364 /**
365  * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
366  * @m3_ipc: Pointer to wkup_m3_ipc context
367  */
368 static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
370         unsigned int wakeup_src_idx;
371         int j, val;
373         val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
375         wakeup_src_idx = val & M3_WAKE_SRC_MASK;
377         for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
378                 if (wakeups[j].irq_nr == wakeup_src_idx)
379                         return wakeups[j].src;
380         }
381         return wakeups[j].src;
384 /**
385  * wkup_m3_set_rtc_only - Set the rtc_only flag
386  * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
387  *                  wakeup src value
388  */
389 static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
391         if (m3_ipc_state)
392                 m3_ipc_state->is_rtc_only = true;
395 static struct wkup_m3_ipc_ops ipc_ops = {
396         .set_mem_type = wkup_m3_set_mem_type,
397         .set_resume_address = wkup_m3_set_resume_address,
398         .prepare_low_power = wkup_m3_prepare_low_power,
399         .finish_low_power = wkup_m3_finish_low_power,
400         .request_pm_status = wkup_m3_request_pm_status,
401         .request_wake_src = wkup_m3_request_wake_src,
402         .set_rtc_only = wkup_m3_set_rtc_only,
403 };
405 /**
406  * wkup_m3_ipc_get - Return handle to wkup_m3_ipc
407  *
408  * Returns NULL if the wkup_m3 is not yet available, otherwise returns
409  * pointer to wkup_m3_ipc struct.
410  */
411 struct wkup_m3_ipc *wkup_m3_ipc_get(void)
413         if (m3_ipc_state)
414                 get_device(m3_ipc_state->dev);
415         else
416                 return NULL;
418         return m3_ipc_state;
420 EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
422 /**
423  * wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
424  * @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
425  */
426 void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
428         if (m3_ipc_state)
429                 put_device(m3_ipc_state->dev);
431 EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
433 static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc)
435         struct device *dev = m3_ipc->dev;
436         int ret;
438         init_completion(&m3_ipc->sync_complete);
440         ret = rproc_boot(m3_ipc->rproc);
441         if (ret)
442                 dev_err(dev, "rproc_boot failed\n");
444         do_exit(0);
447 static int wkup_m3_ipc_probe(struct platform_device *pdev)
449         struct device *dev = &pdev->dev;
450         int irq, ret, temp;
451         phandle rproc_phandle;
452         struct rproc *m3_rproc;
453         struct resource *res;
454         struct task_struct *task;
455         struct wkup_m3_ipc *m3_ipc;
456         struct device_node *np = dev->of_node;
458         m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
459         if (!m3_ipc)
460                 return -ENOMEM;
462         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
463         m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res);
464         if (IS_ERR(m3_ipc->ipc_mem_base)) {
465                 dev_err(dev, "could not ioremap ipc_mem\n");
466                 return PTR_ERR(m3_ipc->ipc_mem_base);
467         }
469         irq = platform_get_irq(pdev, 0);
470         if (!irq) {
471                 dev_err(&pdev->dev, "no irq resource\n");
472                 return -ENXIO;
473         }
475         ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
476                                0, "wkup_m3_txev", m3_ipc);
477         if (ret) {
478                 dev_err(dev, "request_irq failed\n");
479                 return ret;
480         }
482         m3_ipc->mbox_client.dev = dev;
483         m3_ipc->mbox_client.tx_done = NULL;
484         m3_ipc->mbox_client.tx_prepare = NULL;
485         m3_ipc->mbox_client.rx_callback = NULL;
486         m3_ipc->mbox_client.tx_block = false;
487         m3_ipc->mbox_client.knows_txdone = false;
489         m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
491         if (IS_ERR(m3_ipc->mbox)) {
492                 dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
493                         PTR_ERR(m3_ipc->mbox));
494                 return PTR_ERR(m3_ipc->mbox);
495         }
497         if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
498                 dev_err(&pdev->dev, "could not get rproc phandle\n");
499                 ret = -ENODEV;
500                 goto err_free_mbox;
501         }
503         m3_rproc = rproc_get_by_phandle(rproc_phandle);
504         if (!m3_rproc) {
505                 dev_err(&pdev->dev, "could not get rproc handle\n");
506                 ret = -EPROBE_DEFER;
507                 goto err_free_mbox;
508         }
510         m3_ipc->rproc = m3_rproc;
511         m3_ipc->dev = dev;
512         m3_ipc->state = M3_STATE_RESET;
514         m3_ipc->ops = &ipc_ops;
516         if (of_find_property(np, "ti,needs-vtt-toggle", NULL) &&
517             !(of_property_read_u32(np, "ti,vtt-gpio-pin", &temp))) {
518                 if (temp >= 0 && temp <= 31)
519                         wkup_m3_set_vtt_gpio(m3_ipc, temp);
520                 else
521                         dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp);
522         }
524         /*
525          * Wait for firmware loading completion in a thread so we
526          * can boot the wkup_m3 as soon as it's ready without holding
527          * up kernel boot
528          */
529         task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc,
530                            "wkup_m3_rproc_loader");
532         if (IS_ERR(task)) {
533                 dev_err(dev, "can't create rproc_boot thread\n");
534                 ret = PTR_ERR(task);
535                 goto err_put_rproc;
536         }
538         m3_ipc_state = m3_ipc;
540         return 0;
542 err_put_rproc:
543         rproc_put(m3_rproc);
544 err_free_mbox:
545         mbox_free_channel(m3_ipc->mbox);
546         return ret;
549 static int wkup_m3_ipc_remove(struct platform_device *pdev)
551         mbox_free_channel(m3_ipc_state->mbox);
553         rproc_shutdown(m3_ipc_state->rproc);
554         rproc_put(m3_ipc_state->rproc);
556         m3_ipc_state = NULL;
558         return 0;
561 static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
563         /*
564          * Nothing needs to be done on suspend even with rtc_only flag set
565          */
566         return 0;
569 static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
571         if (m3_ipc_state->is_rtc_only) {
572                 rproc_shutdown(m3_ipc_state->rproc);
573                 rproc_boot(m3_ipc_state->rproc);
574         }
576         m3_ipc_state->is_rtc_only = false;
578         return 0;
581 static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
582         SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
583 };
585 static const struct of_device_id wkup_m3_ipc_of_match[] = {
586         { .compatible = "ti,am3352-wkup-m3-ipc", },
587         { .compatible = "ti,am4372-wkup-m3-ipc", },
588         {},
589 };
590 MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
592 static struct platform_driver wkup_m3_ipc_driver = {
593         .probe = wkup_m3_ipc_probe,
594         .remove = wkup_m3_ipc_remove,
595         .driver = {
596                 .name = "wkup_m3_ipc",
597                 .of_match_table = wkup_m3_ipc_of_match,
598                 .pm = &wkup_m3_ipc_pm_ops,
599         },
600 };
602 module_platform_driver(wkup_m3_ipc_driver);
604 MODULE_LICENSE("GPL v2");
605 MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
606 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");