wkup_m3_ipc: Add support for IO Isolation
[rpmsg/hwspinlock.git] / drivers / soc / ti / wkup_m3_ipc.c
1 /*
2  * AMx3 Wkup M3 IPC driver
3  *
4  * Copyright (C) 2015 Texas Instruments, Inc.
5  *
6  * Dave Gerlach <d-gerlach@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
18 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/omap-mailbox.h>
26 #include <linux/platform_device.h>
27 #include <linux/remoteproc.h>
28 #include <linux/suspend.h>
29 #include <linux/wkup_m3_ipc.h>
31 #define AM33XX_CTRL_IPC_REG_COUNT       0x8
32 #define AM33XX_CTRL_IPC_REG_OFFSET(m)   (0x4 + 4 * (m))
34 /* AM33XX M3_TXEV_EOI register */
35 #define AM33XX_CONTROL_M3_TXEV_EOI      0x00
37 #define AM33XX_M3_TXEV_ACK              (0x1 << 0)
38 #define AM33XX_M3_TXEV_ENABLE           (0x0 << 0)
40 #define IPC_CMD_DS0                     0x4
41 #define IPC_CMD_STANDBY                 0xc
42 #define IPC_CMD_IDLE                    0x10
43 #define IPC_CMD_RESET                   0xe
44 #define DS_IPC_DEFAULT                  0xffffffff
45 #define M3_VERSION_UNKNOWN              0x0000ffff
46 #define M3_BASELINE_VERSION             0x191
47 #define M3_STATUS_RESP_MASK             (0xffff << 16)
48 #define M3_FW_VERSION_MASK              0xffff
49 #define M3_WAKE_SRC_MASK                0xff
51 #define IPC_MEM_TYPE_SHIFT              (0x0)
52 #define IPC_MEM_TYPE_MASK               (0x7 << 0)
53 #define IPC_VTT_STAT_SHIFT              (0x3)
54 #define IPC_VTT_STAT_MASK               (0x1 << 3)
55 #define IPC_VTT_GPIO_PIN_SHIFT          (0x4)
56 #define IPC_VTT_GPIO_PIN_MASK           (0x3f << 4)
57 #define IPC_IO_ISOLATION_STAT_SHIFT     (10)
58 #define IPC_IO_ISOLATION_STAT_MASK      (0x1 << 10)
60 #define M3_STATE_UNKNOWN                0
61 #define M3_STATE_RESET                  1
62 #define M3_STATE_INITED                 2
63 #define M3_STATE_MSG_FOR_LP             3
64 #define M3_STATE_MSG_FOR_RESET          4
66 static struct wkup_m3_ipc *m3_ipc_state;
68 static const struct wkup_m3_wakeup_src wakeups[] = {
69         {.irq_nr = 35,  .src = "USB0_PHY"},
70         {.irq_nr = 36,  .src = "USB1_PHY"},
71         {.irq_nr = 40,  .src = "I2C0"},
72         {.irq_nr = 41,  .src = "RTC Timer"},
73         {.irq_nr = 42,  .src = "RTC Alarm"},
74         {.irq_nr = 43,  .src = "Timer0"},
75         {.irq_nr = 44,  .src = "Timer1"},
76         {.irq_nr = 45,  .src = "UART"},
77         {.irq_nr = 46,  .src = "GPIO0"},
78         {.irq_nr = 48,  .src = "MPU_WAKE"},
79         {.irq_nr = 49,  .src = "WDT0"},
80         {.irq_nr = 50,  .src = "WDT1"},
81         {.irq_nr = 51,  .src = "ADC_TSC"},
82         {.irq_nr = 0,   .src = "Unknown"},
83 };
85 static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
86 {
87         writel(AM33XX_M3_TXEV_ACK,
88                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
89 }
91 static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
92 {
93         writel(AM33XX_M3_TXEV_ENABLE,
94                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
95 }
97 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
98                                    u32 val, int ipc_reg_num)
99 {
100         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
101                  "ipc register operation out of range"))
102                 return;
104         writel(val, m3_ipc->ipc_mem_base +
105                AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
108 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
109                                           int ipc_reg_num)
111         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
112                  "ipc register operation out of range"))
113                 return 0;
115         return readl(m3_ipc->ipc_mem_base +
116                      AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
119 static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
121         int val;
123         val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
125         return val & M3_FW_VERSION_MASK;
128 static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
130         struct wkup_m3_ipc *m3_ipc = ipc_data;
131         struct device *dev = m3_ipc->dev;
132         int ver = 0;
134         am33xx_txev_eoi(m3_ipc);
136         switch (m3_ipc->state) {
137         case M3_STATE_RESET:
138                 ver = wkup_m3_fw_version_read(m3_ipc);
140                 if (ver == M3_VERSION_UNKNOWN ||
141                     ver < M3_BASELINE_VERSION) {
142                         dev_warn(dev, "CM3 Firmware Version %x not supported\n",
143                                  ver);
144                 } else {
145                         dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
146                 }
148                 m3_ipc->state = M3_STATE_INITED;
149                 complete(&m3_ipc->sync_complete);
150                 break;
151         case M3_STATE_MSG_FOR_RESET:
152                 m3_ipc->state = M3_STATE_INITED;
153                 complete(&m3_ipc->sync_complete);
154                 break;
155         case M3_STATE_MSG_FOR_LP:
156                 complete(&m3_ipc->sync_complete);
157                 break;
158         case M3_STATE_UNKNOWN:
159                 dev_warn(dev, "Unknown CM3 State\n");
160         }
162         am33xx_txev_enable(m3_ipc);
164         return IRQ_HANDLED;
167 static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
169         struct device *dev = m3_ipc->dev;
170         mbox_msg_t dummy_msg = 0;
171         int ret;
173         if (!m3_ipc->mbox) {
174                 dev_err(dev,
175                         "No IPC channel to communicate with wkup_m3!\n");
176                 return -EIO;
177         }
179         /*
180          * Write a dummy message to the mailbox in order to trigger the RX
181          * interrupt to alert the M3 that data is available in the IPC
182          * registers. We must enable the IRQ here and disable it after in
183          * the RX callback to avoid multiple interrupts being received
184          * by the CM3.
185          */
186         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
187         if (ret < 0) {
188                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
189                         __func__, ret);
190                 return ret;
191         }
193         ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
194                                           msecs_to_jiffies(500));
195         if (!ret) {
196                 dev_err(dev, "MPU<->CM3 sync failure\n");
197                 m3_ipc->state = M3_STATE_UNKNOWN;
198                 return -EIO;
199         }
201         mbox_client_txdone(m3_ipc->mbox, 0);
202         return 0;
205 static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
207         struct device *dev = m3_ipc->dev;
208         mbox_msg_t dummy_msg = 0;
209         int ret;
211         if (!m3_ipc->mbox) {
212                 dev_err(dev,
213                         "No IPC channel to communicate with wkup_m3!\n");
214                 return -EIO;
215         }
217         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
218         if (ret < 0) {
219                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
220                         __func__, ret);
221                 return ret;
222         }
224         mbox_client_txdone(m3_ipc->mbox, 0);
225         return 0;
228 static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
230         return ((m3_ipc->state != M3_STATE_RESET) &&
231                 (m3_ipc->state != M3_STATE_UNKNOWN));
234 static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m3_ipc, int gpio)
236         m3_ipc->vtt_conf = (1 << IPC_VTT_STAT_SHIFT) |
237                             (gpio << IPC_VTT_GPIO_PIN_SHIFT);
240 static void wkup_m3_set_io_isolation(struct wkup_m3_ipc *m3_ipc)
242         m3_ipc->isolation_conf = (1 << IPC_IO_ISOLATION_STAT_SHIFT);
245 /* Public functions */
246 /**
247  * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
248  * @mem_type: memory type value read directly from emif
249  *
250  * wkup_m3 must know what memory type is in use to properly suspend
251  * and resume.
252  */
253 static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
255         m3_ipc->mem_type = mem_type;
258 /**
259  * wkup_m3_set_resume_address - Pass wkup_m3 resume address
260  * @addr: Physical address from which resume code should execute
261  */
262 static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
264         m3_ipc->resume_addr = (unsigned long)addr;
267 /**
268  * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
269  *
270  * Returns code representing the status of a low power mode transition.
271  *      0 - Successful transition
272  *      1 - Failure to transition to low power state
273  */
274 static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
276         unsigned int i;
277         int val;
279         val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
281         i = M3_STATUS_RESP_MASK & val;
282         i >>= __ffs(M3_STATUS_RESP_MASK);
284         return i;
287 /**
288  * wkup_m3_prepare_low_power - Request preparation for transition to
289  *                             low power state
290  * @state: A kernel suspend state to enter, either MEM or STANDBY
291  *
292  * Returns 0 if preparation was successful, otherwise returns error code
293  */
294 static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
296         struct device *dev = m3_ipc->dev;
297         int m3_power_state;
298         int ret = 0;
300         if (!wkup_m3_is_available(m3_ipc))
301                 return -ENODEV;
303         switch (state) {
304         case WKUP_M3_DEEPSLEEP:
305                 m3_power_state = IPC_CMD_DS0;
306                 break;
307         case WKUP_M3_STANDBY:
308                 m3_power_state = IPC_CMD_STANDBY;
309                 break;
310         case WKUP_M3_IDLE:
311                 m3_power_state = IPC_CMD_IDLE;
312                 break;
313         default:
314                 return 1;
315         }
317         /* Program each required IPC register then write defaults to others */
318         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
319         wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
320         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type |
321                                m3_ipc->vtt_conf |
322                                m3_ipc->isolation_conf, 4);
323         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
324         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
325         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
326         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
327         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
329         m3_ipc->state = M3_STATE_MSG_FOR_LP;
331         if (state == WKUP_M3_IDLE)
332                 ret = wkup_m3_ping_noirq(m3_ipc);
333         else
334                 ret = wkup_m3_ping(m3_ipc);
336         if (ret) {
337                 dev_err(dev, "Unable to ping CM3\n");
338                 return ret;
339         }
341         return 0;
344 /**
345  * wkup_m3_finish_low_power - Return m3 to reset state
346  *
347  * Returns 0 if reset was successful, otherwise returns error code
348  */
349 static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
351         struct device *dev = m3_ipc->dev;
352         int ret = 0;
354         if (!wkup_m3_is_available(m3_ipc))
355                 return -ENODEV;
357         wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
358         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
360         m3_ipc->state = M3_STATE_MSG_FOR_RESET;
362         ret = wkup_m3_ping(m3_ipc);
363         if (ret) {
364                 dev_err(dev, "Unable to ping CM3\n");
365                 return ret;
366         }
368         return 0;
371 /**
372  * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
373  * @m3_ipc: Pointer to wkup_m3_ipc context
374  */
375 static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
377         unsigned int wakeup_src_idx;
378         int j, val;
380         val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
382         wakeup_src_idx = val & M3_WAKE_SRC_MASK;
384         for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
385                 if (wakeups[j].irq_nr == wakeup_src_idx)
386                         return wakeups[j].src;
387         }
388         return wakeups[j].src;
391 /**
392  * wkup_m3_set_rtc_only - Set the rtc_only flag
393  * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
394  *                  wakeup src value
395  */
396 static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
398         if (m3_ipc_state)
399                 m3_ipc_state->is_rtc_only = true;
402 static struct wkup_m3_ipc_ops ipc_ops = {
403         .set_mem_type = wkup_m3_set_mem_type,
404         .set_resume_address = wkup_m3_set_resume_address,
405         .prepare_low_power = wkup_m3_prepare_low_power,
406         .finish_low_power = wkup_m3_finish_low_power,
407         .request_pm_status = wkup_m3_request_pm_status,
408         .request_wake_src = wkup_m3_request_wake_src,
409         .set_rtc_only = wkup_m3_set_rtc_only,
410 };
412 /**
413  * wkup_m3_ipc_get - Return handle to wkup_m3_ipc
414  *
415  * Returns NULL if the wkup_m3 is not yet available, otherwise returns
416  * pointer to wkup_m3_ipc struct.
417  */
418 struct wkup_m3_ipc *wkup_m3_ipc_get(void)
420         if (m3_ipc_state)
421                 get_device(m3_ipc_state->dev);
422         else
423                 return NULL;
425         return m3_ipc_state;
427 EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
429 /**
430  * wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
431  * @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
432  */
433 void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
435         if (m3_ipc_state)
436                 put_device(m3_ipc_state->dev);
438 EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
440 static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc)
442         struct device *dev = m3_ipc->dev;
443         int ret;
445         init_completion(&m3_ipc->sync_complete);
447         ret = rproc_boot(m3_ipc->rproc);
448         if (ret)
449                 dev_err(dev, "rproc_boot failed\n");
451         do_exit(0);
454 static int wkup_m3_ipc_probe(struct platform_device *pdev)
456         struct device *dev = &pdev->dev;
457         int irq, ret, temp;
458         phandle rproc_phandle;
459         struct rproc *m3_rproc;
460         struct resource *res;
461         struct task_struct *task;
462         struct wkup_m3_ipc *m3_ipc;
463         struct device_node *np = dev->of_node;
465         m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
466         if (!m3_ipc)
467                 return -ENOMEM;
469         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
470         m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res);
471         if (IS_ERR(m3_ipc->ipc_mem_base)) {
472                 dev_err(dev, "could not ioremap ipc_mem\n");
473                 return PTR_ERR(m3_ipc->ipc_mem_base);
474         }
476         irq = platform_get_irq(pdev, 0);
477         if (!irq) {
478                 dev_err(&pdev->dev, "no irq resource\n");
479                 return -ENXIO;
480         }
482         ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
483                                0, "wkup_m3_txev", m3_ipc);
484         if (ret) {
485                 dev_err(dev, "request_irq failed\n");
486                 return ret;
487         }
489         m3_ipc->mbox_client.dev = dev;
490         m3_ipc->mbox_client.tx_done = NULL;
491         m3_ipc->mbox_client.tx_prepare = NULL;
492         m3_ipc->mbox_client.rx_callback = NULL;
493         m3_ipc->mbox_client.tx_block = false;
494         m3_ipc->mbox_client.knows_txdone = false;
496         m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
498         if (IS_ERR(m3_ipc->mbox)) {
499                 dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
500                         PTR_ERR(m3_ipc->mbox));
501                 return PTR_ERR(m3_ipc->mbox);
502         }
504         if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
505                 dev_err(&pdev->dev, "could not get rproc phandle\n");
506                 ret = -ENODEV;
507                 goto err_free_mbox;
508         }
510         m3_rproc = rproc_get_by_phandle(rproc_phandle);
511         if (!m3_rproc) {
512                 dev_err(&pdev->dev, "could not get rproc handle\n");
513                 ret = -EPROBE_DEFER;
514                 goto err_free_mbox;
515         }
517         m3_ipc->rproc = m3_rproc;
518         m3_ipc->dev = dev;
519         m3_ipc->state = M3_STATE_RESET;
521         m3_ipc->ops = &ipc_ops;
523         if (of_find_property(np, "ti,needs-vtt-toggle", NULL) &&
524             !(of_property_read_u32(np, "ti,vtt-gpio-pin", &temp))) {
525                 if (temp >= 0 && temp <= 31)
526                         wkup_m3_set_vtt_gpio(m3_ipc, temp);
527                 else
528                         dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp);
529         }
531         if (of_find_property(np, "ti,set-io-isolation", NULL))
532                 wkup_m3_set_io_isolation(m3_ipc);
534         /*
535          * Wait for firmware loading completion in a thread so we
536          * can boot the wkup_m3 as soon as it's ready without holding
537          * up kernel boot
538          */
539         task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc,
540                            "wkup_m3_rproc_loader");
542         if (IS_ERR(task)) {
543                 dev_err(dev, "can't create rproc_boot thread\n");
544                 ret = PTR_ERR(task);
545                 goto err_put_rproc;
546         }
548         m3_ipc_state = m3_ipc;
550         return 0;
552 err_put_rproc:
553         rproc_put(m3_rproc);
554 err_free_mbox:
555         mbox_free_channel(m3_ipc->mbox);
556         return ret;
559 static int wkup_m3_ipc_remove(struct platform_device *pdev)
561         mbox_free_channel(m3_ipc_state->mbox);
563         rproc_shutdown(m3_ipc_state->rproc);
564         rproc_put(m3_ipc_state->rproc);
566         m3_ipc_state = NULL;
568         return 0;
571 static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
573         /*
574          * Nothing needs to be done on suspend even with rtc_only flag set
575          */
576         return 0;
579 static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
581         if (m3_ipc_state->is_rtc_only) {
582                 rproc_shutdown(m3_ipc_state->rproc);
583                 rproc_boot(m3_ipc_state->rproc);
584         }
586         m3_ipc_state->is_rtc_only = false;
588         return 0;
591 static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
592         SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
593 };
595 static const struct of_device_id wkup_m3_ipc_of_match[] = {
596         { .compatible = "ti,am3352-wkup-m3-ipc", },
597         { .compatible = "ti,am4372-wkup-m3-ipc", },
598         {},
599 };
600 MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
602 static struct platform_driver wkup_m3_ipc_driver = {
603         .probe = wkup_m3_ipc_probe,
604         .remove = wkup_m3_ipc_remove,
605         .driver = {
606                 .name = "wkup_m3_ipc",
607                 .of_match_table = wkup_m3_ipc_of_match,
608                 .pm = &wkup_m3_ipc_pm_ops,
609         },
610 };
612 module_platform_driver(wkup_m3_ipc_driver);
614 MODULE_LICENSE("GPL v2");
615 MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
616 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");