a32412906b3ae358cde7c5d02f895e364868f12b
[rpmsg/hwspinlock.git] / drivers / soc / ti / wkup_m3_ipc.c
1 /*
2  * AMx3 Wkup M3 IPC driver
3  *
4  * Copyright (C) 2015 Texas Instruments, Inc.
5  *
6  * Dave Gerlach <d-gerlach@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
18 #include <linux/err.h>
19 #include <linux/firmware.h>
20 #include <linux/kernel.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/omap-mailbox.h>
27 #include <linux/platform_device.h>
28 #include <linux/remoteproc.h>
29 #include <linux/suspend.h>
30 #include <linux/wkup_m3_ipc.h>
32 #define AM33XX_CTRL_IPC_REG_COUNT       0x8
33 #define AM33XX_CTRL_IPC_REG_OFFSET(m)   (0x4 + 4 * (m))
35 /* AM33XX M3_TXEV_EOI register */
36 #define AM33XX_CONTROL_M3_TXEV_EOI      0x00
38 #define AM33XX_M3_TXEV_ACK              (0x1 << 0)
39 #define AM33XX_M3_TXEV_ENABLE           (0x0 << 0)
41 #define IPC_CMD_DS0                     0x4
42 #define IPC_CMD_STANDBY                 0xc
43 #define IPC_CMD_IDLE                    0x10
44 #define IPC_CMD_RESET                   0xe
45 #define DS_IPC_DEFAULT                  0xffffffff
46 #define M3_VERSION_UNKNOWN              0x0000ffff
47 #define M3_BASELINE_VERSION             0x191
48 #define M3_STATUS_RESP_MASK             (0xffff << 16)
49 #define M3_FW_VERSION_MASK              0xffff
50 #define M3_WAKE_SRC_MASK                0xff
52 #define IPC_MEM_TYPE_SHIFT              (0x0)
53 #define IPC_MEM_TYPE_MASK               (0x7 << 0)
54 #define IPC_VTT_STAT_SHIFT              (0x3)
55 #define IPC_VTT_STAT_MASK               (0x1 << 3)
56 #define IPC_VTT_GPIO_PIN_SHIFT          (0x4)
57 #define IPC_VTT_GPIO_PIN_MASK           (0x3f << 4)
58 #define IPC_IO_ISOLATION_STAT_SHIFT     (10)
59 #define IPC_IO_ISOLATION_STAT_MASK      (0x1 << 10)
61 #define M3_STATE_UNKNOWN                0
62 #define M3_STATE_RESET                  1
63 #define M3_STATE_INITED                 2
64 #define M3_STATE_MSG_FOR_LP             3
65 #define M3_STATE_MSG_FOR_RESET          4
67 #define WKUP_M3_SD_FW_MAGIC             0x570C
69 #define WKUP_M3_DMEM_START              0x80000
70 #define WKUP_M3_AUXDATA_OFFSET          0x1000
71 #define WKUP_M3_AUXDATA_SIZE            0xFF
73 static struct wkup_m3_ipc *m3_ipc_state;
75 static const struct wkup_m3_wakeup_src wakeups[] = {
76         {.irq_nr = 35,  .src = "USB0_PHY"},
77         {.irq_nr = 36,  .src = "USB1_PHY"},
78         {.irq_nr = 40,  .src = "I2C0"},
79         {.irq_nr = 41,  .src = "RTC Timer"},
80         {.irq_nr = 42,  .src = "RTC Alarm"},
81         {.irq_nr = 43,  .src = "Timer0"},
82         {.irq_nr = 44,  .src = "Timer1"},
83         {.irq_nr = 45,  .src = "UART"},
84         {.irq_nr = 46,  .src = "GPIO0"},
85         {.irq_nr = 48,  .src = "MPU_WAKE"},
86         {.irq_nr = 49,  .src = "WDT0"},
87         {.irq_nr = 50,  .src = "WDT1"},
88         {.irq_nr = 51,  .src = "ADC_TSC"},
89         {.irq_nr = 0,   .src = "Unknown"},
90 };
92 /**
93  * wkup_m3_copy_aux_data - Copy auxiliary data to special region of m3 dmem
94  * @data - pointer to data
95  * @sz - size of data to copy (limit 256 bytes)
96  *
97  * Copies any additional blob of data to the wkup_m3 dmem to be used by the
98  * firmware
99  */
100 static unsigned long wkup_m3_copy_aux_data(struct wkup_m3_ipc *m3_ipc,
101                                            const void *data, int sz)
103         unsigned long aux_data_dev_addr;
104         void *aux_data_addr;
106         aux_data_dev_addr = WKUP_M3_DMEM_START + WKUP_M3_AUXDATA_OFFSET;
107         aux_data_addr = rproc_da_to_va(m3_ipc->rproc,
108                                        aux_data_dev_addr,
109                                        WKUP_M3_AUXDATA_SIZE);
110         memcpy(aux_data_addr, data, sz);
112         return WKUP_M3_AUXDATA_OFFSET;
115 static void wkup_m3_scale_data_fw_cb(const struct firmware *fw, void *context)
117         unsigned long val, aux_base;
118         struct wkup_m3_scale_data_header hdr;
119         struct wkup_m3_ipc *m3_ipc = context;
120         struct device *dev = m3_ipc->dev;
122         if (!fw) {
123                 dev_err(dev, "Voltage scale fw name given but file missing.\n");
124                 return;
125         }
127         memcpy(&hdr, fw->data, sizeof(hdr));
129         if (hdr.magic != WKUP_M3_SD_FW_MAGIC) {
130                 dev_err(dev, "PM: Voltage Scale Data binary does not appear valid.\n");
131                 goto release_sd_fw;
132         }
134         aux_base = wkup_m3_copy_aux_data(m3_ipc, fw->data + sizeof(hdr),
135                                          fw->size - sizeof(hdr));
137         val = (aux_base + hdr.sleep_offset);
138         val |= ((aux_base + hdr.wake_offset) << 16);
140         m3_ipc->volt_scale_offsets = val;
142 release_sd_fw:
143         release_firmware(fw);
144 };
146 static int wkup_m3_init_scale_data(struct wkup_m3_ipc *m3_ipc,
147                                    struct device *dev)
149         int ret = 0;
151         /*
152          * If no name is provided, user has already been warned, pm will
153          * still work so return 0
154          */
156         if (!m3_ipc->sd_fw_name)
157                 return ret;
159         ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
160                                       m3_ipc->sd_fw_name, dev, GFP_ATOMIC,
161                                       m3_ipc, wkup_m3_scale_data_fw_cb);
163         return ret;
166 static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
168         writel(AM33XX_M3_TXEV_ACK,
169                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
172 static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
174         writel(AM33XX_M3_TXEV_ENABLE,
175                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
178 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
179                                    u32 val, int ipc_reg_num)
181         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
182                  "ipc register operation out of range"))
183                 return;
185         writel(val, m3_ipc->ipc_mem_base +
186                AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
189 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
190                                           int ipc_reg_num)
192         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
193                  "ipc register operation out of range"))
194                 return 0;
196         return readl(m3_ipc->ipc_mem_base +
197                      AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
200 static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
202         int val;
204         val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
206         return val & M3_FW_VERSION_MASK;
209 static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
211         struct wkup_m3_ipc *m3_ipc = ipc_data;
212         struct device *dev = m3_ipc->dev;
213         int ver = 0;
215         am33xx_txev_eoi(m3_ipc);
217         switch (m3_ipc->state) {
218         case M3_STATE_RESET:
219                 ver = wkup_m3_fw_version_read(m3_ipc);
221                 if (ver == M3_VERSION_UNKNOWN ||
222                     ver < M3_BASELINE_VERSION) {
223                         dev_warn(dev, "CM3 Firmware Version %x not supported\n",
224                                  ver);
225                 } else {
226                         dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
227                 }
229                 m3_ipc->state = M3_STATE_INITED;
230                 wkup_m3_init_scale_data(m3_ipc, dev);
231                 complete(&m3_ipc->sync_complete);
232                 break;
233         case M3_STATE_MSG_FOR_RESET:
234                 m3_ipc->state = M3_STATE_INITED;
235                 complete(&m3_ipc->sync_complete);
236                 break;
237         case M3_STATE_MSG_FOR_LP:
238                 complete(&m3_ipc->sync_complete);
239                 break;
240         case M3_STATE_UNKNOWN:
241                 dev_warn(dev, "Unknown CM3 State\n");
242         }
244         am33xx_txev_enable(m3_ipc);
246         return IRQ_HANDLED;
249 static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
251         struct device *dev = m3_ipc->dev;
252         mbox_msg_t dummy_msg = 0;
253         int ret;
255         if (!m3_ipc->mbox) {
256                 dev_err(dev,
257                         "No IPC channel to communicate with wkup_m3!\n");
258                 return -EIO;
259         }
261         /*
262          * Write a dummy message to the mailbox in order to trigger the RX
263          * interrupt to alert the M3 that data is available in the IPC
264          * registers. We must enable the IRQ here and disable it after in
265          * the RX callback to avoid multiple interrupts being received
266          * by the CM3.
267          */
268         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
269         if (ret < 0) {
270                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
271                         __func__, ret);
272                 return ret;
273         }
275         ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
276                                           msecs_to_jiffies(500));
277         if (!ret) {
278                 dev_err(dev, "MPU<->CM3 sync failure\n");
279                 m3_ipc->state = M3_STATE_UNKNOWN;
280                 return -EIO;
281         }
283         mbox_client_txdone(m3_ipc->mbox, 0);
284         return 0;
287 static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
289         struct device *dev = m3_ipc->dev;
290         mbox_msg_t dummy_msg = 0;
291         int ret;
293         if (!m3_ipc->mbox) {
294                 dev_err(dev,
295                         "No IPC channel to communicate with wkup_m3!\n");
296                 return -EIO;
297         }
299         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
300         if (ret < 0) {
301                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
302                         __func__, ret);
303                 return ret;
304         }
306         mbox_client_txdone(m3_ipc->mbox, 0);
307         return 0;
310 static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
312         return ((m3_ipc->state != M3_STATE_RESET) &&
313                 (m3_ipc->state != M3_STATE_UNKNOWN));
316 static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m3_ipc, int gpio)
318         m3_ipc->vtt_conf = (1 << IPC_VTT_STAT_SHIFT) |
319                             (gpio << IPC_VTT_GPIO_PIN_SHIFT);
322 static void wkup_m3_set_io_isolation(struct wkup_m3_ipc *m3_ipc)
324         m3_ipc->isolation_conf = (1 << IPC_IO_ISOLATION_STAT_SHIFT);
327 /* Public functions */
328 /**
329  * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
330  * @mem_type: memory type value read directly from emif
331  *
332  * wkup_m3 must know what memory type is in use to properly suspend
333  * and resume.
334  */
335 static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
337         m3_ipc->mem_type = mem_type;
340 /**
341  * wkup_m3_set_resume_address - Pass wkup_m3 resume address
342  * @addr: Physical address from which resume code should execute
343  */
344 static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
346         m3_ipc->resume_addr = (unsigned long)addr;
349 /**
350  * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
351  *
352  * Returns code representing the status of a low power mode transition.
353  *      0 - Successful transition
354  *      1 - Failure to transition to low power state
355  */
356 static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
358         unsigned int i;
359         int val;
361         val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
363         i = M3_STATUS_RESP_MASK & val;
364         i >>= __ffs(M3_STATUS_RESP_MASK);
366         return i;
369 /**
370  * wkup_m3_prepare_low_power - Request preparation for transition to
371  *                             low power state
372  * @state: A kernel suspend state to enter, either MEM or STANDBY
373  *
374  * Returns 0 if preparation was successful, otherwise returns error code
375  */
376 static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
378         struct device *dev = m3_ipc->dev;
379         int m3_power_state;
380         int ret = 0;
382         if (!wkup_m3_is_available(m3_ipc))
383                 return -ENODEV;
385         switch (state) {
386         case WKUP_M3_DEEPSLEEP:
387                 m3_power_state = IPC_CMD_DS0;
388                 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->volt_scale_offsets, 5);
389                 break;
390         case WKUP_M3_STANDBY:
391                 m3_power_state = IPC_CMD_STANDBY;
392                 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
393                 break;
394         case WKUP_M3_IDLE:
395                 m3_power_state = IPC_CMD_IDLE;
396                 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
397                 break;
398         default:
399                 return 1;
400         }
402         /* Program each required IPC register then write defaults to others */
403         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
404         wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
405         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type |
406                                m3_ipc->vtt_conf |
407                                m3_ipc->isolation_conf, 4);
408         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
409         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
410         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
411         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
413         m3_ipc->state = M3_STATE_MSG_FOR_LP;
415         if (state == WKUP_M3_IDLE)
416                 ret = wkup_m3_ping_noirq(m3_ipc);
417         else
418                 ret = wkup_m3_ping(m3_ipc);
420         if (ret) {
421                 dev_err(dev, "Unable to ping CM3\n");
422                 return ret;
423         }
425         return 0;
428 /**
429  * wkup_m3_finish_low_power - Return m3 to reset state
430  *
431  * Returns 0 if reset was successful, otherwise returns error code
432  */
433 static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
435         struct device *dev = m3_ipc->dev;
436         int ret = 0;
438         if (!wkup_m3_is_available(m3_ipc))
439                 return -ENODEV;
441         wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
442         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
444         m3_ipc->state = M3_STATE_MSG_FOR_RESET;
446         ret = wkup_m3_ping(m3_ipc);
447         if (ret) {
448                 dev_err(dev, "Unable to ping CM3\n");
449                 return ret;
450         }
452         return 0;
455 /**
456  * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
457  * @m3_ipc: Pointer to wkup_m3_ipc context
458  */
459 static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
461         unsigned int wakeup_src_idx;
462         int j, val;
464         val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
466         wakeup_src_idx = val & M3_WAKE_SRC_MASK;
468         for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
469                 if (wakeups[j].irq_nr == wakeup_src_idx)
470                         return wakeups[j].src;
471         }
472         return wakeups[j].src;
475 /**
476  * wkup_m3_set_rtc_only - Set the rtc_only flag
477  * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
478  *                  wakeup src value
479  */
480 static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
482         if (m3_ipc_state)
483                 m3_ipc_state->is_rtc_only = true;
486 static struct wkup_m3_ipc_ops ipc_ops = {
487         .set_mem_type = wkup_m3_set_mem_type,
488         .set_resume_address = wkup_m3_set_resume_address,
489         .prepare_low_power = wkup_m3_prepare_low_power,
490         .finish_low_power = wkup_m3_finish_low_power,
491         .request_pm_status = wkup_m3_request_pm_status,
492         .request_wake_src = wkup_m3_request_wake_src,
493         .set_rtc_only = wkup_m3_set_rtc_only,
494 };
496 /**
497  * wkup_m3_ipc_get - Return handle to wkup_m3_ipc
498  *
499  * Returns NULL if the wkup_m3 is not yet available, otherwise returns
500  * pointer to wkup_m3_ipc struct.
501  */
502 struct wkup_m3_ipc *wkup_m3_ipc_get(void)
504         if (m3_ipc_state)
505                 get_device(m3_ipc_state->dev);
506         else
507                 return NULL;
509         return m3_ipc_state;
511 EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
513 /**
514  * wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
515  * @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
516  */
517 void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
519         if (m3_ipc_state)
520                 put_device(m3_ipc_state->dev);
522 EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
524 static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc)
526         struct device *dev = m3_ipc->dev;
527         int ret;
529         init_completion(&m3_ipc->sync_complete);
531         ret = rproc_boot(m3_ipc->rproc);
532         if (ret)
533                 dev_err(dev, "rproc_boot failed\n");
535         do_exit(0);
538 static int wkup_m3_ipc_probe(struct platform_device *pdev)
540         struct device *dev = &pdev->dev;
541         int irq, ret, temp;
542         phandle rproc_phandle;
543         struct rproc *m3_rproc;
544         struct resource *res;
545         struct task_struct *task;
546         struct wkup_m3_ipc *m3_ipc;
547         struct device_node *np = dev->of_node;
549         m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
550         if (!m3_ipc)
551                 return -ENOMEM;
553         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
554         m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res);
555         if (IS_ERR(m3_ipc->ipc_mem_base)) {
556                 dev_err(dev, "could not ioremap ipc_mem\n");
557                 return PTR_ERR(m3_ipc->ipc_mem_base);
558         }
560         irq = platform_get_irq(pdev, 0);
561         if (!irq) {
562                 dev_err(&pdev->dev, "no irq resource\n");
563                 return -ENXIO;
564         }
566         ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
567                                0, "wkup_m3_txev", m3_ipc);
568         if (ret) {
569                 dev_err(dev, "request_irq failed\n");
570                 return ret;
571         }
573         m3_ipc->mbox_client.dev = dev;
574         m3_ipc->mbox_client.tx_done = NULL;
575         m3_ipc->mbox_client.tx_prepare = NULL;
576         m3_ipc->mbox_client.rx_callback = NULL;
577         m3_ipc->mbox_client.tx_block = false;
578         m3_ipc->mbox_client.knows_txdone = false;
580         m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
582         if (IS_ERR(m3_ipc->mbox)) {
583                 dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
584                         PTR_ERR(m3_ipc->mbox));
585                 return PTR_ERR(m3_ipc->mbox);
586         }
588         if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
589                 dev_err(&pdev->dev, "could not get rproc phandle\n");
590                 ret = -ENODEV;
591                 goto err_free_mbox;
592         }
594         m3_rproc = rproc_get_by_phandle(rproc_phandle);
595         if (!m3_rproc) {
596                 dev_err(&pdev->dev, "could not get rproc handle\n");
597                 ret = -EPROBE_DEFER;
598                 goto err_free_mbox;
599         }
601         m3_ipc->rproc = m3_rproc;
602         m3_ipc->dev = dev;
603         m3_ipc->state = M3_STATE_RESET;
605         m3_ipc->ops = &ipc_ops;
607         if (of_find_property(np, "ti,needs-vtt-toggle", NULL) &&
608             !(of_property_read_u32(np, "ti,vtt-gpio-pin", &temp))) {
609                 if (temp >= 0 && temp <= 31)
610                         wkup_m3_set_vtt_gpio(m3_ipc, temp);
611                 else
612                         dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp);
613         }
615         if (of_find_property(np, "ti,set-io-isolation", NULL))
616                 wkup_m3_set_io_isolation(m3_ipc);
618         ret = of_property_read_string(np, "ti,scale-data-fw",
619                                       &m3_ipc->sd_fw_name);
620         if (ret) {
621                 dev_dbg(dev, "Voltage scaling data blob not provided from DT.\n");
622         };
624         /*
625          * Wait for firmware loading completion in a thread so we
626          * can boot the wkup_m3 as soon as it's ready without holding
627          * up kernel boot
628          */
629         task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc,
630                            "wkup_m3_rproc_loader");
632         if (IS_ERR(task)) {
633                 dev_err(dev, "can't create rproc_boot thread\n");
634                 ret = PTR_ERR(task);
635                 goto err_put_rproc;
636         }
638         m3_ipc_state = m3_ipc;
640         return 0;
642 err_put_rproc:
643         rproc_put(m3_rproc);
644 err_free_mbox:
645         mbox_free_channel(m3_ipc->mbox);
646         return ret;
649 static int wkup_m3_ipc_remove(struct platform_device *pdev)
651         mbox_free_channel(m3_ipc_state->mbox);
653         rproc_shutdown(m3_ipc_state->rproc);
654         rproc_put(m3_ipc_state->rproc);
656         m3_ipc_state = NULL;
658         return 0;
661 static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
663         /*
664          * Nothing needs to be done on suspend even with rtc_only flag set
665          */
666         return 0;
669 static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
671         if (m3_ipc_state->is_rtc_only) {
672                 rproc_shutdown(m3_ipc_state->rproc);
673                 rproc_boot(m3_ipc_state->rproc);
674         }
676         m3_ipc_state->is_rtc_only = false;
678         return 0;
681 static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
682         SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
683 };
685 static const struct of_device_id wkup_m3_ipc_of_match[] = {
686         { .compatible = "ti,am3352-wkup-m3-ipc", },
687         { .compatible = "ti,am4372-wkup-m3-ipc", },
688         {},
689 };
690 MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
692 static struct platform_driver wkup_m3_ipc_driver = {
693         .probe = wkup_m3_ipc_probe,
694         .remove = wkup_m3_ipc_remove,
695         .driver = {
696                 .name = "wkup_m3_ipc",
697                 .of_match_table = wkup_m3_ipc_of_match,
698                 .pm = &wkup_m3_ipc_pm_ops,
699         },
700 };
702 module_platform_driver(wkup_m3_ipc_driver);
704 MODULE_LICENSE("GPL v2");
705 MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
706 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");