soc: ti: wkup_m3_ipc: Fix race condition with rproc_boot
[rpmsg/hwspinlock.git] / drivers / soc / ti / wkup_m3_ipc.c
1 /*
2  * AMx3 Wkup M3 IPC driver
3  *
4  * Copyright (C) 2015 Texas Instruments, Inc.
5  *
6  * Dave Gerlach <d-gerlach@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
18 #include <linux/err.h>
19 #include <linux/firmware.h>
20 #include <linux/kernel.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/omap-mailbox.h>
27 #include <linux/platform_device.h>
28 #include <linux/remoteproc.h>
29 #include <linux/suspend.h>
30 #include <linux/wkup_m3_ipc.h>
32 #define AM33XX_CTRL_IPC_REG_COUNT       0x8
33 #define AM33XX_CTRL_IPC_REG_OFFSET(m)   (0x4 + 4 * (m))
35 /* AM33XX M3_TXEV_EOI register */
36 #define AM33XX_CONTROL_M3_TXEV_EOI      0x00
38 #define AM33XX_M3_TXEV_ACK              (0x1 << 0)
39 #define AM33XX_M3_TXEV_ENABLE           (0x0 << 0)
41 #define IPC_CMD_DS0                     0x4
42 #define IPC_CMD_STANDBY                 0xc
43 #define IPC_CMD_IDLE                    0x10
44 #define IPC_CMD_RESET                   0xe
45 #define DS_IPC_DEFAULT                  0xffffffff
46 #define M3_VERSION_UNKNOWN              0x0000ffff
47 #define M3_BASELINE_VERSION             0x191
48 #define M3_STATUS_RESP_MASK             (0xffff << 16)
49 #define M3_FW_VERSION_MASK              0xffff
50 #define M3_WAKE_SRC_MASK                0xff
52 #define IPC_MEM_TYPE_SHIFT              (0x0)
53 #define IPC_MEM_TYPE_MASK               (0x7 << 0)
54 #define IPC_VTT_STAT_SHIFT              (0x3)
55 #define IPC_VTT_STAT_MASK               (0x1 << 3)
56 #define IPC_VTT_GPIO_PIN_SHIFT          (0x4)
57 #define IPC_VTT_GPIO_PIN_MASK           (0x3f << 4)
58 #define IPC_IO_ISOLATION_STAT_SHIFT     (10)
59 #define IPC_IO_ISOLATION_STAT_MASK      (0x1 << 10)
61 #define M3_STATE_UNKNOWN                0
62 #define M3_STATE_RESET                  1
63 #define M3_STATE_INITED                 2
64 #define M3_STATE_MSG_FOR_LP             3
65 #define M3_STATE_MSG_FOR_RESET          4
67 #define WKUP_M3_SD_FW_MAGIC             0x570C
69 #define WKUP_M3_DMEM_START              0x80000
70 #define WKUP_M3_AUXDATA_OFFSET          0x1000
71 #define WKUP_M3_AUXDATA_SIZE            0xFF
73 static struct wkup_m3_ipc *m3_ipc_state;
75 static const struct wkup_m3_wakeup_src wakeups[] = {
76         {.irq_nr = 16,  .src = "PRCM"},
77         {.irq_nr = 35,  .src = "USB0_PHY"},
78         {.irq_nr = 36,  .src = "USB1_PHY"},
79         {.irq_nr = 40,  .src = "I2C0"},
80         {.irq_nr = 41,  .src = "RTC Timer"},
81         {.irq_nr = 42,  .src = "RTC Alarm"},
82         {.irq_nr = 43,  .src = "Timer0"},
83         {.irq_nr = 44,  .src = "Timer1"},
84         {.irq_nr = 45,  .src = "UART"},
85         {.irq_nr = 46,  .src = "GPIO0"},
86         {.irq_nr = 48,  .src = "MPU_WAKE"},
87         {.irq_nr = 49,  .src = "WDT0"},
88         {.irq_nr = 50,  .src = "WDT1"},
89         {.irq_nr = 51,  .src = "ADC_TSC"},
90         {.irq_nr = 0,   .src = "Unknown"},
91 };
93 /**
94  * wkup_m3_copy_aux_data - Copy auxiliary data to special region of m3 dmem
95  * @data - pointer to data
96  * @sz - size of data to copy (limit 256 bytes)
97  *
98  * Copies any additional blob of data to the wkup_m3 dmem to be used by the
99  * firmware
100  */
101 static unsigned long wkup_m3_copy_aux_data(struct wkup_m3_ipc *m3_ipc,
102                                            const void *data, int sz)
104         unsigned long aux_data_dev_addr;
105         void *aux_data_addr;
107         aux_data_dev_addr = WKUP_M3_DMEM_START + WKUP_M3_AUXDATA_OFFSET;
108         aux_data_addr = rproc_da_to_va(m3_ipc->rproc,
109                                        aux_data_dev_addr,
110                                        WKUP_M3_AUXDATA_SIZE);
111         memcpy(aux_data_addr, data, sz);
113         return WKUP_M3_AUXDATA_OFFSET;
116 static void wkup_m3_scale_data_fw_cb(const struct firmware *fw, void *context)
118         unsigned long val, aux_base;
119         struct wkup_m3_scale_data_header hdr;
120         struct wkup_m3_ipc *m3_ipc = context;
121         struct device *dev = m3_ipc->dev;
123         if (!fw) {
124                 dev_err(dev, "Voltage scale fw name given but file missing.\n");
125                 return;
126         }
128         memcpy(&hdr, fw->data, sizeof(hdr));
130         if (hdr.magic != WKUP_M3_SD_FW_MAGIC) {
131                 dev_err(dev, "PM: Voltage Scale Data binary does not appear valid.\n");
132                 goto release_sd_fw;
133         }
135         aux_base = wkup_m3_copy_aux_data(m3_ipc, fw->data + sizeof(hdr),
136                                          fw->size - sizeof(hdr));
138         val = (aux_base + hdr.sleep_offset);
139         val |= ((aux_base + hdr.wake_offset) << 16);
141         m3_ipc->volt_scale_offsets = val;
143 release_sd_fw:
144         release_firmware(fw);
145 };
147 static int wkup_m3_init_scale_data(struct wkup_m3_ipc *m3_ipc,
148                                    struct device *dev)
150         int ret = 0;
152         /*
153          * If no name is provided, user has already been warned, pm will
154          * still work so return 0
155          */
157         if (!m3_ipc->sd_fw_name)
158                 return ret;
160         ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
161                                       m3_ipc->sd_fw_name, dev, GFP_ATOMIC,
162                                       m3_ipc, wkup_m3_scale_data_fw_cb);
164         return ret;
167 static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
169         writel(AM33XX_M3_TXEV_ACK,
170                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
173 static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
175         writel(AM33XX_M3_TXEV_ENABLE,
176                m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
179 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
180                                    u32 val, int ipc_reg_num)
182         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
183                  "ipc register operation out of range"))
184                 return;
186         writel(val, m3_ipc->ipc_mem_base +
187                AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
190 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
191                                           int ipc_reg_num)
193         if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
194                  "ipc register operation out of range"))
195                 return 0;
197         return readl(m3_ipc->ipc_mem_base +
198                      AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
201 static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
203         int val;
205         val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
207         return val & M3_FW_VERSION_MASK;
210 static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
212         struct wkup_m3_ipc *m3_ipc = ipc_data;
213         struct device *dev = m3_ipc->dev;
214         int ver = 0;
216         am33xx_txev_eoi(m3_ipc);
218         switch (m3_ipc->state) {
219         case M3_STATE_RESET:
220                 ver = wkup_m3_fw_version_read(m3_ipc);
222                 if (ver == M3_VERSION_UNKNOWN ||
223                     ver < M3_BASELINE_VERSION) {
224                         dev_warn(dev, "CM3 Firmware Version %x not supported\n",
225                                  ver);
226                 } else {
227                         dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
228                 }
230                 m3_ipc->state = M3_STATE_INITED;
231                 wkup_m3_init_scale_data(m3_ipc, dev);
232                 complete(&m3_ipc->sync_complete);
233                 break;
234         case M3_STATE_MSG_FOR_RESET:
235                 m3_ipc->state = M3_STATE_INITED;
236                 complete(&m3_ipc->sync_complete);
237                 break;
238         case M3_STATE_MSG_FOR_LP:
239                 complete(&m3_ipc->sync_complete);
240                 break;
241         case M3_STATE_UNKNOWN:
242                 dev_warn(dev, "Unknown CM3 State\n");
243         }
245         am33xx_txev_enable(m3_ipc);
247         return IRQ_HANDLED;
250 static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
252         struct device *dev = m3_ipc->dev;
253         mbox_msg_t dummy_msg = 0;
254         int ret;
256         if (!m3_ipc->mbox) {
257                 dev_err(dev,
258                         "No IPC channel to communicate with wkup_m3!\n");
259                 return -EIO;
260         }
262         /*
263          * Write a dummy message to the mailbox in order to trigger the RX
264          * interrupt to alert the M3 that data is available in the IPC
265          * registers. We must enable the IRQ here and disable it after in
266          * the RX callback to avoid multiple interrupts being received
267          * by the CM3.
268          */
269         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
270         if (ret < 0) {
271                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
272                         __func__, ret);
273                 return ret;
274         }
276         ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
277                                           msecs_to_jiffies(500));
278         if (!ret) {
279                 dev_err(dev, "MPU<->CM3 sync failure\n");
280                 m3_ipc->state = M3_STATE_UNKNOWN;
281                 return -EIO;
282         }
284         mbox_client_txdone(m3_ipc->mbox, 0);
285         return 0;
288 static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
290         struct device *dev = m3_ipc->dev;
291         mbox_msg_t dummy_msg = 0;
292         int ret;
294         if (!m3_ipc->mbox) {
295                 dev_err(dev,
296                         "No IPC channel to communicate with wkup_m3!\n");
297                 return -EIO;
298         }
300         ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
301         if (ret < 0) {
302                 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
303                         __func__, ret);
304                 return ret;
305         }
307         mbox_client_txdone(m3_ipc->mbox, 0);
308         return 0;
311 static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
313         return ((m3_ipc->state != M3_STATE_RESET) &&
314                 (m3_ipc->state != M3_STATE_UNKNOWN));
317 static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m3_ipc, int gpio)
319         m3_ipc->vtt_conf = (1 << IPC_VTT_STAT_SHIFT) |
320                             (gpio << IPC_VTT_GPIO_PIN_SHIFT);
323 static void wkup_m3_set_io_isolation(struct wkup_m3_ipc *m3_ipc)
325         m3_ipc->isolation_conf = (1 << IPC_IO_ISOLATION_STAT_SHIFT);
328 /* Public functions */
329 /**
330  * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
331  * @mem_type: memory type value read directly from emif
332  *
333  * wkup_m3 must know what memory type is in use to properly suspend
334  * and resume.
335  */
336 static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
338         m3_ipc->mem_type = mem_type;
341 /**
342  * wkup_m3_set_resume_address - Pass wkup_m3 resume address
343  * @addr: Physical address from which resume code should execute
344  */
345 static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
347         m3_ipc->resume_addr = (unsigned long)addr;
350 /**
351  * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
352  *
353  * Returns code representing the status of a low power mode transition.
354  *      0 - Successful transition
355  *      1 - Failure to transition to low power state
356  */
357 static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
359         unsigned int i;
360         int val;
362         val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
364         i = M3_STATUS_RESP_MASK & val;
365         i >>= __ffs(M3_STATUS_RESP_MASK);
367         return i;
370 /**
371  * wkup_m3_prepare_low_power - Request preparation for transition to
372  *                             low power state
373  * @state: A kernel suspend state to enter, either MEM or STANDBY
374  *
375  * Returns 0 if preparation was successful, otherwise returns error code
376  */
377 static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
379         struct device *dev = m3_ipc->dev;
380         int m3_power_state;
381         int ret = 0;
383         if (!wkup_m3_is_available(m3_ipc))
384                 return -ENODEV;
386         switch (state) {
387         case WKUP_M3_DEEPSLEEP:
388                 m3_power_state = IPC_CMD_DS0;
389                 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->volt_scale_offsets, 5);
390                 break;
391         case WKUP_M3_STANDBY:
392                 m3_power_state = IPC_CMD_STANDBY;
393                 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
394                 break;
395         case WKUP_M3_IDLE:
396                 m3_power_state = IPC_CMD_IDLE;
397                 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
398                 break;
399         default:
400                 return 1;
401         }
403         /* Program each required IPC register then write defaults to others */
404         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
405         wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
406         wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type |
407                                m3_ipc->vtt_conf |
408                                m3_ipc->isolation_conf, 4);
409         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
410         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
411         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
412         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
414         m3_ipc->state = M3_STATE_MSG_FOR_LP;
416         if (state == WKUP_M3_IDLE)
417                 ret = wkup_m3_ping_noirq(m3_ipc);
418         else
419                 ret = wkup_m3_ping(m3_ipc);
421         if (ret) {
422                 dev_err(dev, "Unable to ping CM3\n");
423                 return ret;
424         }
426         return 0;
429 /**
430  * wkup_m3_finish_low_power - Return m3 to reset state
431  *
432  * Returns 0 if reset was successful, otherwise returns error code
433  */
434 static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
436         struct device *dev = m3_ipc->dev;
437         int ret = 0;
439         if (!wkup_m3_is_available(m3_ipc))
440                 return -ENODEV;
442         wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
443         wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
445         m3_ipc->state = M3_STATE_MSG_FOR_RESET;
447         ret = wkup_m3_ping(m3_ipc);
448         if (ret) {
449                 dev_err(dev, "Unable to ping CM3\n");
450                 return ret;
451         }
453         return 0;
456 /**
457  * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
458  * @m3_ipc: Pointer to wkup_m3_ipc context
459  */
460 static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
462         unsigned int wakeup_src_idx;
463         int j, val;
465         val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
467         wakeup_src_idx = val & M3_WAKE_SRC_MASK;
469         for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
470                 if (wakeups[j].irq_nr == wakeup_src_idx)
471                         return wakeups[j].src;
472         }
473         return wakeups[j].src;
476 /**
477  * wkup_m3_set_rtc_only - Set the rtc_only flag
478  * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
479  *                  wakeup src value
480  */
481 static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
483         if (m3_ipc_state)
484                 m3_ipc_state->is_rtc_only = true;
487 static struct wkup_m3_ipc_ops ipc_ops = {
488         .set_mem_type = wkup_m3_set_mem_type,
489         .set_resume_address = wkup_m3_set_resume_address,
490         .prepare_low_power = wkup_m3_prepare_low_power,
491         .finish_low_power = wkup_m3_finish_low_power,
492         .request_pm_status = wkup_m3_request_pm_status,
493         .request_wake_src = wkup_m3_request_wake_src,
494         .set_rtc_only = wkup_m3_set_rtc_only,
495 };
497 /**
498  * wkup_m3_ipc_get - Return handle to wkup_m3_ipc
499  *
500  * Returns NULL if the wkup_m3 is not yet available, otherwise returns
501  * pointer to wkup_m3_ipc struct.
502  */
503 struct wkup_m3_ipc *wkup_m3_ipc_get(void)
505         if (m3_ipc_state)
506                 get_device(m3_ipc_state->dev);
507         else
508                 return NULL;
510         return m3_ipc_state;
512 EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
514 /**
515  * wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
516  * @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
517  */
518 void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
520         if (m3_ipc_state)
521                 put_device(m3_ipc_state->dev);
523 EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
525 static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc)
527         struct device *dev = m3_ipc->dev;
528         int ret;
530         init_completion(&m3_ipc->sync_complete);
532         ret = rproc_boot(m3_ipc->rproc);
533         if (ret)
534                 dev_err(dev, "rproc_boot failed\n");
535         else
536                 m3_ipc_state = m3_ipc;
538         do_exit(0);
541 static int wkup_m3_ipc_probe(struct platform_device *pdev)
543         struct device *dev = &pdev->dev;
544         int irq, ret, temp;
545         phandle rproc_phandle;
546         struct rproc *m3_rproc;
547         struct resource *res;
548         struct task_struct *task;
549         struct wkup_m3_ipc *m3_ipc;
550         struct device_node *np = dev->of_node;
552         m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
553         if (!m3_ipc)
554                 return -ENOMEM;
556         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557         m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res);
558         if (IS_ERR(m3_ipc->ipc_mem_base)) {
559                 dev_err(dev, "could not ioremap ipc_mem\n");
560                 return PTR_ERR(m3_ipc->ipc_mem_base);
561         }
563         irq = platform_get_irq(pdev, 0);
564         if (!irq) {
565                 dev_err(&pdev->dev, "no irq resource\n");
566                 return -ENXIO;
567         }
569         ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
570                                0, "wkup_m3_txev", m3_ipc);
571         if (ret) {
572                 dev_err(dev, "request_irq failed\n");
573                 return ret;
574         }
576         m3_ipc->mbox_client.dev = dev;
577         m3_ipc->mbox_client.tx_done = NULL;
578         m3_ipc->mbox_client.tx_prepare = NULL;
579         m3_ipc->mbox_client.rx_callback = NULL;
580         m3_ipc->mbox_client.tx_block = false;
581         m3_ipc->mbox_client.knows_txdone = false;
583         m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
585         if (IS_ERR(m3_ipc->mbox)) {
586                 dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
587                         PTR_ERR(m3_ipc->mbox));
588                 return PTR_ERR(m3_ipc->mbox);
589         }
591         if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
592                 dev_err(&pdev->dev, "could not get rproc phandle\n");
593                 ret = -ENODEV;
594                 goto err_free_mbox;
595         }
597         m3_rproc = rproc_get_by_phandle(rproc_phandle);
598         if (!m3_rproc) {
599                 dev_err(&pdev->dev, "could not get rproc handle\n");
600                 ret = -EPROBE_DEFER;
601                 goto err_free_mbox;
602         }
604         m3_ipc->rproc = m3_rproc;
605         m3_ipc->dev = dev;
606         m3_ipc->state = M3_STATE_RESET;
608         m3_ipc->ops = &ipc_ops;
610         if (of_find_property(np, "ti,needs-vtt-toggle", NULL) &&
611             !(of_property_read_u32(np, "ti,vtt-gpio-pin", &temp))) {
612                 if (temp >= 0 && temp <= 31)
613                         wkup_m3_set_vtt_gpio(m3_ipc, temp);
614                 else
615                         dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp);
616         }
618         if (of_find_property(np, "ti,set-io-isolation", NULL))
619                 wkup_m3_set_io_isolation(m3_ipc);
621         ret = of_property_read_string(np, "ti,scale-data-fw",
622                                       &m3_ipc->sd_fw_name);
623         if (ret) {
624                 dev_dbg(dev, "Voltage scaling data blob not provided from DT.\n");
625         };
627         /*
628          * Wait for firmware loading completion in a thread so we
629          * can boot the wkup_m3 as soon as it's ready without holding
630          * up kernel boot
631          */
632         task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc,
633                            "wkup_m3_rproc_loader");
635         if (IS_ERR(task)) {
636                 dev_err(dev, "can't create rproc_boot thread\n");
637                 ret = PTR_ERR(task);
638                 goto err_put_rproc;
639         }
641         return 0;
643 err_put_rproc:
644         rproc_put(m3_rproc);
645 err_free_mbox:
646         mbox_free_channel(m3_ipc->mbox);
647         return ret;
650 static int wkup_m3_ipc_remove(struct platform_device *pdev)
652         mbox_free_channel(m3_ipc_state->mbox);
654         rproc_shutdown(m3_ipc_state->rproc);
655         rproc_put(m3_ipc_state->rproc);
657         m3_ipc_state = NULL;
659         return 0;
662 static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
664         /*
665          * Nothing needs to be done on suspend even with rtc_only flag set
666          */
667         return 0;
670 static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
672         if (m3_ipc_state->is_rtc_only) {
673                 rproc_shutdown(m3_ipc_state->rproc);
674                 rproc_boot(m3_ipc_state->rproc);
675         }
677         m3_ipc_state->is_rtc_only = false;
679         return 0;
682 static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
683         SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
684 };
686 static const struct of_device_id wkup_m3_ipc_of_match[] = {
687         { .compatible = "ti,am3352-wkup-m3-ipc", },
688         { .compatible = "ti,am4372-wkup-m3-ipc", },
689         {},
690 };
691 MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
693 static struct platform_driver wkup_m3_ipc_driver = {
694         .probe = wkup_m3_ipc_probe,
695         .remove = wkup_m3_ipc_remove,
696         .driver = {
697                 .name = "wkup_m3_ipc",
698                 .of_match_table = wkup_m3_ipc_of_match,
699                 .pm = &wkup_m3_ipc_pm_ops,
700         },
701 };
703 module_platform_driver(wkup_m3_ipc_driver);
705 MODULE_LICENSE("GPL v2");
706 MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
707 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");