ARM: dts: dra762: Add MCAN clock support

[rpmsg/hwspinlock.git] / arch / arm / boot / dts / dra76x.dtsi

diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
index 1c88c581ff18879a4991f3a77634e3b998d56b3d..bfc82636999c95585164ae473bc5af413953af79 100644 (file)
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -17,3 +17,36 @@
 &crossbar_mpu {
        ti,irqs-skip = <10 67 68 133 139 140>;
 };
+
+&scm_conf_clocks {
+       dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_gmac_x2_ck>;
+               ti,max-div = <63>;
+               reg = <0x03fc>;
+               ti,bit-shift=<20>;
+               ti,latch-bit=<26>;
+               assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
+               assigned-clock-rates = <80000000>;
+       };
+
+       dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
+               reg = <0x3fc>;
+               ti,bit-shift = <29>;
+               ti,latch-bit=<26>;
+               assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+               assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
+       };
+
+       mcan_clk: mcan_clk@3fc {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+               ti,bit-shift = <27>;
+               reg = <0x3fc>;
+       };
+};