author | Suman Anna <s-anna@ti.com> | |
Fri, 15 Nov 2013 20:03:09 +0000 (14:03 -0600) | ||
committer | Suman Anna <s-anna@ti.com> | |
Mon, 18 Nov 2013 23:00:44 +0000 (17:00 -0600) | ||
commit | b3ab081586a062cb5ef67c547e32a1a5e81d77df | |
tree | f824c5060cfc5b7678d9453f2e1cab95d458ef51 | tree | snapshot (tar.xz tar.gz zip) |
parent | 7dd72f9de71649210c0563f82b7565ef867ac0fa | commit | diff |
parent | f8f9a8c38644d27dc8671009209922531b072110 | commit | diff |
Merge branch 'platform-ti-linux-3.12.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into HEAD
Merge platform base tree to bring in SoC support for OMAP5, DRA7 and AM4372.
This is required to add/enable the necessary hwspinlock support on these SoCs.
The boot on DRA7xx/AM4372 with this branch requires a ramdisk, a MMC-based
filesystem support is only available in branch ti-linux-3.12.y of integration
tree, git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git
* 'platform-ti-linux-3.12.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (187 commits)
ARM: omap: edma: add suspend suspend/resume hooks(v4-modified)
ARM: AM43xx: clk: Change the wdt1 func clk src to per_32k clk
ARM: AM43xx: clk: Add a comment for not using "clk_rc32k_ck"
ARM: AM33xx: clk: Add a comment for not using "clk_rc32k_ck"
ARM: OMAP5/DRA7: hwmod: Add HWMOD_SWSUP_SIDLE_ACT flag for non WKUP domain timers
ARM: DRA7: hwmod: Remove the duplicate omap_hwmod_class structs
ARM: OMAP5: hwmod: Fix the omap_hwmod_class structs for timer1/2/10
ARM: dts: DRA7: Pass the timer clock source info from DT
ARM: dts: OMAP5: Pass the timer clock source info from DT
ARM: OMAP2+: hwmod: Correct oh->opt_clks_cnt in case of DT boot
ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only
ARM: dts: AM4372: Enable watchdog for AM4372 SoC
ARM: OMAP: Disable POSTED mode for errata i103 and i767
crypto: omap-aes: Fix CTR mode counter length
OMAP: AM33xx: hwmod: Correct AES module SYSC type
ARM: dts: OMAP4: Add node for DES3DES module
ARM: dts: OMAP4: Add node for AES
ARM: OMAP4: hwmod: add hwmod data for DES IP
ARM: OMAP4: hwmod: Add hwmod data for AES IP
ARM: dts: DRA7: Add DT node for AES IP
...
Signed-off-by: Suman Anna <s-anna@ti.com>
Conflicts:
arch/arm/boot/dts/am33xx.dtsi
arch/arm/common/edma.c
arch/arm/kernel/head.S
Merge platform base tree to bring in SoC support for OMAP5, DRA7 and AM4372.
This is required to add/enable the necessary hwspinlock support on these SoCs.
The boot on DRA7xx/AM4372 with this branch requires a ramdisk, a MMC-based
filesystem support is only available in branch ti-linux-3.12.y of integration
tree, git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git
* 'platform-ti-linux-3.12.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (187 commits)
ARM: omap: edma: add suspend suspend/resume hooks(v4-modified)
ARM: AM43xx: clk: Change the wdt1 func clk src to per_32k clk
ARM: AM43xx: clk: Add a comment for not using "clk_rc32k_ck"
ARM: AM33xx: clk: Add a comment for not using "clk_rc32k_ck"
ARM: OMAP5/DRA7: hwmod: Add HWMOD_SWSUP_SIDLE_ACT flag for non WKUP domain timers
ARM: DRA7: hwmod: Remove the duplicate omap_hwmod_class structs
ARM: OMAP5: hwmod: Fix the omap_hwmod_class structs for timer1/2/10
ARM: dts: DRA7: Pass the timer clock source info from DT
ARM: dts: OMAP5: Pass the timer clock source info from DT
ARM: OMAP2+: hwmod: Correct oh->opt_clks_cnt in case of DT boot
ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only
ARM: dts: AM4372: Enable watchdog for AM4372 SoC
ARM: OMAP: Disable POSTED mode for errata i103 and i767
crypto: omap-aes: Fix CTR mode counter length
OMAP: AM33xx: hwmod: Correct AES module SYSC type
ARM: dts: OMAP4: Add node for DES3DES module
ARM: dts: OMAP4: Add node for AES
ARM: OMAP4: hwmod: add hwmod data for DES IP
ARM: OMAP4: hwmod: Add hwmod data for AES IP
ARM: dts: DRA7: Add DT node for AES IP
...
Signed-off-by: Suman Anna <s-anna@ti.com>
Conflicts:
arch/arm/boot/dts/am33xx.dtsi
arch/arm/common/edma.c
arch/arm/kernel/head.S
13 files changed: