arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Wed, 28 Nov 2018 10:48:15 +0000 (12:48 +0200)
committerTero Kristo <t-kristo@ti.com>
Wed, 28 Nov 2018 10:52:32 +0000 (12:52 +0200)
Add nodes and sub nodes for both NAVSS (main and mcu) and add the PDMA
nodes as well.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
arch/arm64/boot/dts/ti/k3-am65.dtsi

index b69e6b128db642b1e505ef1ab90298851b054f6a..60096565744d24dab3e28425fd5ee11c9ea3d4b2 100644 (file)
                ti,sci-rm-range-girq = <0x1>;
        };
 
-       main_navss_intr: interrupt-controller1 {
-               compatible = "ti,sci-intr";
-               interrupt-controller;
-               interrupt-parent = <&gic500>;
-               #interrupt-cells = <3>;
-               ti,sci = <&dmsc>;
-               ti,sci-dst-id = <56>;
-               ti,sci-rm-range-girq = <0x0>,
-                                      <0x2>;
+       main_navss: main_navss {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dma-coherent;
+               dma-ranges;
+               ranges;
+
+               ti,sci-dev-id = <118>;
+
+               main_navss_intr: interrupt-controller1 {
+                       compatible = "ti,sci-intr";
+                       interrupt-controller;
+                       interrupt-parent = <&gic500>;
+                       #interrupt-cells = <3>;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dst-id = <56>;
+                       ti,sci-rm-range-girq = <0x0>,
+                                              <0x2>;
+               };
+
+               main_udmass_inta: interrupt-controller@33d00000 {
+                       compatible = "ti,sci-inta";
+                       reg = <0x0 0x33d00000 0x0 0x100000>;
+                       interrupt-controller;
+                       interrupt-parent = <&main_navss_intr>;
+                       #interrupt-cells = <3>;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <179>;
+                       ti,sci-rm-range-vint = <0x0>;
+                       ti,sci-rm-range-global-event = <0x1>;
+               };
+
+               ringacc: ringacc@3c000000 {
+                       compatible = "ti,am654-navss-ringacc";
+                       reg =   <0x0 0x3c000000 0x0 0x400000>,
+                               <0x0 0x38000000 0x0 0x400000>,
+                               <0x0 0x31120000 0x0 0x100>,
+                               <0x0 0x33000000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+                       ti,num-rings = <818>;
+                       ti,gp-rings = <304 464>; /* start, cnt */
+                       ti,dma-ring-reset-quirk;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <187>;
+                       interrupt-parent = <&main_udmass_inta>;
+               };
+
+               main_udmap: udmap@31150000 {
+                       compatible = "ti,am654-navss-main-udmap";
+                       reg =   <0x0 0x31150000 0x0 0x100>,
+                               <0x0 0x34000000 0x0 0x100000>,
+                               <0x0 0x35000000 0x0 0x100000>;
+                       reg-names = "gcfg", "rchanrt", "tchanrt";
+                       #dma-cells = <3>;
+
+                       ti,ringacc = <&ringacc>;
+                       ti,psil-base = <0x1000>;
+
+                       interrupt-parent = <&main_udmass_inta>;
+
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <188>;
+
+                       ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
+                                               <0x2>; /* TX_CHAN */
+                       ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
+                                               <0x5>; /* RX_CHAN */
+                       ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
+               };
        };
 
-       main_udmass_inta: interrupt-controller@33d00000 {
-               compatible = "ti,sci-inta";
-               reg = <0x0 0x33d00000 0x0 0x100000>;
-               interrupt-controller;
-               interrupt-parent = <&main_navss_intr>;
-               #interrupt-cells = <3>;
-               ti,sci = <&dmsc>;
-               ti,sci-dev-id = <179>;
-               ti,sci-rm-range-vint = <0x0>;
-               ti,sci-rm-range-global-event = <0x1>;
+       pdma0: pdma@2a41000 {
+               compatible = "ti,am654-pdma";
+               reg = <0x0 0x02A41000 0x0 0x400>;
+               reg-names = "eccaggr_cfg";
+
+               ti,psil-base = <0x4400>;
+
+               /* ti,psil-config0-2 */
+               UDMA_PDMA_TR_XY(0);
+               UDMA_PDMA_TR_XY(1);
+               UDMA_PDMA_TR_XY(2);
+       };
+
+       pdma1: pdma@2a42000 {
+               compatible = "ti,am654-pdma";
+               reg = <0x0 0x02A42000 0x0 0x400>;
+               reg-names = "eccaggr_cfg";
+
+               ti,psil-base = <0x4500>;
+
+               /* ti,psil-config0-22 */
+               UDMA_PDMA_TR_XY(0);
+               UDMA_PDMA_TR_XY(1);
+               UDMA_PDMA_TR_XY(2);
+               UDMA_PDMA_TR_XY(3);
+               UDMA_PDMA_TR_XY(4);
+               UDMA_PDMA_TR_XY(5);
+               UDMA_PDMA_TR_XY(6);
+               UDMA_PDMA_TR_XY(7);
+               UDMA_PDMA_TR_XY(8);
+               UDMA_PDMA_TR_XY(9);
+               UDMA_PDMA_TR_XY(10);
+               UDMA_PDMA_TR_XY(11);
+               UDMA_PDMA_TR_XY(12);
+               UDMA_PDMA_TR_XY(13);
+               UDMA_PDMA_TR_XY(14);
+               UDMA_PDMA_TR_XY(15);
+               UDMA_PDMA_TR_XY(16);
+               UDMA_PDMA_TR_XY(17);
+               UDMA_PDMA_TR_XY(18);
+               UDMA_PDMA_TR_XY(19);
+               UDMA_PDMA_PKT_XY(20);
+               UDMA_PDMA_PKT_XY(21);
+               UDMA_PDMA_PKT_XY(22);
        };
 
        main_pmx0: pinmux@11c000 {
index 1fd027748e1fa525922f412fa866f1ed7c2f9dfb..6788b2716e51a019d5694d04e5ae4b3486f43205 100644 (file)
                clocks = <&k3_clks 114 1>;
                power-domains = <&k3_pds 114>;
        };
+
+       mcu_navss: mcu_navss {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dma-coherent;
+               dma-ranges;
+               ranges;
+
+               ti,sci-dev-id = <119>;
+
+               mcu_ringacc: ringacc@2b800000 {
+                       compatible = "ti,am654-navss-ringacc";
+                       reg =   <0x0 0x2b800000 0x0 0x400000>,
+                               <0x0 0x2b000000 0x0 0x400000>,
+                               <0x0 0x28590000 0x0 0x100>,
+                               <0x0 0x2a500000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+                       ti,num-rings = <286>;
+                       ti,gp-rings = <96 255>; /* start, cnt */
+                       ti,dma-ring-reset-quirk;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <195>;
+                       interrupt-parent = <&main_udmass_inta>;
+               };
+
+               mcu_udmap: udmap@31150000 {
+                       compatible = "ti,am654-navss-mcu-udmap";
+                       reg =   <0x0 0x285c0000 0x0 0x100>,
+                               <0x0 0x2a800000 0x0 0x40000>,
+                               <0x0 0x2aa00000 0x0 0x40000>;
+                       reg-names = "gcfg", "rchanrt", "tchanrt";
+                       #dma-cells = <3>;
+
+                       ti,ringacc = <&mcu_ringacc>;
+                       ti,psil-base = <0x6000>;
+
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <194>;
+
+                       ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
+                                               <0x2>; /* TX_CHAN */
+                       ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
+                                               <0x4>; /* RX_CHAN */
+                       ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
+
+                       interrupt-parent = <&main_udmass_inta>;
+               };
+       };
+
+       mcu_pdma0: pdma@40710000 {
+               compatible = "ti,am654-pdma";
+               reg = <0x0 0x40710000 0x0 0x400>;
+               reg-names = "eccaggr_cfg";
+
+               ti,psil-base = <0x7100>;
+
+               /* ti,psil-config0-3 */
+               UDMA_PDMA_TR_XY(0);
+               UDMA_PDMA_TR_XY(1);
+               UDMA_PDMA_TR_XY(2);
+               UDMA_PDMA_TR_XY(3);
+       };
+
+       mcu_pdma1: pdma@40711000 {
+               compatible = "ti,am654-pdma";
+               reg = <0x0 0x40711000 0x0 0x400>;
+               reg-names = "eccaggr_cfg";
+
+               ti,psil-base = <0x7200>;
+
+               /* ti,psil-config18 */
+               UDMA_PDMA_PKT_XY(18);
+       };
 };
index b4af7e605a9dedf3cb8dc9bdb6be602ba0573144..7cf390860225aaa07c9c6abfe780e8f0b2bae492 100644 (file)
@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/k3.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/dma/k3-udma.h>
 
 / {
        model = "Texas Instruments K3 AM654 SoC";