ARM: OMAP2+: am43xx: Add lcdc clockdomain
authorDave Gerlach <d-gerlach@ti.com>
Fri, 2 Nov 2018 10:30:48 +0000 (16:00 +0530)
committerTero Kristo <t-kristo@ti.com>
Tue, 6 Nov 2018 13:26:13 +0000 (15:26 +0200)
As described in AM437x TRM, spruhl7f, Revised September 2016, there is
an LCDC clockdomain present in the PER power domain. Although it is
entirely unused on AM437x, it should be defined along with the other
clockdomains so it can be shut off by Linux as there are no users.

Reported-by: Munan Xu <munan@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
arch/arm/mach-omap2/clockdomains43xx_data.c
arch/arm/mach-omap2/prcm43xx.h

index 6d71c6082a247a37c13326982494615f63a86591..237a0157bccf94664df3f5cb49ffbf95ce0c542c 100644 (file)
@@ -87,6 +87,15 @@ static struct clockdomain l3s_tsc_43xx_clkdm = {
        .flags            = CLKDM_CAN_SWSUP,
 };
 
+static struct clockdomain lcdc_43xx_clkdm = {
+       .name             = "lcdc_clkdm",
+       .pwrdm            = { .name = "per_pwrdm" },
+       .prcm_partition   = AM43XX_CM_PARTITION,
+       .cm_inst          = AM43XX_CM_PER_INST,
+       .clkdm_offs       = AM43XX_CM_PER_LCDC_CDOFFS,
+       .flags            = CLKDM_CAN_SWSUP,
+};
+
 static struct clockdomain dss_43xx_clkdm = {
        .name             = "dss_clkdm",
        .pwrdm            = { .name = "per_pwrdm" },
@@ -176,6 +185,7 @@ static struct clockdomain *clockdomains_am43xx[] __initdata = {
        &pruss_ocp_43xx_clkdm,
        &ocpwp_l3_43xx_clkdm,
        &l3s_tsc_43xx_clkdm,
+       &lcdc_43xx_clkdm,
        &dss_43xx_clkdm,
        &l3_aon_43xx_clkdm,
        &emif_43xx_clkdm,
index e2ad14e77064ccd6cb15fd3140b9a274b9042cde..7078a61c1d3fc25328834881770c1f2f6dd2802c 100644 (file)
@@ -68,6 +68,7 @@
 #define AM43XX_CM_PER_ICSS_CDOFFS                      0x0300
 #define AM43XX_CM_PER_L4LS_CDOFFS                      0x0400
 #define AM43XX_CM_PER_EMIF_CDOFFS                      0x0700
+#define AM43XX_CM_PER_LCDC_CDOFFS                      0x0800
 #define AM43XX_CM_PER_DSS_CDOFFS                       0x0a00
 #define AM43XX_CM_PER_CPSW_CDOFFS                      0x0b00
 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS                  0x0c00