]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - rpmsg/hwspinlock.git/commitdiff
ARM: OMAP2+: prm44xx: Introduce context save/restore for am43 PRCM IO
authorDave Gerlach <d-gerlach@ti.com>
Fri, 18 May 2018 08:40:21 +0000 (14:10 +0530)
committerTony Lindgren <tony@atomide.com>
Fri, 18 May 2018 13:59:24 +0000 (06:59 -0700)
There are two registers on am43x needed for IO daisy chain wake to work
properly, however currently after an RTC+DDR cycle they are lost. We
must take care to save and restore these before and after entering RTC
mode otherwise IO daisy chain wake will stop working from DeepSleep
after resuming.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/prm44xx.c

index 47b657ceba8f246d490116dc3c746c0abf05244d..18b4955ff755ea42a8d7b85b921615ae4e57befe 100644 (file)
@@ -57,6 +57,13 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
        .reconfigure_io_chain   = &omap44xx_prm_reconfigure_io_chain,
 };
 
+struct omap_prm_irq_context {
+       unsigned long irq_enable;
+       unsigned long pm_ctrl;
+};
+
+static struct omap_prm_irq_context omap_prm_context;
+
 /*
  * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
  *   hardware register (which are specific to OMAP44xx SoCs) to reset
@@ -739,6 +746,28 @@ struct pwrdm_ops omap4_pwrdm_operations = {
 
 static int omap44xx_prm_late_init(void);
 
+void prm_save_context(void)
+{
+       omap_prm_context.irq_enable =
+                       omap4_prm_read_inst_reg(AM43XX_PRM_OCP_SOCKET_INST,
+                                               omap4_prcm_irq_setup.mask);
+
+       omap_prm_context.pm_ctrl =
+                       omap4_prm_read_inst_reg(AM43XX_PRM_DEVICE_INST,
+                                               omap4_prcm_irq_setup.pm_ctrl);
+}
+
+void prm_restore_context(void)
+{
+       omap4_prm_write_inst_reg(omap_prm_context.irq_enable,
+                                OMAP4430_PRM_OCP_SOCKET_INST,
+                                omap4_prcm_irq_setup.mask);
+
+       omap4_prm_write_inst_reg(omap_prm_context.pm_ctrl,
+                                AM43XX_PRM_DEVICE_INST,
+                                omap4_prcm_irq_setup.pm_ctrl);
+}
+
 /*
  * XXX document
  */