author | Tomi Valkeinen <tomi.valkeinen@ti.com> | |
Mon, 24 Mar 2014 11:01:52 +0000 (16:31 +0530) | ||
committer | Paul Walmsley <paul@pwsan.com> | |
Fri, 11 Apr 2014 18:29:09 +0000 (12:29 -0600) | ||
commit | 8e4cb9aac2ada7f8a986606703c34e2d573bb876 | |
tree | de9f5ee073353e9253df9dcaa91145254fbe45cc | tree | snapshot (tar.xz tar.gz zip) |
parent | c6c56697ae4bf1226263c19e8353343d7083f40e | commit | diff |
ARM: AM43xx: fix dpll init in bypass mode
On AM43xx, if a PLL is in bypass at kernel init, the code in
omap2_get_dpll_rate() will not realize this and will try to calculate
the clock rate using the multiplier and the divider, resulting in
errors.
omap2_init_dpll_parent() has similar issue.
Add the missing soc_is_am43xx() check to make the code work on AM43xx.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Sathya Prakash M R <sathyap@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On AM43xx, if a PLL is in bypass at kernel init, the code in
omap2_get_dpll_rate() will not realize this and will try to calculate
the clock rate using the multiplier and the divider, resulting in
errors.
omap2_init_dpll_parent() has similar issue.
Add the missing soc_is_am43xx() check to make the code work on AM43xx.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Sathya Prakash M R <sathyap@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/clkt_dpll.c | diff | blob | history |