arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node

The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
    MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes)
    MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode)

Signed-off-by: Suman Anna <s-anna@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 555dc7b7aedc964e61ce541aaa33dca69272f3ca..206c8a48ea2d11d84b6ff65e71436bbe75be4e08 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -121,4 +121,44 @@
                clocks = <&k3_clks 114 0>;
                clock-names = "gpio";
        };
+
+       mcu_r5fss0: r5fss@41000000 {
+               compatible = "ti,j721e-r5fss";
+               lockstep-mode = <1>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x41000000 0x00 0x41000000 0x20000>,
+                        <0x41400000 0x00 0x41400000 0x20000>;
+               power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+               mcu_r5fss0_core0: r5f@41000000 {
+                       compatible = "ti,j721e-r5f";
+                       reg = <0x41000000 0x00008000>,
+                             <0x41010000 0x00008000>;
+                       reg-names = "atcm", "btcm";
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <250>;
+                       ti,sci-proc-ids = <0x01 0xFF>;
+                       resets = <&k3_reset 250 1>;
+                       firmware-name = "j7-mcu-r5f0_0-fw";
+                       atcm-enable = <1>;
+                       btcm-enable = <1>;
+                       loczrama = <1>;
+               };
+
+               mcu_r5fss0_core1: r5f@41400000 {
+                       compatible = "ti,j721e-r5f";
+                       reg = <0x41400000 0x00008000>,
+                             <0x41410000 0x00008000>;
+                       reg-names = "atcm", "btcm";
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <251>;
+                       ti,sci-proc-ids = <0x02 0xFF>;
+                       resets = <&k3_reset 251 1>;
+                       firmware-name = "j7-mcu-r5f0_1-fw";
+                       atcm-enable = <1>;
+                       btcm-enable = <1>;
+                       loczrama = <1>;
+               };
+       };
 };