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ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs
[rpmsg/rpmsg.git] / arch / arm / boot / dts / am571x-idk.dts
1 /*
2  * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 /dts-v1/;
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include "dra7-mmc-iodelay.dtsi"
14 #include "dra72x-mmc-iodelay.dtsi"
15 #include "am57xx-idk-common.dtsi"
16 #include "dra7-ipu-dsp-common.dtsi"
18 / {
19         model = "TI AM5718 IDK";
20         compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
22         memory@80000000 {
23                 device_type = "memory";
24                 reg = <0x0 0x80000000 0x0 0x40000000>;
25         };
27         reserved-memory {
28                 #address-cells = <2>;
29                 #size-cells = <2>;
30                 ranges;
32                 ipu2_memory_region: ipu2-memory@95800000 {
33                         compatible = "shared-dma-pool";
34                         reg = <0x0 0x95800000 0x0 0x3800000>;
35                         reusable;
36                         status = "okay";
37                 };
39                 dsp1_memory_region: dsp1-memory@99000000 {
40                         compatible = "shared-dma-pool";
41                         reg = <0x0 0x99000000 0x0 0x4000000>;
42                         reusable;
43                         status = "okay";
44                 };
46                 ipu1_memory_region: ipu1-memory@9d000000 {
47                         compatible = "shared-dma-pool";
48                         reg = <0x0 0x9d000000 0x0 0x2000000>;
49                         reusable;
50                         status = "okay";
51                 };
52         };
54         leds {
55                 compatible = "gpio-leds";
56                 cpu0-led {
57                         label = "status0:red:cpu0";
58                         gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
59                         default-state = "off";
60                         linux,default-trigger = "cpu0";
61                 };
63                 usr0-led {
64                         label = "status0:green:usr";
65                         gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
66                         default-state = "off";
67                 };
69                 heartbeat-led {
70                         label = "status0:blue:heartbeat";
71                         gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
72                         default-state = "off";
73                         linux,default-trigger = "heartbeat";
74                 };
76                 usr1-led {
77                         label = "status1:red:usr";
78                         gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
79                         default-state = "off";
80                 };
82                 usr2-led {
83                         label = "status1:green:usr";
84                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
85                         default-state = "off";
86                 };
88                 mmc0-led {
89                         label = "status1:blue:mmc0";
90                         gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
91                         default-state = "off";
92                         linux,default-trigger = "mmc0";
93                 };
94         };
95 };
97 &extcon_usb2 {
98         id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
99         vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
100 };
102 &ipu2 {
103         status = "okay";
104         memory-region = <&ipu2_memory_region>;
105 };
107 &ipu1 {
108         status = "okay";
109         memory-region = <&ipu1_memory_region>;
110 };
112 &dsp1 {
113         status = "okay";
114         memory-region = <&dsp1_memory_region>;
115 };
117 &pcie1_rc {
118         status = "okay";
119         gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
120 };
122 &pcie1_ep {
123         gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
124 };
126 &mmc1 {
127         pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
128         pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
129         pinctrl-1 = <&mmc1_pins_hs>;
130         pinctrl-2 = <&mmc1_pins_sdr12>;
131         pinctrl-3 = <&mmc1_pins_sdr25>;
132         pinctrl-4 = <&mmc1_pins_sdr50>;
133         pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
134         pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
135 };
137 &mmc2 {
138         pinctrl-names = "default", "hs", "ddr_3_3v";
139         pinctrl-0 = <&mmc2_pins_default>;
140         pinctrl-1 = <&mmc2_pins_hs>;
141         pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
142 };
144 &cpu0 {
145         vdd-supply = <&smps12_reg>;
146 };