arch/arm/boot/dts/dra74x.dtsi

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include "dra7.dtsi"
  11
  12 / {
  13         compatible = "ti,dra742", "ti,dra74", "ti,dra7";
  14
  15         cpus {
  16                 cpu@1 {
  17                         device_type = "cpu";
  18                         compatible = "arm,cortex-a15";
  19                         reg = <1>;
  20                         operating-points-v2 = <&cpu0_opp_table>;
  21
  22                         clocks = <&dpll_mpu_ck>;
  23                         clock-names = "cpu";
  24
  25                         clock-latency = <300000>; /* From omap-cpufreq driver */
  26
  27                         /* cooling options */
  28                         #cooling-cells = <2>; /* min followed by max */
  29
  30                         vbb-supply = <&abb_mpu>;
  31                 };
  32         };
  33
  34         aliases {
  35                 rproc0 = &ipu1;
  36                 rproc1 = &ipu2;
  37                 rproc2 = &dsp1;
  38                 rproc3 = &dsp2;
  39         };
  40
  41         pmu {
  42                 compatible = "arm,cortex-a15-pmu";
  43                 interrupt-parent = <&wakeupgen>;
  44                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  45                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  46         };
  47
  48         ocp {
  49                 dsp2_system: dsp_system@41500000 {
  50                         compatible = "syscon";
  51                         reg = <0x41500000 0x100>;
  52                 };
  53
  54                 omap_dwc3_4: omap_dwc3_4@48940000 {
  55                         compatible = "ti,dwc3";
  56                         ti,hwmods = "usb_otg_ss4";
  57                         reg = <0x48940000 0x10000>;
  58                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         utmi-mode = <2>;
  62                         ranges;
  63                         status = "disabled";
  64                         usb4: usb@48950000 {
  65                                 compatible = "snps,dwc3";
  66                                 reg = <0x48950000 0x17000>;
  67                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  68                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  69                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  70                                 interrupt-names = "peripheral",
  71                                                   "host",
  72                                                   "otg";
  73                                 maximum-speed = "high-speed";
  74                                 dr_mode = "otg";
  75                         };
  76                 };
  77
  78                 mmu0_dsp2: mmu@41501000 {
  79                         compatible = "ti,dra7-dsp-iommu";
  80                         reg = <0x41501000 0x100>;
  81                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  82                         ti,hwmods = "mmu0_dsp2";
  83                         #iommu-cells = <0>;
  84                         ti,syscon-mmuconfig = <&dsp2_system 0x0>;
  85                 };
  86
  87                 mmu1_dsp2: mmu@41502000 {
  88                         compatible = "ti,dra7-dsp-iommu";
  89                         reg = <0x41502000 0x100>;
  90                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
  91                         ti,hwmods = "mmu1_dsp2";
  92                         #iommu-cells = <0>;
  93                         ti,syscon-mmuconfig = <&dsp2_system 0x1>;
  94                 };
  95
  96                 dsp2: dsp@41000000 {
  97                         compatible = "ti,dra7-dsp";
  98                         reg = <0x41000000 0x48000>,
  99                               <0x41600000 0x8000>,
 100                               <0x41700000 0x8000>;
 101                         reg-names = "l2ram", "l1pram", "l1dram";
 102                         ti,hwmods = "dsp2";
 103                         syscon-bootreg = <&scm_conf 0x560>;
 104                         iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
 105                         ti,rproc-standby-info = <0x4a005620>;
 106                         status = "disabled";
 107                 };
 108         };
 109 };
 110
 111 &cpu0_opp_table {
 112         opp-shared;
 113 };
 114
 115 &dss {
 116         reg = <0x58000000 0x80>,
 117               <0x58004054 0x4>,
 118               <0x58004300 0x20>,
 119               <0x58009054 0x4>,
 120               <0x58009300 0x20>;
 121         reg-names = "dss", "pll1_clkctrl", "pll1",
 122                     "pll2_clkctrl", "pll2";
 123
 124         clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
 125                  <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
 126                  <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
 127         clock-names = "fck", "video1_clk", "video2_clk";
 128 };
 129
 130 &mailbox5 {
 131         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 132                 ti,mbox-tx = <6 2 2>;
 133                 ti,mbox-rx = <4 2 2>;
 134                 status = "disabled";
 135         };
 136         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 137                 ti,mbox-tx = <5 2 2>;
 138                 ti,mbox-rx = <1 2 2>;
 139                 status = "disabled";
 140         };
 141 };
 142
 143 &mailbox6 {
 144         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 145                 ti,mbox-tx = <6 2 2>;
 146                 ti,mbox-rx = <4 2 2>;
 147                 status = "disabled";
 148         };
 149         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 150                 ti,mbox-tx = <5 2 2>;
 151                 ti,mbox-rx = <1 2 2>;
 152                 status = "disabled";
 153         };
 154 };
 155
 156 &pcie1_rc {
 157         compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
 158 };
 159
 160 &pcie1_ep {
 161         compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
 162 };
 163
 164 &pcie2_rc {
 165         compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
 166 };