1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2014 Freescale Semiconductor, Inc.
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 * Also for U-Boot there must be a pre-existing /memory node.
19 */
20 chosen {};
21 memory { device_type = "memory"; };
23 aliases {
24 can0 = &flexcan1;
25 can1 = &flexcan2;
26 ethernet0 = &fec1;
27 ethernet1 = &fec2;
28 gpio0 = &gpio1;
29 gpio1 = &gpio2;
30 gpio2 = &gpio3;
31 gpio3 = &gpio4;
32 gpio4 = &gpio5;
33 gpio5 = &gpio6;
34 gpio6 = &gpio7;
35 i2c0 = &i2c1;
36 i2c1 = &i2c2;
37 i2c2 = &i2c3;
38 i2c3 = &i2c4;
39 mmc0 = &usdhc1;
40 mmc1 = &usdhc2;
41 mmc2 = &usdhc3;
42 mmc3 = &usdhc4;
43 serial0 = &uart1;
44 serial1 = &uart2;
45 serial2 = &uart3;
46 serial3 = &uart4;
47 serial4 = &uart5;
48 serial5 = &uart6;
49 spi0 = &ecspi1;
50 spi1 = &ecspi2;
51 spi2 = &ecspi3;
52 spi3 = &ecspi4;
53 spi4 = &ecspi5;
54 usbphy0 = &usbphy1;
55 usbphy1 = &usbphy2;
56 };
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
62 cpu0: cpu@0 {
63 compatible = "arm,cortex-a9";
64 device_type = "cpu";
65 reg = <0>;
66 next-level-cache = <&L2>;
67 operating-points = <
68 /* kHz uV */
69 996000 1250000
70 792000 1175000
71 396000 1075000
72 198000 975000
73 >;
74 fsl,soc-operating-points = <
75 /* ARM kHz SOC uV */
76 996000 1175000
77 792000 1175000
78 396000 1175000
79 198000 1175000
80 >;
81 clock-latency = <61036>; /* two CLK32 periods */
82 #cooling-cells = <2>;
83 clocks = <&clks IMX6SX_CLK_ARM>,
84 <&clks IMX6SX_CLK_PLL2_PFD2>,
85 <&clks IMX6SX_CLK_STEP>,
86 <&clks IMX6SX_CLK_PLL1_SW>,
87 <&clks IMX6SX_CLK_PLL1_SYS>;
88 clock-names = "arm", "pll2_pfd2_396m", "step",
89 "pll1_sw", "pll1_sys";
90 arm-supply = <®_arm>;
91 soc-supply = <®_soc>;
92 };
93 };
95 intc: interrupt-controller@a01000 {
96 compatible = "arm,cortex-a9-gic";
97 #interrupt-cells = <3>;
98 interrupt-controller;
99 reg = <0x00a01000 0x1000>,
100 <0x00a00100 0x100>;
101 interrupt-parent = <&intc>;
102 };
104 ckil: clock-ckil {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <32768>;
108 clock-output-names = "ckil";
109 };
111 osc: clock-osc {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <24000000>;
115 clock-output-names = "osc";
116 };
118 ipp_di0: clock-ipp-di0 {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <0>;
122 clock-output-names = "ipp_di0";
123 };
125 ipp_di1: clock-ipp-di1 {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <0>;
129 clock-output-names = "ipp_di1";
130 };
132 anaclk1: clock-anaclk1 {
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-frequency = <0>;
136 clock-output-names = "anaclk1";
137 };
139 anaclk2: clock-anaclk2 {
140 compatible = "fixed-clock";
141 #clock-cells = <0>;
142 clock-frequency = <0>;
143 clock-output-names = "anaclk2";
144 };
146 tempmon: tempmon {
147 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
148 interrupt-parent = <&gpc>;
149 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
150 fsl,tempmon = <&anatop>;
151 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
152 nvmem-cell-names = "calib", "temp_grade";
153 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
154 };
156 pmu {
157 compatible = "arm,cortex-a9-pmu";
158 interrupt-parent = <&gpc>;
159 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
160 };
162 soc {
163 #address-cells = <1>;
164 #size-cells = <1>;
165 compatible = "simple-bus";
166 interrupt-parent = <&gpc>;
167 ranges;
169 ocram_s: sram@8f8000 {
170 compatible = "mmio-sram";
171 reg = <0x008f8000 0x4000>;
172 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
173 };
175 ocram: sram@900000 {
176 compatible = "mmio-sram";
177 reg = <0x00900000 0x20000>;
178 clocks = <&clks IMX6SX_CLK_OCRAM>;
179 };
181 L2: l2-cache@a02000 {
182 compatible = "arm,pl310-cache";
183 reg = <0x00a02000 0x1000>;
184 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
185 cache-unified;
186 cache-level = <2>;
187 arm,tag-latency = <4 2 3>;
188 arm,data-latency = <4 2 3>;
189 };
191 gpu: gpu@1800000 {
192 compatible = "vivante,gc";
193 reg = <0x01800000 0x4000>;
194 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clks IMX6SX_CLK_GPU>,
196 <&clks IMX6SX_CLK_GPU>,
197 <&clks IMX6SX_CLK_GPU>;
198 clock-names = "bus", "core", "shader";
199 power-domains = <&pd_pu>;
200 };
202 dma_apbh: dma-apbh@1804000 {
203 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
204 reg = <0x01804000 0x2000>;
205 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
209 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
210 #dma-cells = <1>;
211 dma-channels = <4>;
212 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
213 };
215 gpmi: gpmi-nand@1806000{
216 compatible = "fsl,imx6sx-gpmi-nand";
217 #address-cells = <1>;
218 #size-cells = <1>;
219 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
220 reg-names = "gpmi-nand", "bch";
221 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
222 interrupt-names = "bch";
223 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
224 <&clks IMX6SX_CLK_GPMI_APB>,
225 <&clks IMX6SX_CLK_GPMI_BCH>,
226 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
227 <&clks IMX6SX_CLK_PER1_BCH>;
228 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
229 "gpmi_bch_apb", "per1_bch";
230 dmas = <&dma_apbh 0>;
231 dma-names = "rx-tx";
232 status = "disabled";
233 };
235 aips1: aips-bus@2000000 {
236 compatible = "fsl,aips-bus", "simple-bus";
237 #address-cells = <1>;
238 #size-cells = <1>;
239 reg = <0x02000000 0x100000>;
240 ranges;
242 spba-bus@2000000 {
243 compatible = "fsl,spba-bus", "simple-bus";
244 #address-cells = <1>;
245 #size-cells = <1>;
246 reg = <0x02000000 0x40000>;
247 ranges;
249 spdif: spdif@2004000 {
250 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
251 reg = <0x02004000 0x4000>;
252 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
253 dmas = <&sdma 14 18 0>,
254 <&sdma 15 18 0>;
255 dma-names = "rx", "tx";
256 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
257 <&clks IMX6SX_CLK_OSC>,
258 <&clks IMX6SX_CLK_SPDIF>,
259 <&clks 0>, <&clks 0>, <&clks 0>,
260 <&clks IMX6SX_CLK_IPG>,
261 <&clks 0>, <&clks 0>,
262 <&clks IMX6SX_CLK_SPBA>;
263 clock-names = "core", "rxtx0",
264 "rxtx1", "rxtx2",
265 "rxtx3", "rxtx4",
266 "rxtx5", "rxtx6",
267 "rxtx7", "spba";
268 status = "disabled";
269 };
271 ecspi1: ecspi@2008000 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
275 reg = <0x02008000 0x4000>;
276 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6SX_CLK_ECSPI1>,
278 <&clks IMX6SX_CLK_ECSPI1>;
279 clock-names = "ipg", "per";
280 status = "disabled";
281 };
283 ecspi2: ecspi@200c000 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
287 reg = <0x0200c000 0x4000>;
288 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clks IMX6SX_CLK_ECSPI2>,
290 <&clks IMX6SX_CLK_ECSPI2>;
291 clock-names = "ipg", "per";
292 status = "disabled";
293 };
295 ecspi3: ecspi@2010000 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
299 reg = <0x02010000 0x4000>;
300 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clks IMX6SX_CLK_ECSPI3>,
302 <&clks IMX6SX_CLK_ECSPI3>;
303 clock-names = "ipg", "per";
304 status = "disabled";
305 };
307 ecspi4: ecspi@2014000 {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
311 reg = <0x02014000 0x4000>;
312 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clks IMX6SX_CLK_ECSPI4>,
314 <&clks IMX6SX_CLK_ECSPI4>;
315 clock-names = "ipg", "per";
316 status = "disabled";
317 };
319 uart1: serial@2020000 {
320 compatible = "fsl,imx6sx-uart",
321 "fsl,imx6q-uart", "fsl,imx21-uart";
322 reg = <0x02020000 0x4000>;
323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clks IMX6SX_CLK_UART_IPG>,
325 <&clks IMX6SX_CLK_UART_SERIAL>;
326 clock-names = "ipg", "per";
327 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
328 dma-names = "rx", "tx";
329 status = "disabled";
330 };
332 esai: esai@2024000 {
333 reg = <0x02024000 0x4000>;
334 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
336 <&clks IMX6SX_CLK_ESAI_MEM>,
337 <&clks IMX6SX_CLK_ESAI_EXTAL>,
338 <&clks IMX6SX_CLK_ESAI_IPG>,
339 <&clks IMX6SX_CLK_SPBA>;
340 clock-names = "core", "mem", "extal",
341 "fsys", "spba";
342 status = "disabled";
343 };
345 ssi1: ssi@2028000 {
346 #sound-dai-cells = <0>;
347 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
348 reg = <0x02028000 0x4000>;
349 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
351 <&clks IMX6SX_CLK_SSI1>;
352 clock-names = "ipg", "baud";
353 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
354 dma-names = "rx", "tx";
355 fsl,fifo-depth = <15>;
356 status = "disabled";
357 };
359 ssi2: ssi@202c000 {
360 #sound-dai-cells = <0>;
361 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
362 reg = <0x0202c000 0x4000>;
363 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
365 <&clks IMX6SX_CLK_SSI2>;
366 clock-names = "ipg", "baud";
367 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
368 dma-names = "rx", "tx";
369 fsl,fifo-depth = <15>;
370 status = "disabled";
371 };
373 ssi3: ssi@2030000 {
374 #sound-dai-cells = <0>;
375 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
376 reg = <0x02030000 0x4000>;
377 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
379 <&clks IMX6SX_CLK_SSI3>;
380 clock-names = "ipg", "baud";
381 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
382 dma-names = "rx", "tx";
383 fsl,fifo-depth = <15>;
384 status = "disabled";
385 };
387 asrc: asrc@2034000 {
388 reg = <0x02034000 0x4000>;
389 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
391 <&clks IMX6SX_CLK_ASRC_IPG>,
392 <&clks IMX6SX_CLK_SPDIF>,
393 <&clks IMX6SX_CLK_SPBA>;
394 clock-names = "mem", "ipg", "asrck", "spba";
395 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
396 <&sdma 19 20 1>, <&sdma 20 20 1>,
397 <&sdma 21 20 1>, <&sdma 22 20 1>;
398 dma-names = "rxa", "rxb", "rxc",
399 "txa", "txb", "txc";
400 status = "okay";
401 };
402 };
404 pwm1: pwm@2080000 {
405 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
406 reg = <0x02080000 0x4000>;
407 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&clks IMX6SX_CLK_PWM1>,
409 <&clks IMX6SX_CLK_PWM1>;
410 clock-names = "ipg", "per";
411 #pwm-cells = <2>;
412 };
414 pwm2: pwm@2084000 {
415 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
416 reg = <0x02084000 0x4000>;
417 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clks IMX6SX_CLK_PWM2>,
419 <&clks IMX6SX_CLK_PWM2>;
420 clock-names = "ipg", "per";
421 #pwm-cells = <2>;
422 };
424 pwm3: pwm@2088000 {
425 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
426 reg = <0x02088000 0x4000>;
427 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clks IMX6SX_CLK_PWM3>,
429 <&clks IMX6SX_CLK_PWM3>;
430 clock-names = "ipg", "per";
431 #pwm-cells = <2>;
432 };
434 pwm4: pwm@208c000 {
435 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
436 reg = <0x0208c000 0x4000>;
437 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clks IMX6SX_CLK_PWM4>,
439 <&clks IMX6SX_CLK_PWM4>;
440 clock-names = "ipg", "per";
441 #pwm-cells = <2>;
442 };
444 flexcan1: can@2090000 {
445 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
446 reg = <0x02090000 0x4000>;
447 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
449 <&clks IMX6SX_CLK_CAN1_SERIAL>;
450 clock-names = "ipg", "per";
451 status = "disabled";
452 };
454 flexcan2: can@2094000 {
455 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
456 reg = <0x02094000 0x4000>;
457 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
459 <&clks IMX6SX_CLK_CAN2_SERIAL>;
460 clock-names = "ipg", "per";
461 status = "disabled";
462 };
464 gpt: gpt@2098000 {
465 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
466 reg = <0x02098000 0x4000>;
467 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
469 <&clks IMX6SX_CLK_GPT_3M>;
470 clock-names = "ipg", "per";
471 };
473 gpio1: gpio@209c000 {
474 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
475 reg = <0x0209c000 0x4000>;
476 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
478 gpio-controller;
479 #gpio-cells = <2>;
480 interrupt-controller;
481 #interrupt-cells = <2>;
482 gpio-ranges = <&iomuxc 0 5 26>;
483 };
485 gpio2: gpio@20a0000 {
486 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
487 reg = <0x020a0000 0x4000>;
488 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
490 gpio-controller;
491 #gpio-cells = <2>;
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 gpio-ranges = <&iomuxc 0 31 20>;
495 };
497 gpio3: gpio@20a4000 {
498 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
499 reg = <0x020a4000 0x4000>;
500 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 gpio-ranges = <&iomuxc 0 51 29>;
507 };
509 gpio4: gpio@20a8000 {
510 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
511 reg = <0x020a8000 0x4000>;
512 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 gpio-ranges = <&iomuxc 0 80 32>;
519 };
521 gpio5: gpio@20ac000 {
522 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
523 reg = <0x020ac000 0x4000>;
524 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
526 gpio-controller;
527 #gpio-cells = <2>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 gpio-ranges = <&iomuxc 0 112 24>;
531 };
533 gpio6: gpio@20b0000 {
534 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
535 reg = <0x020b0000 0x4000>;
536 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
538 gpio-controller;
539 #gpio-cells = <2>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
543 };
545 gpio7: gpio@20b4000 {
546 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
547 reg = <0x020b4000 0x4000>;
548 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
555 };
557 kpp: kpp@20b8000 {
558 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
559 reg = <0x020b8000 0x4000>;
560 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clks IMX6SX_CLK_DUMMY>;
562 status = "disabled";
563 };
565 wdog1: wdog@20bc000 {
566 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
567 reg = <0x020bc000 0x4000>;
568 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&clks IMX6SX_CLK_DUMMY>;
570 };
572 wdog2: wdog@20c0000 {
573 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
574 reg = <0x020c0000 0x4000>;
575 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&clks IMX6SX_CLK_DUMMY>;
577 status = "disabled";
578 };
580 clks: ccm@20c4000 {
581 compatible = "fsl,imx6sx-ccm";
582 reg = <0x020c4000 0x4000>;
583 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
585 #clock-cells = <1>;
586 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
587 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
588 };
590 anatop: anatop@20c8000 {
591 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
592 "syscon", "simple-bus";
593 reg = <0x020c8000 0x1000>;
594 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
598 regulator-1p1 {
599 compatible = "fsl,anatop-regulator";
600 regulator-name = "vdd1p1";
601 regulator-min-microvolt = <1000000>;
602 regulator-max-microvolt = <1200000>;
603 regulator-always-on;
604 anatop-reg-offset = <0x110>;
605 anatop-vol-bit-shift = <8>;
606 anatop-vol-bit-width = <5>;
607 anatop-min-bit-val = <4>;
608 anatop-min-voltage = <800000>;
609 anatop-max-voltage = <1375000>;
610 anatop-enable-bit = <0>;
611 };
613 regulator-3p0 {
614 compatible = "fsl,anatop-regulator";
615 regulator-name = "vdd3p0";
616 regulator-min-microvolt = <2800000>;
617 regulator-max-microvolt = <3150000>;
618 regulator-always-on;
619 anatop-reg-offset = <0x120>;
620 anatop-vol-bit-shift = <8>;
621 anatop-vol-bit-width = <5>;
622 anatop-min-bit-val = <0>;
623 anatop-min-voltage = <2625000>;
624 anatop-max-voltage = <3400000>;
625 anatop-enable-bit = <0>;
626 };
628 regulator-2p5 {
629 compatible = "fsl,anatop-regulator";
630 regulator-name = "vdd2p5";
631 regulator-min-microvolt = <2250000>;
632 regulator-max-microvolt = <2750000>;
633 regulator-always-on;
634 anatop-reg-offset = <0x130>;
635 anatop-vol-bit-shift = <8>;
636 anatop-vol-bit-width = <5>;
637 anatop-min-bit-val = <0>;
638 anatop-min-voltage = <2100000>;
639 anatop-max-voltage = <2875000>;
640 anatop-enable-bit = <0>;
641 };
643 reg_arm: regulator-vddcore {
644 compatible = "fsl,anatop-regulator";
645 regulator-name = "vddarm";
646 regulator-min-microvolt = <725000>;
647 regulator-max-microvolt = <1450000>;
648 regulator-always-on;
649 anatop-reg-offset = <0x140>;
650 anatop-vol-bit-shift = <0>;
651 anatop-vol-bit-width = <5>;
652 anatop-delay-reg-offset = <0x170>;
653 anatop-delay-bit-shift = <24>;
654 anatop-delay-bit-width = <2>;
655 anatop-min-bit-val = <1>;
656 anatop-min-voltage = <725000>;
657 anatop-max-voltage = <1450000>;
658 };
660 reg_pcie: regulator-vddpcie {
661 compatible = "fsl,anatop-regulator";
662 regulator-name = "vddpcie";
663 regulator-min-microvolt = <725000>;
664 regulator-max-microvolt = <1450000>;
665 anatop-reg-offset = <0x140>;
666 anatop-vol-bit-shift = <9>;
667 anatop-vol-bit-width = <5>;
668 anatop-delay-reg-offset = <0x170>;
669 anatop-delay-bit-shift = <26>;
670 anatop-delay-bit-width = <2>;
671 anatop-min-bit-val = <1>;
672 anatop-min-voltage = <725000>;
673 anatop-max-voltage = <1450000>;
674 };
676 reg_soc: regulator-vddsoc {
677 compatible = "fsl,anatop-regulator";
678 regulator-name = "vddsoc";
679 regulator-min-microvolt = <725000>;
680 regulator-max-microvolt = <1450000>;
681 regulator-always-on;
682 anatop-reg-offset = <0x140>;
683 anatop-vol-bit-shift = <18>;
684 anatop-vol-bit-width = <5>;
685 anatop-delay-reg-offset = <0x170>;
686 anatop-delay-bit-shift = <28>;
687 anatop-delay-bit-width = <2>;
688 anatop-min-bit-val = <1>;
689 anatop-min-voltage = <725000>;
690 anatop-max-voltage = <1450000>;
691 };
692 };
694 usbphy1: usbphy@20c9000 {
695 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
696 reg = <0x020c9000 0x1000>;
697 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clks IMX6SX_CLK_USBPHY1>;
699 fsl,anatop = <&anatop>;
700 };
702 usbphy2: usbphy@20ca000 {
703 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
704 reg = <0x020ca000 0x1000>;
705 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&clks IMX6SX_CLK_USBPHY2>;
707 fsl,anatop = <&anatop>;
708 };
710 snvs: snvs@20cc000 {
711 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
712 reg = <0x020cc000 0x4000>;
714 snvs_rtc: snvs-rtc-lp {
715 compatible = "fsl,sec-v4.0-mon-rtc-lp";
716 regmap = <&snvs>;
717 offset = <0x34>;
718 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
719 };
721 snvs_poweroff: snvs-poweroff {
722 compatible = "syscon-poweroff";
723 regmap = <&snvs>;
724 offset = <0x38>;
725 value = <0x60>;
726 mask = <0x60>;
727 status = "disabled";
728 };
730 snvs_pwrkey: snvs-powerkey {
731 compatible = "fsl,sec-v4.0-pwrkey";
732 regmap = <&snvs>;
733 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
734 linux,keycode = <KEY_POWER>;
735 wakeup-source;
736 };
737 };
739 epit1: epit@20d0000 {
740 reg = <0x020d0000 0x4000>;
741 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
742 };
744 epit2: epit@20d4000 {
745 reg = <0x020d4000 0x4000>;
746 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
747 };
749 src: src@20d8000 {
750 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
751 reg = <0x020d8000 0x4000>;
752 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
754 #reset-cells = <1>;
755 };
757 gpc: gpc@20dc000 {
758 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
759 reg = <0x020dc000 0x4000>;
760 interrupt-controller;
761 #interrupt-cells = <3>;
762 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
763 interrupt-parent = <&intc>;
764 clocks = <&clks IMX6SX_CLK_IPG>;
765 clock-names = "ipg";
767 pgc {
768 #address-cells = <1>;
769 #size-cells = <0>;
771 power-domain@0 {
772 reg = <0>;
773 #power-domain-cells = <0>;
774 };
776 pd_pu: power-domain@1 {
777 reg = <1>;
778 #power-domain-cells = <0>;
779 power-supply = <®_soc>;
780 clocks = <&clks IMX6SX_CLK_GPU>;
781 };
783 pd_pci: power-domain@3 {
784 reg = <3>;
785 #power-domain-cells = <0>;
786 power-supply = <®_pcie>;
787 };
788 };
789 };
791 iomuxc: iomuxc@20e0000 {
792 compatible = "fsl,imx6sx-iomuxc";
793 reg = <0x020e0000 0x4000>;
794 };
796 gpr: iomuxc-gpr@20e4000 {
797 compatible = "fsl,imx6sx-iomuxc-gpr",
798 "fsl,imx6q-iomuxc-gpr", "syscon";
799 reg = <0x020e4000 0x4000>;
800 };
802 sdma: sdma@20ec000 {
803 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
804 reg = <0x020ec000 0x4000>;
805 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6SX_CLK_SDMA>,
807 <&clks IMX6SX_CLK_SDMA>;
808 clock-names = "ipg", "ahb";
809 #dma-cells = <3>;
810 /* imx6sx reuses imx6q sdma firmware */
811 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
812 };
813 };
815 aips2: aips-bus@2100000 {
816 compatible = "fsl,aips-bus", "simple-bus";
817 #address-cells = <1>;
818 #size-cells = <1>;
819 reg = <0x02100000 0x100000>;
820 ranges;
822 crypto: caam@2100000 {
823 compatible = "fsl,sec-v4.0";
824 #address-cells = <1>;
825 #size-cells = <1>;
826 reg = <0x2100000 0x10000>;
827 ranges = <0 0x2100000 0x10000>;
828 interrupt-parent = <&intc>;
829 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
830 <&clks IMX6SX_CLK_CAAM_ACLK>,
831 <&clks IMX6SX_CLK_CAAM_IPG>,
832 <&clks IMX6SX_CLK_EIM_SLOW>;
833 clock-names = "mem", "aclk", "ipg", "emi_slow";
835 sec_jr0: jr0@1000 {
836 compatible = "fsl,sec-v4.0-job-ring";
837 reg = <0x1000 0x1000>;
838 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
839 };
841 sec_jr1: jr1@2000 {
842 compatible = "fsl,sec-v4.0-job-ring";
843 reg = <0x2000 0x1000>;
844 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
845 };
846 };
848 usbotg1: usb@2184000 {
849 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
850 reg = <0x02184000 0x200>;
851 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clks IMX6SX_CLK_USBOH3>;
853 fsl,usbphy = <&usbphy1>;
854 fsl,usbmisc = <&usbmisc 0>;
855 fsl,anatop = <&anatop>;
856 ahb-burst-config = <0x0>;
857 tx-burst-size-dword = <0x10>;
858 rx-burst-size-dword = <0x10>;
859 status = "disabled";
860 };
862 usbotg2: usb@2184200 {
863 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
864 reg = <0x02184200 0x200>;
865 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clks IMX6SX_CLK_USBOH3>;
867 fsl,usbphy = <&usbphy2>;
868 fsl,usbmisc = <&usbmisc 1>;
869 ahb-burst-config = <0x0>;
870 tx-burst-size-dword = <0x10>;
871 rx-burst-size-dword = <0x10>;
872 status = "disabled";
873 };
875 usbh: usb@2184400 {
876 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
877 reg = <0x02184400 0x200>;
878 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6SX_CLK_USBOH3>;
880 fsl,usbmisc = <&usbmisc 2>;
881 phy_type = "hsic";
882 fsl,anatop = <&anatop>;
883 dr_mode = "host";
884 ahb-burst-config = <0x0>;
885 tx-burst-size-dword = <0x10>;
886 rx-burst-size-dword = <0x10>;
887 status = "disabled";
888 };
890 usbmisc: usbmisc@2184800 {
891 #index-cells = <1>;
892 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
893 reg = <0x02184800 0x200>;
894 clocks = <&clks IMX6SX_CLK_USBOH3>;
895 };
897 fec1: ethernet@2188000 {
898 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
899 reg = <0x02188000 0x4000>;
900 interrupt-names = "int0", "pps";
901 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&clks IMX6SX_CLK_ENET>,
904 <&clks IMX6SX_CLK_ENET_AHB>,
905 <&clks IMX6SX_CLK_ENET_PTP>,
906 <&clks IMX6SX_CLK_ENET_REF>,
907 <&clks IMX6SX_CLK_ENET_PTP>;
908 clock-names = "ipg", "ahb", "ptp",
909 "enet_clk_ref", "enet_out";
910 fsl,num-tx-queues=<3>;
911 fsl,num-rx-queues=<3>;
912 status = "disabled";
913 };
915 mlb: mlb@218c000 {
916 reg = <0x0218c000 0x4000>;
917 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clks IMX6SX_CLK_MLB>;
921 status = "disabled";
922 };
924 usdhc1: usdhc@2190000 {
925 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
926 reg = <0x02190000 0x4000>;
927 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX6SX_CLK_USDHC1>,
929 <&clks IMX6SX_CLK_USDHC1>,
930 <&clks IMX6SX_CLK_USDHC1>;
931 clock-names = "ipg", "ahb", "per";
932 bus-width = <4>;
933 status = "disabled";
934 };
936 usdhc2: usdhc@2194000 {
937 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
938 reg = <0x02194000 0x4000>;
939 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&clks IMX6SX_CLK_USDHC2>,
941 <&clks IMX6SX_CLK_USDHC2>,
942 <&clks IMX6SX_CLK_USDHC2>;
943 clock-names = "ipg", "ahb", "per";
944 bus-width = <4>;
945 status = "disabled";
946 };
948 usdhc3: usdhc@2198000 {
949 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
950 reg = <0x02198000 0x4000>;
951 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&clks IMX6SX_CLK_USDHC3>,
953 <&clks IMX6SX_CLK_USDHC3>,
954 <&clks IMX6SX_CLK_USDHC3>;
955 clock-names = "ipg", "ahb", "per";
956 bus-width = <4>;
957 status = "disabled";
958 };
960 usdhc4: usdhc@219c000 {
961 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
962 reg = <0x0219c000 0x4000>;
963 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&clks IMX6SX_CLK_USDHC4>,
965 <&clks IMX6SX_CLK_USDHC4>,
966 <&clks IMX6SX_CLK_USDHC4>;
967 clock-names = "ipg", "ahb", "per";
968 bus-width = <4>;
969 status = "disabled";
970 };
972 i2c1: i2c@21a0000 {
973 #address-cells = <1>;
974 #size-cells = <0>;
975 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
976 reg = <0x021a0000 0x4000>;
977 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clks IMX6SX_CLK_I2C1>;
979 status = "disabled";
980 };
982 i2c2: i2c@21a4000 {
983 #address-cells = <1>;
984 #size-cells = <0>;
985 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
986 reg = <0x021a4000 0x4000>;
987 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&clks IMX6SX_CLK_I2C2>;
989 status = "disabled";
990 };
992 i2c3: i2c@21a8000 {
993 #address-cells = <1>;
994 #size-cells = <0>;
995 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
996 reg = <0x021a8000 0x4000>;
997 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX6SX_CLK_I2C3>;
999 status = "disabled";
1000 };
1002 mmdc: mmdc@21b0000 {
1003 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1004 reg = <0x021b0000 0x4000>;
1005 };
1007 fec2: ethernet@21b4000 {
1008 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1009 reg = <0x021b4000 0x4000>;
1010 interrupt-names = "int0", "pps";
1011 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clks IMX6SX_CLK_ENET>,
1014 <&clks IMX6SX_CLK_ENET_AHB>,
1015 <&clks IMX6SX_CLK_ENET_PTP>,
1016 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1017 <&clks IMX6SX_CLK_ENET_PTP>;
1018 clock-names = "ipg", "ahb", "ptp",
1019 "enet_clk_ref", "enet_out";
1020 status = "disabled";
1021 };
1023 weim: weim@21b8000 {
1024 #address-cells = <2>;
1025 #size-cells = <1>;
1026 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1027 reg = <0x021b8000 0x4000>;
1028 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1030 fsl,weim-cs-gpr = <&gpr>;
1031 status = "disabled";
1032 };
1034 ocotp: ocotp@21bc000 {
1035 #address-cells = <1>;
1036 #size-cells = <1>;
1037 compatible = "fsl,imx6sx-ocotp", "syscon";
1038 reg = <0x021bc000 0x4000>;
1039 clocks = <&clks IMX6SX_CLK_OCOTP>;
1041 tempmon_calib: calib@38 {
1042 reg = <0x38 4>;
1043 };
1045 tempmon_temp_grade: temp-grade@20 {
1046 reg = <0x20 4>;
1047 };
1048 };
1050 sai1: sai@21d4000 {
1051 compatible = "fsl,imx6sx-sai";
1052 reg = <0x021d4000 0x4000>;
1053 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1055 <&clks IMX6SX_CLK_SAI1>,
1056 <&clks 0>, <&clks 0>;
1057 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1058 dma-names = "rx", "tx";
1059 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1060 status = "disabled";
1061 };
1063 audmux: audmux@21d8000 {
1064 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1065 reg = <0x021d8000 0x4000>;
1066 status = "disabled";
1067 };
1069 sai2: sai@21dc000 {
1070 compatible = "fsl,imx6sx-sai";
1071 reg = <0x021dc000 0x4000>;
1072 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1074 <&clks IMX6SX_CLK_SAI2>,
1075 <&clks 0>, <&clks 0>;
1076 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1077 dma-names = "rx", "tx";
1078 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1079 status = "disabled";
1080 };
1082 qspi1: qspi@21e0000 {
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 compatible = "fsl,imx6sx-qspi";
1086 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1087 reg-names = "QuadSPI", "QuadSPI-memory";
1088 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&clks IMX6SX_CLK_QSPI1>,
1090 <&clks IMX6SX_CLK_QSPI1>;
1091 clock-names = "qspi_en", "qspi";
1092 status = "disabled";
1093 };
1095 qspi2: qspi@21e4000 {
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1098 compatible = "fsl,imx6sx-qspi";
1099 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1100 reg-names = "QuadSPI", "QuadSPI-memory";
1101 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1102 clocks = <&clks IMX6SX_CLK_QSPI2>,
1103 <&clks IMX6SX_CLK_QSPI2>;
1104 clock-names = "qspi_en", "qspi";
1105 status = "disabled";
1106 };
1108 uart2: serial@21e8000 {
1109 compatible = "fsl,imx6sx-uart",
1110 "fsl,imx6q-uart", "fsl,imx21-uart";
1111 reg = <0x021e8000 0x4000>;
1112 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1114 <&clks IMX6SX_CLK_UART_SERIAL>;
1115 clock-names = "ipg", "per";
1116 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1117 dma-names = "rx", "tx";
1118 status = "disabled";
1119 };
1121 uart3: serial@21ec000 {
1122 compatible = "fsl,imx6sx-uart",
1123 "fsl,imx6q-uart", "fsl,imx21-uart";
1124 reg = <0x021ec000 0x4000>;
1125 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1127 <&clks IMX6SX_CLK_UART_SERIAL>;
1128 clock-names = "ipg", "per";
1129 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1130 dma-names = "rx", "tx";
1131 status = "disabled";
1132 };
1134 uart4: serial@21f0000 {
1135 compatible = "fsl,imx6sx-uart",
1136 "fsl,imx6q-uart", "fsl,imx21-uart";
1137 reg = <0x021f0000 0x4000>;
1138 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1140 <&clks IMX6SX_CLK_UART_SERIAL>;
1141 clock-names = "ipg", "per";
1142 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1143 dma-names = "rx", "tx";
1144 status = "disabled";
1145 };
1147 uart5: serial@21f4000 {
1148 compatible = "fsl,imx6sx-uart",
1149 "fsl,imx6q-uart", "fsl,imx21-uart";
1150 reg = <0x021f4000 0x4000>;
1151 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1153 <&clks IMX6SX_CLK_UART_SERIAL>;
1154 clock-names = "ipg", "per";
1155 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1156 dma-names = "rx", "tx";
1157 status = "disabled";
1158 };
1160 i2c4: i2c@21f8000 {
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1164 reg = <0x021f8000 0x4000>;
1165 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&clks IMX6SX_CLK_I2C4>;
1167 status = "disabled";
1168 };
1169 };
1171 aips3: aips-bus@2200000 {
1172 compatible = "fsl,aips-bus", "simple-bus";
1173 #address-cells = <1>;
1174 #size-cells = <1>;
1175 reg = <0x02200000 0x100000>;
1176 ranges;
1178 spba-bus@2240000 {
1179 compatible = "fsl,spba-bus", "simple-bus";
1180 #address-cells = <1>;
1181 #size-cells = <1>;
1182 reg = <0x02240000 0x40000>;
1183 ranges;
1185 csi1: csi@2214000 {
1186 reg = <0x02214000 0x4000>;
1187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1189 <&clks IMX6SX_CLK_CSI>,
1190 <&clks IMX6SX_CLK_DCIC1>;
1191 clock-names = "disp-axi", "csi_mclk", "dcic";
1192 status = "disabled";
1193 };
1195 pxp: pxp@2218000 {
1196 reg = <0x02218000 0x4000>;
1197 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1199 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1200 clock-names = "pxp-axi", "disp-axi";
1201 status = "disabled";
1202 };
1204 csi2: csi@221c000 {
1205 reg = <0x0221c000 0x4000>;
1206 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1208 <&clks IMX6SX_CLK_CSI>,
1209 <&clks IMX6SX_CLK_DCIC2>;
1210 clock-names = "disp-axi", "csi_mclk", "dcic";
1211 status = "disabled";
1212 };
1214 lcdif1: lcdif@2220000 {
1215 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1216 reg = <0x02220000 0x4000>;
1217 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1218 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1219 <&clks IMX6SX_CLK_LCDIF_APB>,
1220 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1221 clock-names = "pix", "axi", "disp_axi";
1222 status = "disabled";
1223 };
1225 lcdif2: lcdif@2224000 {
1226 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1227 reg = <0x02224000 0x4000>;
1228 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1229 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1230 <&clks IMX6SX_CLK_LCDIF_APB>,
1231 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1232 clock-names = "pix", "axi", "disp_axi";
1233 status = "disabled";
1234 };
1236 vadc: vadc@2228000 {
1237 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1238 reg-names = "vadc-vafe", "vadc-vdec";
1239 clocks = <&clks IMX6SX_CLK_VADC>,
1240 <&clks IMX6SX_CLK_CSI>;
1241 clock-names = "vadc", "csi";
1242 status = "disabled";
1243 };
1244 };
1246 adc1: adc@2280000 {
1247 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1248 reg = <0x02280000 0x4000>;
1249 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&clks IMX6SX_CLK_IPG>;
1251 clock-names = "adc";
1252 fsl,adck-max-frequency = <30000000>, <40000000>,
1253 <20000000>;
1254 status = "disabled";
1255 };
1257 adc2: adc@2284000 {
1258 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1259 reg = <0x02284000 0x4000>;
1260 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&clks IMX6SX_CLK_IPG>;
1262 clock-names = "adc";
1263 fsl,adck-max-frequency = <30000000>, <40000000>,
1264 <20000000>;
1265 status = "disabled";
1266 };
1268 wdog3: wdog@2288000 {
1269 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1270 reg = <0x02288000 0x4000>;
1271 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1272 clocks = <&clks IMX6SX_CLK_DUMMY>;
1273 status = "disabled";
1274 };
1276 ecspi5: ecspi@228c000 {
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1279 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1280 reg = <0x0228c000 0x4000>;
1281 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1282 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1283 <&clks IMX6SX_CLK_ECSPI5>;
1284 clock-names = "ipg", "per";
1285 status = "disabled";
1286 };
1288 uart6: serial@22a0000 {
1289 compatible = "fsl,imx6sx-uart",
1290 "fsl,imx6q-uart", "fsl,imx21-uart";
1291 reg = <0x022a0000 0x4000>;
1292 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1294 <&clks IMX6SX_CLK_UART_SERIAL>;
1295 clock-names = "ipg", "per";
1296 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1297 dma-names = "rx", "tx";
1298 status = "disabled";
1299 };
1301 pwm5: pwm@22a4000 {
1302 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1303 reg = <0x022a4000 0x4000>;
1304 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&clks IMX6SX_CLK_PWM5>,
1306 <&clks IMX6SX_CLK_PWM5>;
1307 clock-names = "ipg", "per";
1308 #pwm-cells = <2>;
1309 };
1311 pwm6: pwm@22a8000 {
1312 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1313 reg = <0x022a8000 0x4000>;
1314 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1315 clocks = <&clks IMX6SX_CLK_PWM6>,
1316 <&clks IMX6SX_CLK_PWM6>;
1317 clock-names = "ipg", "per";
1318 #pwm-cells = <2>;
1319 };
1321 pwm7: pwm@22ac000 {
1322 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1323 reg = <0x022ac000 0x4000>;
1324 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1325 clocks = <&clks IMX6SX_CLK_PWM7>,
1326 <&clks IMX6SX_CLK_PWM7>;
1327 clock-names = "ipg", "per";
1328 #pwm-cells = <2>;
1329 };
1331 pwm8: pwm@22b0000 {
1332 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1333 reg = <0x0022b0000 0x4000>;
1334 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&clks IMX6SX_CLK_PWM8>,
1336 <&clks IMX6SX_CLK_PWM8>;
1337 clock-names = "ipg", "per";
1338 #pwm-cells = <2>;
1339 };
1340 };
1342 pcie: pcie@8ffc000 {
1343 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1344 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1345 reg-names = "dbi", "config";
1346 #address-cells = <3>;
1347 #size-cells = <2>;
1348 device_type = "pci";
1349 bus-range = <0x00 0xff>;
1350 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
1351 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1352 num-lanes = <1>;
1353 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1354 interrupt-names = "msi";
1355 #interrupt-cells = <1>;
1356 interrupt-map-mask = <0 0 0 0x7>;
1357 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1358 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1359 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1360 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1361 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1362 <&clks IMX6SX_CLK_LVDS1_OUT>,
1363 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1364 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1365 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1366 power-domains = <&pd_pci>;
1367 status = "disabled";
1368 };
1369 };
1370 };