1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx7d-pinfunc.h"
13 / {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 /*
17 * The decompressor and also some bootloaders rely on a
18 * pre-existing /chosen node to be available to insert the
19 * command line and merge other ATAGS info.
20 * Also for U-Boot there must be a pre-existing /memory node.
21 */
22 chosen {};
23 memory { device_type = "memory"; };
25 aliases {
26 gpio0 = &gpio1;
27 gpio1 = &gpio2;
28 gpio2 = &gpio3;
29 gpio3 = &gpio4;
30 gpio4 = &gpio5;
31 gpio5 = &gpio6;
32 gpio6 = &gpio7;
33 i2c0 = &i2c1;
34 i2c1 = &i2c2;
35 i2c2 = &i2c3;
36 i2c3 = &i2c4;
37 mmc0 = &usdhc1;
38 mmc1 = &usdhc2;
39 mmc2 = &usdhc3;
40 serial0 = &uart1;
41 serial1 = &uart2;
42 serial2 = &uart3;
43 serial3 = &uart4;
44 serial4 = &uart5;
45 serial5 = &uart6;
46 serial6 = &uart7;
47 spi0 = &ecspi1;
48 spi1 = &ecspi2;
49 spi2 = &ecspi3;
50 spi3 = &ecspi4;
51 };
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
57 cpu0: cpu@0 {
58 compatible = "arm,cortex-a7";
59 device_type = "cpu";
60 reg = <0>;
61 clock-frequency = <792000000>;
62 clock-latency = <61036>; /* two CLK32 periods */
63 clocks = <&clks IMX7D_CLK_ARM>;
64 };
65 };
67 ckil: clock-cki {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <32768>;
71 clock-output-names = "ckil";
72 };
74 osc: clock-osc {
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <24000000>;
78 clock-output-names = "osc";
79 };
81 usbphynop1: usbphynop1 {
82 compatible = "usb-nop-xceiv";
83 clocks = <&clks IMX7D_USB_PHY1_CLK>;
84 clock-names = "main_clk";
85 #phy-cells = <0>;
86 };
88 usbphynop3: usbphynop3 {
89 compatible = "usb-nop-xceiv";
90 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
91 clock-names = "main_clk";
92 #phy-cells = <0>;
93 };
95 pmu {
96 compatible = "arm,cortex-a7-pmu";
97 interrupt-parent = <&gpc>;
98 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-affinity = <&cpu0>;
100 };
102 replicator {
103 /*
104 * non-configurable replicators don't show up on the
105 * AMBA bus. As such no need to add "arm,primecell"
106 */
107 compatible = "arm,coresight-replicator";
109 ports {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 /* replicator output ports */
113 port@0 {
114 reg = <0>;
115 replicator_out_port0: endpoint {
116 remote-endpoint = <&tpiu_in_port>;
117 };
118 };
120 port@1 {
121 reg = <1>;
122 replicator_out_port1: endpoint {
123 remote-endpoint = <&etr_in_port>;
124 };
125 };
127 /* replicator input port */
128 port@2 {
129 reg = <0>;
130 replicator_in_port0: endpoint {
131 slave-mode;
132 remote-endpoint = <&etf_out_port>;
133 };
134 };
135 };
136 };
138 tempmon: tempmon {
139 compatible = "fsl,imx7d-tempmon";
140 interrupt-parent = <&gpc>;
141 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
142 fsl,tempmon =<&anatop>;
143 nvmem-cells = <&tempmon_calib>,
144 <&tempmon_temp_grade>;
145 nvmem-cell-names = "calib", "temp_grade";
146 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
147 };
149 timer {
150 compatible = "arm,armv7-timer";
151 interrupt-parent = <&intc>;
152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
156 };
158 soc {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "simple-bus";
162 interrupt-parent = <&gpc>;
163 ranges;
165 funnel@30041000 {
166 compatible = "arm,coresight-funnel", "arm,primecell";
167 reg = <0x30041000 0x1000>;
168 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
169 clock-names = "apb_pclk";
171 ca_funnel_ports: ports {
172 #address-cells = <1>;
173 #size-cells = <0>;
175 /* funnel input ports */
176 port@0 {
177 reg = <0>;
178 ca_funnel_in_port0: endpoint {
179 slave-mode;
180 remote-endpoint = <&etm0_out_port>;
181 };
182 };
184 /* funnel output port */
185 port@2 {
186 reg = <0>;
187 ca_funnel_out_port0: endpoint {
188 remote-endpoint = <&hugo_funnel_in_port0>;
189 };
190 };
192 /* the other input ports are not connect to anything */
193 };
194 };
196 etm@3007c000 {
197 compatible = "arm,coresight-etm3x", "arm,primecell";
198 reg = <0x3007c000 0x1000>;
199 cpu = <&cpu0>;
200 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
201 clock-names = "apb_pclk";
203 port {
204 etm0_out_port: endpoint {
205 remote-endpoint = <&ca_funnel_in_port0>;
206 };
207 };
208 };
210 funnel@30083000 {
211 compatible = "arm,coresight-funnel", "arm,primecell";
212 reg = <0x30083000 0x1000>;
213 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
214 clock-names = "apb_pclk";
216 ports {
217 #address-cells = <1>;
218 #size-cells = <0>;
220 /* funnel input ports */
221 port@0 {
222 reg = <0>;
223 hugo_funnel_in_port0: endpoint {
224 slave-mode;
225 remote-endpoint = <&ca_funnel_out_port0>;
226 };
227 };
229 port@1 {
230 reg = <1>;
231 hugo_funnel_in_port1: endpoint {
232 slave-mode; /* M4 input */
233 };
234 };
236 port@2 {
237 reg = <0>;
238 hugo_funnel_out_port0: endpoint {
239 remote-endpoint = <&etf_in_port>;
240 };
241 };
243 /* the other input ports are not connect to anything */
244 };
245 };
247 etf@30084000 {
248 compatible = "arm,coresight-tmc", "arm,primecell";
249 reg = <0x30084000 0x1000>;
250 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
251 clock-names = "apb_pclk";
253 ports {
254 #address-cells = <1>;
255 #size-cells = <0>;
257 port@0 {
258 reg = <0>;
259 etf_in_port: endpoint {
260 slave-mode;
261 remote-endpoint = <&hugo_funnel_out_port0>;
262 };
263 };
265 port@1 {
266 reg = <0>;
267 etf_out_port: endpoint {
268 remote-endpoint = <&replicator_in_port0>;
269 };
270 };
271 };
272 };
274 etr@30086000 {
275 compatible = "arm,coresight-tmc", "arm,primecell";
276 reg = <0x30086000 0x1000>;
277 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
278 clock-names = "apb_pclk";
280 port {
281 etr_in_port: endpoint {
282 slave-mode;
283 remote-endpoint = <&replicator_out_port1>;
284 };
285 };
286 };
288 tpiu@30087000 {
289 compatible = "arm,coresight-tpiu", "arm,primecell";
290 reg = <0x30087000 0x1000>;
291 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
292 clock-names = "apb_pclk";
294 port {
295 tpiu_in_port: endpoint {
296 slave-mode;
297 remote-endpoint = <&replicator_out_port0>;
298 };
299 };
300 };
302 intc: interrupt-controller@31001000 {
303 compatible = "arm,cortex-a7-gic";
304 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
305 #interrupt-cells = <3>;
306 interrupt-controller;
307 interrupt-parent = <&intc>;
308 reg = <0x31001000 0x1000>,
309 <0x31002000 0x2000>,
310 <0x31004000 0x2000>,
311 <0x31006000 0x2000>;
312 };
314 aips1: aips-bus@30000000 {
315 compatible = "fsl,aips-bus", "simple-bus";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 reg = <0x30000000 0x400000>;
319 ranges;
321 gpio1: gpio@30200000 {
322 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
323 reg = <0x30200000 0x10000>;
324 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
325 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
331 };
333 gpio2: gpio@30210000 {
334 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
335 reg = <0x30210000 0x10000>;
336 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 gpio-ranges = <&iomuxc 0 13 32>;
343 };
345 gpio3: gpio@30220000 {
346 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
347 reg = <0x30220000 0x10000>;
348 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 gpio-ranges = <&iomuxc 0 45 29>;
355 };
357 gpio4: gpio@30230000 {
358 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
359 reg = <0x30230000 0x10000>;
360 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 gpio-ranges = <&iomuxc 0 74 24>;
367 };
369 gpio5: gpio@30240000 {
370 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
371 reg = <0x30240000 0x10000>;
372 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 gpio-ranges = <&iomuxc 0 98 18>;
379 };
381 gpio6: gpio@30250000 {
382 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
383 reg = <0x30250000 0x10000>;
384 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 gpio-ranges = <&iomuxc 0 116 23>;
391 };
393 gpio7: gpio@30260000 {
394 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
395 reg = <0x30260000 0x10000>;
396 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
398 gpio-controller;
399 #gpio-cells = <2>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 gpio-ranges = <&iomuxc 0 139 16>;
403 };
405 wdog1: wdog@30280000 {
406 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
407 reg = <0x30280000 0x10000>;
408 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
410 };
412 wdog2: wdog@30290000 {
413 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
414 reg = <0x30290000 0x10000>;
415 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
417 status = "disabled";
418 };
420 wdog3: wdog@302a0000 {
421 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
422 reg = <0x302a0000 0x10000>;
423 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
425 status = "disabled";
426 };
428 wdog4: wdog@302b0000 {
429 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
430 reg = <0x302b0000 0x10000>;
431 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
433 status = "disabled";
434 };
436 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
437 compatible = "fsl,imx7d-iomuxc-lpsr";
438 reg = <0x302c0000 0x10000>;
439 fsl,input-sel = <&iomuxc>;
440 };
442 gpt1: gpt@302d0000 {
443 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
444 reg = <0x302d0000 0x10000>;
445 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clks IMX7D_CLK_DUMMY>,
447 <&clks IMX7D_GPT1_ROOT_CLK>;
448 clock-names = "ipg", "per";
449 };
451 gpt2: gpt@302e0000 {
452 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
453 reg = <0x302e0000 0x10000>;
454 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clks IMX7D_CLK_DUMMY>,
456 <&clks IMX7D_GPT2_ROOT_CLK>;
457 clock-names = "ipg", "per";
458 status = "disabled";
459 };
461 gpt3: gpt@302f0000 {
462 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
463 reg = <0x302f0000 0x10000>;
464 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clks IMX7D_CLK_DUMMY>,
466 <&clks IMX7D_GPT3_ROOT_CLK>;
467 clock-names = "ipg", "per";
468 status = "disabled";
469 };
471 gpt4: gpt@30300000 {
472 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
473 reg = <0x30300000 0x10000>;
474 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clks IMX7D_CLK_DUMMY>,
476 <&clks IMX7D_GPT4_ROOT_CLK>;
477 clock-names = "ipg", "per";
478 status = "disabled";
479 };
481 kpp: kpp@30320000 {
482 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
483 reg = <0x30320000 0x10000>;
484 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
486 status = "disabled";
487 };
489 iomuxc: iomuxc@30330000 {
490 compatible = "fsl,imx7d-iomuxc";
491 reg = <0x30330000 0x10000>;
492 };
494 gpr: iomuxc-gpr@30340000 {
495 compatible = "fsl,imx7d-iomuxc-gpr",
496 "fsl,imx6q-iomuxc-gpr", "syscon";
497 reg = <0x30340000 0x10000>;
498 };
500 ocotp: ocotp-ctrl@30350000 {
501 #address-cells = <1>;
502 #size-cells = <1>;
503 compatible = "fsl,imx7d-ocotp", "syscon";
504 reg = <0x30350000 0x10000>;
505 clocks = <&clks IMX7D_OCOTP_CLK>;
507 tempmon_calib: calib@3c {
508 reg = <0x3c 0x4>;
509 };
511 tempmon_temp_grade: temp-grade@10 {
512 reg = <0x10 0x4>;
513 };
514 };
516 anatop: anatop@30360000 {
517 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
518 "syscon", "simple-bus";
519 reg = <0x30360000 0x10000>;
520 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
523 reg_1p0d: regulator-vdd1p0d {
524 compatible = "fsl,anatop-regulator";
525 regulator-name = "vdd1p0d";
526 regulator-min-microvolt = <800000>;
527 regulator-max-microvolt = <1200000>;
528 anatop-reg-offset = <0x210>;
529 anatop-vol-bit-shift = <8>;
530 anatop-vol-bit-width = <5>;
531 anatop-min-bit-val = <8>;
532 anatop-min-voltage = <800000>;
533 anatop-max-voltage = <1200000>;
534 anatop-enable-bit = <0>;
535 };
537 reg_1p2: regulator-vdd1p2 {
538 compatible = "fsl,anatop-regulator";
539 regulator-name = "vdd1p2";
540 regulator-min-microvolt = <1100000>;
541 regulator-max-microvolt = <1300000>;
542 anatop-reg-offset = <0x220>;
543 anatop-vol-bit-shift = <8>;
544 anatop-vol-bit-width = <5>;
545 anatop-min-bit-val = <0x14>;
546 anatop-min-voltage = <1100000>;
547 anatop-max-voltage = <1300000>;
548 anatop-enable-bit = <0>;
549 };
550 };
552 snvs: snvs@30370000 {
553 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
554 reg = <0x30370000 0x10000>;
556 snvs_rtc: snvs-rtc-lp {
557 compatible = "fsl,sec-v4.0-mon-rtc-lp";
558 regmap = <&snvs>;
559 offset = <0x34>;
560 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clks IMX7D_SNVS_CLK>;
563 clock-names = "snvs-rtc";
564 };
566 snvs_poweroff: snvs-poweroff {
567 compatible = "syscon-poweroff";
568 regmap = <&snvs>;
569 offset = <0x38>;
570 value = <0x60>;
571 mask = <0x60>;
572 };
574 snvs_pwrkey: snvs-powerkey {
575 compatible = "fsl,sec-v4.0-pwrkey";
576 regmap = <&snvs>;
577 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
578 linux,keycode = <KEY_POWER>;
579 wakeup-source;
580 };
581 };
583 clks: ccm@30380000 {
584 compatible = "fsl,imx7d-ccm";
585 reg = <0x30380000 0x10000>;
586 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
588 #clock-cells = <1>;
589 clocks = <&ckil>, <&osc>;
590 clock-names = "ckil", "osc";
591 };
593 src: src@30390000 {
594 compatible = "fsl,imx7d-src", "syscon";
595 reg = <0x30390000 0x10000>;
596 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
597 #reset-cells = <1>;
598 };
600 gpc: gpc@303a0000 {
601 compatible = "fsl,imx7d-gpc";
602 reg = <0x303a0000 0x10000>;
603 interrupt-controller;
604 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
605 #interrupt-cells = <3>;
606 interrupt-parent = <&intc>;
607 #power-domain-cells = <1>;
609 pgc {
610 #address-cells = <1>;
611 #size-cells = <0>;
613 pgc_pcie_phy: pgc-power-domain@1 {
614 #power-domain-cells = <0>;
615 reg = <1>;
616 power-supply = <®_1p0d>;
617 };
618 };
619 };
620 };
622 aips2: aips-bus@30400000 {
623 compatible = "fsl,aips-bus", "simple-bus";
624 #address-cells = <1>;
625 #size-cells = <1>;
626 reg = <0x30400000 0x400000>;
627 ranges;
629 adc1: adc@30610000 {
630 compatible = "fsl,imx7d-adc";
631 reg = <0x30610000 0x10000>;
632 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
634 clock-names = "adc";
635 status = "disabled";
636 };
638 adc2: adc@30620000 {
639 compatible = "fsl,imx7d-adc";
640 reg = <0x30620000 0x10000>;
641 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
643 clock-names = "adc";
644 status = "disabled";
645 };
647 ecspi4: ecspi@30630000 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
651 reg = <0x30630000 0x10000>;
652 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
654 <&clks IMX7D_ECSPI4_ROOT_CLK>;
655 clock-names = "ipg", "per";
656 status = "disabled";
657 };
659 pwm1: pwm@30660000 {
660 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
661 reg = <0x30660000 0x10000>;
662 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
664 <&clks IMX7D_PWM1_ROOT_CLK>;
665 clock-names = "ipg", "per";
666 #pwm-cells = <3>;
667 status = "disabled";
668 };
670 pwm2: pwm@30670000 {
671 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
672 reg = <0x30670000 0x10000>;
673 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
675 <&clks IMX7D_PWM2_ROOT_CLK>;
676 clock-names = "ipg", "per";
677 #pwm-cells = <3>;
678 status = "disabled";
679 };
681 pwm3: pwm@30680000 {
682 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
683 reg = <0x30680000 0x10000>;
684 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
686 <&clks IMX7D_PWM3_ROOT_CLK>;
687 clock-names = "ipg", "per";
688 #pwm-cells = <3>;
689 status = "disabled";
690 };
692 pwm4: pwm@30690000 {
693 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
694 reg = <0x30690000 0x10000>;
695 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
697 <&clks IMX7D_PWM4_ROOT_CLK>;
698 clock-names = "ipg", "per";
699 #pwm-cells = <3>;
700 status = "disabled";
701 };
703 lcdif: lcdif@30730000 {
704 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
705 reg = <0x30730000 0x10000>;
706 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
708 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
709 clock-names = "pix", "axi";
710 status = "disabled";
711 };
712 };
714 aips3: aips-bus@30800000 {
715 compatible = "fsl,aips-bus", "simple-bus";
716 #address-cells = <1>;
717 #size-cells = <1>;
718 reg = <0x30800000 0x400000>;
719 ranges;
721 spba-bus@30800000 {
722 compatible = "fsl,spba-bus", "simple-bus";
723 #address-cells = <1>;
724 #size-cells = <1>;
725 reg = <0x30800000 0x100000>;
726 ranges;
728 ecspi1: ecspi@30820000 {
729 #address-cells = <1>;
730 #size-cells = <0>;
731 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
732 reg = <0x30820000 0x10000>;
733 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
735 <&clks IMX7D_ECSPI1_ROOT_CLK>;
736 clock-names = "ipg", "per";
737 status = "disabled";
738 };
740 ecspi2: ecspi@30830000 {
741 #address-cells = <1>;
742 #size-cells = <0>;
743 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
744 reg = <0x30830000 0x10000>;
745 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
747 <&clks IMX7D_ECSPI2_ROOT_CLK>;
748 clock-names = "ipg", "per";
749 status = "disabled";
750 };
752 ecspi3: ecspi@30840000 {
753 #address-cells = <1>;
754 #size-cells = <0>;
755 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
756 reg = <0x30840000 0x10000>;
757 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
759 <&clks IMX7D_ECSPI3_ROOT_CLK>;
760 clock-names = "ipg", "per";
761 status = "disabled";
762 };
764 uart1: serial@30860000 {
765 compatible = "fsl,imx7d-uart",
766 "fsl,imx6q-uart";
767 reg = <0x30860000 0x10000>;
768 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
770 <&clks IMX7D_UART1_ROOT_CLK>;
771 clock-names = "ipg", "per";
772 status = "disabled";
773 };
775 uart2: serial@30890000 {
776 compatible = "fsl,imx7d-uart",
777 "fsl,imx6q-uart";
778 reg = <0x30890000 0x10000>;
779 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
781 <&clks IMX7D_UART2_ROOT_CLK>;
782 clock-names = "ipg", "per";
783 status = "disabled";
784 };
786 uart3: serial@30880000 {
787 compatible = "fsl,imx7d-uart",
788 "fsl,imx6q-uart";
789 reg = <0x30880000 0x10000>;
790 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
792 <&clks IMX7D_UART3_ROOT_CLK>;
793 clock-names = "ipg", "per";
794 status = "disabled";
795 };
797 sai1: sai@308a0000 {
798 #sound-dai-cells = <0>;
799 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
800 reg = <0x308a0000 0x10000>;
801 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
803 <&clks IMX7D_SAI1_ROOT_CLK>,
804 <&clks IMX7D_CLK_DUMMY>,
805 <&clks IMX7D_CLK_DUMMY>;
806 clock-names = "bus", "mclk1", "mclk2", "mclk3";
807 dma-names = "rx", "tx";
808 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
809 status = "disabled";
810 };
812 sai2: sai@308b0000 {
813 #sound-dai-cells = <0>;
814 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
815 reg = <0x308b0000 0x10000>;
816 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
818 <&clks IMX7D_SAI2_ROOT_CLK>,
819 <&clks IMX7D_CLK_DUMMY>,
820 <&clks IMX7D_CLK_DUMMY>;
821 clock-names = "bus", "mclk1", "mclk2", "mclk3";
822 dma-names = "rx", "tx";
823 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
824 status = "disabled";
825 };
827 sai3: sai@308c0000 {
828 #sound-dai-cells = <0>;
829 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
830 reg = <0x308c0000 0x10000>;
831 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
833 <&clks IMX7D_SAI3_ROOT_CLK>,
834 <&clks IMX7D_CLK_DUMMY>,
835 <&clks IMX7D_CLK_DUMMY>;
836 clock-names = "bus", "mclk1", "mclk2", "mclk3";
837 dma-names = "rx", "tx";
838 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
839 status = "disabled";
840 };
841 };
843 crypto: caam@30900000 {
844 compatible = "fsl,sec-v4.0";
845 #address-cells = <1>;
846 #size-cells = <1>;
847 reg = <0x30900000 0x40000>;
848 ranges = <0 0x30900000 0x40000>;
849 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clks IMX7D_CAAM_CLK>,
851 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
852 clock-names = "ipg", "aclk";
854 sec_jr0: jr0@1000 {
855 compatible = "fsl,sec-v4.0-job-ring";
856 reg = <0x1000 0x1000>;
857 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
858 };
860 sec_jr1: jr1@2000 {
861 compatible = "fsl,sec-v4.0-job-ring";
862 reg = <0x2000 0x1000>;
863 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
864 };
866 sec_jr2: jr1@3000 {
867 compatible = "fsl,sec-v4.0-job-ring";
868 reg = <0x3000 0x1000>;
869 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
870 };
871 };
873 flexcan1: can@30a00000 {
874 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
875 reg = <0x30a00000 0x10000>;
876 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&clks IMX7D_CLK_DUMMY>,
878 <&clks IMX7D_CAN1_ROOT_CLK>;
879 clock-names = "ipg", "per";
880 status = "disabled";
881 };
883 flexcan2: can@30a10000 {
884 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
885 reg = <0x30a10000 0x10000>;
886 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX7D_CLK_DUMMY>,
888 <&clks IMX7D_CAN2_ROOT_CLK>;
889 clock-names = "ipg", "per";
890 status = "disabled";
891 };
893 i2c1: i2c@30a20000 {
894 #address-cells = <1>;
895 #size-cells = <0>;
896 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
897 reg = <0x30a20000 0x10000>;
898 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
900 status = "disabled";
901 };
903 i2c2: i2c@30a30000 {
904 #address-cells = <1>;
905 #size-cells = <0>;
906 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
907 reg = <0x30a30000 0x10000>;
908 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
910 status = "disabled";
911 };
913 i2c3: i2c@30a40000 {
914 #address-cells = <1>;
915 #size-cells = <0>;
916 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
917 reg = <0x30a40000 0x10000>;
918 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
920 status = "disabled";
921 };
923 i2c4: i2c@30a50000 {
924 #address-cells = <1>;
925 #size-cells = <0>;
926 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
927 reg = <0x30a50000 0x10000>;
928 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
930 status = "disabled";
931 };
933 uart4: serial@30a60000 {
934 compatible = "fsl,imx7d-uart",
935 "fsl,imx6q-uart";
936 reg = <0x30a60000 0x10000>;
937 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
939 <&clks IMX7D_UART4_ROOT_CLK>;
940 clock-names = "ipg", "per";
941 status = "disabled";
942 };
944 uart5: serial@30a70000 {
945 compatible = "fsl,imx7d-uart",
946 "fsl,imx6q-uart";
947 reg = <0x30a70000 0x10000>;
948 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
950 <&clks IMX7D_UART5_ROOT_CLK>;
951 clock-names = "ipg", "per";
952 status = "disabled";
953 };
955 uart6: serial@30a80000 {
956 compatible = "fsl,imx7d-uart",
957 "fsl,imx6q-uart";
958 reg = <0x30a80000 0x10000>;
959 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
961 <&clks IMX7D_UART6_ROOT_CLK>;
962 clock-names = "ipg", "per";
963 status = "disabled";
964 };
966 uart7: serial@30a90000 {
967 compatible = "fsl,imx7d-uart",
968 "fsl,imx6q-uart";
969 reg = <0x30a90000 0x10000>;
970 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
972 <&clks IMX7D_UART7_ROOT_CLK>;
973 clock-names = "ipg", "per";
974 status = "disabled";
975 };
977 usbotg1: usb@30b10000 {
978 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
979 reg = <0x30b10000 0x200>;
980 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clks IMX7D_USB_CTRL_CLK>;
982 fsl,usbphy = <&usbphynop1>;
983 fsl,usbmisc = <&usbmisc1 0>;
984 phy-clkgate-delay-us = <400>;
985 status = "disabled";
986 };
988 usbh: usb@30b30000 {
989 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
990 reg = <0x30b30000 0x200>;
991 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clks IMX7D_USB_CTRL_CLK>;
993 fsl,usbphy = <&usbphynop3>;
994 fsl,usbmisc = <&usbmisc3 0>;
995 phy_type = "hsic";
996 dr_mode = "host";
997 phy-clkgate-delay-us = <400>;
998 status = "disabled";
999 };
1001 usbmisc1: usbmisc@30b10200 {
1002 #index-cells = <1>;
1003 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1004 reg = <0x30b10200 0x200>;
1005 };
1007 usbmisc3: usbmisc@30b30200 {
1008 #index-cells = <1>;
1009 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1010 reg = <0x30b30200 0x200>;
1011 };
1013 usdhc1: usdhc@30b40000 {
1014 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1015 reg = <0x30b40000 0x10000>;
1016 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1018 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1019 <&clks IMX7D_USDHC1_ROOT_CLK>;
1020 clock-names = "ipg", "ahb", "per";
1021 bus-width = <4>;
1022 status = "disabled";
1023 };
1025 usdhc2: usdhc@30b50000 {
1026 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1027 reg = <0x30b50000 0x10000>;
1028 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1030 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1031 <&clks IMX7D_USDHC2_ROOT_CLK>;
1032 clock-names = "ipg", "ahb", "per";
1033 bus-width = <4>;
1034 status = "disabled";
1035 };
1037 usdhc3: usdhc@30b60000 {
1038 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1039 reg = <0x30b60000 0x10000>;
1040 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1042 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1043 <&clks IMX7D_USDHC3_ROOT_CLK>;
1044 clock-names = "ipg", "ahb", "per";
1045 bus-width = <4>;
1046 status = "disabled";
1047 };
1049 sdma: sdma@30bd0000 {
1050 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1051 reg = <0x30bd0000 0x10000>;
1052 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1054 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1055 clock-names = "ipg", "ahb";
1056 #dma-cells = <3>;
1057 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1058 };
1060 fec1: ethernet@30be0000 {
1061 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1062 reg = <0x30be0000 0x10000>;
1063 interrupt-names = "int0", "int1", "int2", "pps";
1064 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1069 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1070 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1071 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1072 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1073 clock-names = "ipg", "ahb", "ptp",
1074 "enet_clk_ref", "enet_out";
1075 fsl,num-tx-queues=<3>;
1076 fsl,num-rx-queues=<3>;
1077 status = "disabled";
1078 };
1079 };
1081 dma_apbh: dma-apbh@33000000 {
1082 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1083 reg = <0x33000000 0x2000>;
1084 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1085 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1086 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1087 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1088 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1089 #dma-cells = <1>;
1090 dma-channels = <4>;
1091 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1092 };
1094 gpmi: gpmi-nand@33002000{
1095 compatible = "fsl,imx7d-gpmi-nand";
1096 #address-cells = <1>;
1097 #size-cells = <1>;
1098 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1099 reg-names = "gpmi-nand", "bch";
1100 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1101 interrupt-names = "bch";
1102 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1103 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1104 clock-names = "gpmi_io", "gpmi_bch_apb";
1105 dmas = <&dma_apbh 0>;
1106 dma-names = "rx-tx";
1107 status = "disabled";
1108 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1109 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1110 };
1111 };
1112 };