1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for K2G EVM
4 *
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
6 */
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
11 / {
12 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
13 model = "Texas Instruments K2G General Purpose EVM";
15 memory@800000000 {
16 device_type = "memory";
17 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
18 };
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges;
25 dsp_common_mpm_memory: dsp-common-mpm-memory@81d000000 {
26 compatible = "ti,keystone-dsp-mem-pool";
27 reg = <0x00000008 0x1d000000 0x00000000 0x2800000>;
28 no-map;
29 status = "okay";
30 };
32 dsp_common_memory: dsp-common-memory@81f800000 {
33 compatible = "shared-dma-pool";
34 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
35 reusable;
36 status = "okay";
37 };
38 };
40 vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
41 compatible = "regulator-fixed";
42 regulator-name = "mmc0_fixed";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-always-on;
46 };
48 vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 {
49 compatible = "regulator-fixed";
50 regulator-name = "ldo1";
51 regulator-min-microvolt = <1800000>;
52 regulator-max-microvolt = <1800000>;
53 regulator-always-on;
54 };
55 };
57 &k2g_pinctrl {
58 uart0_pins: pinmux_uart0_pins {
59 pinctrl-single,pins = <
60 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
61 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
62 >;
63 };
65 mmc0_pins: pinmux_mmc0_pins {
66 pinctrl-single,pins = <
67 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
68 K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
69 K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
70 K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
71 K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
72 K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
73 K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */
74 >;
75 };
77 mmc1_pins: pinmux_mmc1_pins {
78 pinctrl-single,pins = <
79 K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */
80 K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */
81 K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */
82 K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */
83 K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
84 K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
85 K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
86 K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
87 K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
88 K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
89 >;
90 };
92 i2c0_pins: pinmux_i2c0_pins {
93 pinctrl-single,pins = <
94 K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
95 K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
96 >;
97 };
99 ecap0_pins: ecap0_pins {
100 pinctrl-single,pins = <
101 K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */
102 >;
103 };
105 spi1_pins: pinmux_spi1_pins {
106 pinctrl-single,pins = <
107 K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */
108 K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */
109 K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */
110 K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */
111 >;
112 };
114 qspi_pins: pinmux_qspi_pins {
115 pinctrl-single,pins = <
116 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
117 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
118 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
119 K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
120 K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
121 K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
122 K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
123 >;
124 };
126 uart2_pins: pinmux_uart2_pins {
127 pinctrl-single,pins = <
128 K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */
129 K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */
130 >;
131 };
133 dcan0_pins: pinmux_dcan0_pins {
134 pinctrl-single,pins = <
135 K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */
136 K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */
137 >;
138 };
140 dcan1_pins: pinmux_dcan1_pins {
141 pinctrl-single,pins = <
142 K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */
143 K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */
144 >;
145 };
147 emac_pins: pinmux_emac_pins {
148 pinctrl-single,pins = <
149 K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
150 K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
151 K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
152 K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
153 K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
154 K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
155 K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
156 K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
157 K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
158 K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
159 K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
160 K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
161 >;
162 };
164 mdio_pins: pinmux_mdio_pins {
165 pinctrl-single,pins = <
166 K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
167 K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
168 >;
169 };
170 };
172 &uart0 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&uart0_pins>;
175 status = "okay";
176 };
178 &gpio1 {
179 status = "okay";
180 };
182 &mmc0 {
183 pinctrl-names = "default";
184 pinctrl-0 = <&mmc0_pins>;
185 vmmc-supply = <&vcc3v3_dcin_reg>;
186 vqmmc-supply = <&vcc3v3_dcin_reg>;
187 cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
188 status = "okay";
189 };
191 &mmc1 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&mmc1_pins>;
194 vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
195 vqmmc-supply = <&vcc1v8_ldo1_reg>;
196 ti,non-removable;
197 status = "okay";
198 };
200 &dsp0 {
201 memory-region = <&dsp_common_memory>;
202 status = "okay";
203 };
205 &i2c0 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&i2c0_pins>;
208 status = "okay";
210 eeprom@50 {
211 compatible = "atmel,24c1024";
212 reg = <0x50>;
213 };
214 };
216 &keystone_usb0 {
217 status = "okay";
218 };
220 &usb0_phy {
221 status = "okay";
222 };
224 &usb0 {
225 dr_mode = "host";
226 status = "okay";
227 };
229 &keystone_usb1 {
230 status = "okay";
231 };
233 &usb1_phy {
234 status = "okay";
235 };
237 &usb1 {
238 dr_mode = "peripheral";
239 status = "okay";
240 };
242 &ecap0 {
243 status = "okay";
244 pinctrl-names = "default";
245 pinctrl-0 = <&ecap0_pins>;
246 };
248 &spi1 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&spi1_pins>;
251 status = "okay";
253 spi_nor: flash@0 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 compatible = "jedec,spi-nor";
257 spi-max-frequency = <5000000>;
258 m25p,fast-read;
259 reg = <0>;
261 partition@0 {
262 label = "u-boot-spl";
263 reg = <0x0 0x100000>;
264 read-only;
265 };
267 partition@1 {
268 label = "misc";
269 reg = <0x100000 0xf00000>;
270 };
271 };
272 };
274 &qspi {
275 status = "okay";
276 pinctrl-names = "default";
277 pinctrl-0 = <&qspi_pins>;
278 cdns,rclk-en;
280 flash0: m25p80@0 {
281 compatible = "s25fl512s", "jedec,spi-nor";
282 reg = <0>;
283 spi-tx-bus-width = <1>;
284 spi-rx-bus-width = <4>;
285 spi-max-frequency = <96000000>;
286 #address-cells = <1>;
287 #size-cells = <1>;
288 cdns,read-delay = <5>;
289 cdns,tshsl-ns = <500>;
290 cdns,tsd2d-ns = <500>;
291 cdns,tchsh-ns = <119>;
292 cdns,tslch-ns = <119>;
294 partition@0 {
295 label = "QSPI.u-boot-spl-os";
296 reg = <0x00000000 0x00100000>;
297 };
298 partition@1 {
299 label = "QSPI.u-boot-env";
300 reg = <0x00100000 0x00040000>;
301 };
302 partition@2 {
303 label = "QSPI.skern";
304 reg = <0x00140000 0x0040000>;
305 };
306 partition@3 {
307 label = "QSPI.pmmc-firmware";
308 reg = <0x00180000 0x0040000>;
309 };
310 partition@4 {
311 label = "QSPI.kernel";
312 reg = <0x001C0000 0x0800000>;
313 };
314 partition@5 {
315 label = "QSPI.file-system";
316 reg = <0x009C0000 0x3640000>;
317 };
318 };
319 };
321 &uart2 {
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart2_pins>;
324 status = "okay";
325 };
327 &dcan0 {
328 pinctrl-names = "default";
329 pinctrl-0 = <&dcan0_pins>;
330 status = "okay";
331 };
333 &dcan1 {
334 pinctrl-names = "default";
335 pinctrl-0 = <&dcan1_pins>;
336 status = "okay";
337 };
339 &qmss {
340 status = "okay";
341 };
343 &knav_dmas {
344 status = "okay";
345 };
347 &mdio {
348 pinctrl-names = "default";
349 pinctrl-0 = <&mdio_pins>;
350 status = "okay";
351 ethphy0: ethernet-phy@0 {
352 reg = <0>;
353 };
354 };
356 &gbe0 {
357 phy-handle = <ðphy0>;
358 phy-mode = "rgmii-id";
359 status = "okay";
360 };
362 &netcp {
363 pinctrl-names = "default";
364 pinctrl-0 = <&emac_pins>;
365 status = "okay";
366 };