1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/i2c-omap.h>
25 #include <linux/omap-dma.h>
27 #include "omap_hwmod.h"
28 #include "omap_hwmod_common_data.h"
29 #include "cm1_7xx.h"
30 #include "cm2_7xx.h"
31 #include "prm7xx.h"
32 #include "i2c.h"
33 #include "wd_timer.h"
34 #include "soc.h"
36 /* Base offset for all DRA7XX interrupts external to MPUSS */
37 #define DRA7XX_IRQ_GIC_START 32
39 /* Base offset for all DRA7XX dma requests */
40 #define DRA7XX_DMA_REQ_START 1
43 /*
44 * IP blocks
45 */
47 /*
48 * 'dmm' class
49 * instance(s): dmm
50 */
51 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
52 .name = "dmm",
53 };
55 /* dmm */
56 static struct omap_hwmod dra7xx_dmm_hwmod = {
57 .name = "dmm",
58 .class = &dra7xx_dmm_hwmod_class,
59 .clkdm_name = "emif_clkdm",
60 .prcm = {
61 .omap4 = {
62 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
63 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
64 },
65 },
66 };
68 /*
69 * 'l3' class
70 * instance(s): l3_instr, l3_main_1, l3_main_2
71 */
72 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
73 .name = "l3",
74 };
76 /* l3_instr */
77 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
78 .name = "l3_instr",
79 .class = &dra7xx_l3_hwmod_class,
80 .clkdm_name = "l3instr_clkdm",
81 .prcm = {
82 .omap4 = {
83 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
84 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
85 .modulemode = MODULEMODE_HWCTRL,
86 },
87 },
88 };
90 /* l3_main_1 */
91 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
92 .name = "l3_main_1",
93 .class = &dra7xx_l3_hwmod_class,
94 .clkdm_name = "l3main1_clkdm",
95 .prcm = {
96 .omap4 = {
97 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
98 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
99 },
100 },
101 };
103 /* l3_main_2 */
104 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
105 .name = "l3_main_2",
106 .class = &dra7xx_l3_hwmod_class,
107 .clkdm_name = "l3instr_clkdm",
108 .prcm = {
109 .omap4 = {
110 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
111 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
112 .modulemode = MODULEMODE_HWCTRL,
113 },
114 },
115 };
117 /*
118 * 'l4' class
119 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
120 */
121 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
122 .name = "l4",
123 };
125 /* l4_cfg */
126 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
127 .name = "l4_cfg",
128 .class = &dra7xx_l4_hwmod_class,
129 .clkdm_name = "l4cfg_clkdm",
130 .prcm = {
131 .omap4 = {
132 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
133 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
134 },
135 },
136 };
138 /* l4_per1 */
139 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
140 .name = "l4_per1",
141 .class = &dra7xx_l4_hwmod_class,
142 .clkdm_name = "l4per_clkdm",
143 .prcm = {
144 .omap4 = {
145 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
146 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
147 },
148 },
149 };
151 /* l4_per2 */
152 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
153 .name = "l4_per2",
154 .class = &dra7xx_l4_hwmod_class,
155 .clkdm_name = "l4per2_clkdm",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
159 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
160 },
161 },
162 };
164 /* l4_per3 */
165 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
166 .name = "l4_per3",
167 .class = &dra7xx_l4_hwmod_class,
168 .clkdm_name = "l4per3_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
172 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173 },
174 },
175 };
177 /* l4_wkup */
178 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
179 .name = "l4_wkup",
180 .class = &dra7xx_l4_hwmod_class,
181 .clkdm_name = "wkupaon_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
185 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
186 },
187 },
188 };
190 /*
191 * 'atl' class
192 *
193 */
195 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
196 .name = "atl",
197 };
199 /* atl */
200 static struct omap_hwmod dra7xx_atl_hwmod = {
201 .name = "atl",
202 .class = &dra7xx_atl_hwmod_class,
203 .clkdm_name = "atl_clkdm",
204 .main_clk = "atl_gfclk_mux",
205 .prcm = {
206 .omap4 = {
207 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
208 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
209 .modulemode = MODULEMODE_SWCTRL,
210 },
211 },
212 };
214 /*
215 * 'bb2d' class
216 *
217 */
219 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
220 .name = "bb2d",
221 };
223 /* bb2d */
224 static struct omap_hwmod dra7xx_bb2d_hwmod = {
225 .name = "bb2d",
226 .class = &dra7xx_bb2d_hwmod_class,
227 .clkdm_name = "dss_clkdm",
228 .main_clk = "dpll_core_h24x2_ck",
229 .prcm = {
230 .omap4 = {
231 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
232 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
233 .modulemode = MODULEMODE_SWCTRL,
234 },
235 },
236 };
238 /*
239 * 'counter' class
240 *
241 */
243 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
244 .rev_offs = 0x0000,
245 .sysc_offs = 0x0010,
246 .sysc_flags = SYSC_HAS_SIDLEMODE,
247 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
248 SIDLE_SMART_WKUP),
249 .sysc_fields = &omap_hwmod_sysc_type1,
250 };
252 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
253 .name = "counter",
254 .sysc = &dra7xx_counter_sysc,
255 };
257 /* counter_32k */
258 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
259 .name = "counter_32k",
260 .class = &dra7xx_counter_hwmod_class,
261 .clkdm_name = "wkupaon_clkdm",
262 .flags = HWMOD_SWSUP_SIDLE,
263 .main_clk = "wkupaon_iclk_mux",
264 .prcm = {
265 .omap4 = {
266 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
267 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
268 },
269 },
270 };
272 /*
273 * 'ctrl_module' class
274 *
275 */
277 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
278 .name = "ctrl_module",
279 };
281 /* ctrl_module_wkup */
282 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
283 .name = "ctrl_module_wkup",
284 .class = &dra7xx_ctrl_module_hwmod_class,
285 .clkdm_name = "wkupaon_clkdm",
286 .prcm = {
287 .omap4 = {
288 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
289 },
290 },
291 };
293 /*
294 * 'gmac' class
295 * cpsw/gmac sub system
296 */
297 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
298 .rev_offs = 0x0,
299 .sysc_offs = 0x8,
300 .syss_offs = 0x4,
301 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
302 SYSS_HAS_RESET_STATUS),
303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
304 MSTANDBY_NO),
305 .sysc_fields = &omap_hwmod_sysc_type3,
306 };
308 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
309 .name = "gmac",
310 .sysc = &dra7xx_gmac_sysc,
311 };
313 static struct omap_hwmod dra7xx_gmac_hwmod = {
314 .name = "gmac",
315 .class = &dra7xx_gmac_hwmod_class,
316 .clkdm_name = "gmac_clkdm",
317 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
318 .main_clk = "dpll_gmac_ck",
319 .mpu_rt_idx = 1,
320 .prcm = {
321 .omap4 = {
322 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
323 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
324 .modulemode = MODULEMODE_SWCTRL,
325 },
326 },
327 };
329 /*
330 * 'mdio' class
331 */
332 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
333 .name = "davinci_mdio",
334 };
336 static struct omap_hwmod dra7xx_mdio_hwmod = {
337 .name = "davinci_mdio",
338 .class = &dra7xx_mdio_hwmod_class,
339 .clkdm_name = "gmac_clkdm",
340 .main_clk = "dpll_gmac_ck",
341 };
343 /*
344 * 'dcan' class
345 *
346 */
348 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
349 .name = "dcan",
350 };
352 /* dcan1 */
353 static struct omap_hwmod dra7xx_dcan1_hwmod = {
354 .name = "dcan1",
355 .class = &dra7xx_dcan_hwmod_class,
356 .clkdm_name = "wkupaon_clkdm",
357 .main_clk = "dcan1_sys_clk_mux",
358 .flags = HWMOD_CLKDM_NOAUTO,
359 .prcm = {
360 .omap4 = {
361 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
362 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
363 .modulemode = MODULEMODE_SWCTRL,
364 },
365 },
366 };
368 /* dcan2 */
369 static struct omap_hwmod dra7xx_dcan2_hwmod = {
370 .name = "dcan2",
371 .class = &dra7xx_dcan_hwmod_class,
372 .clkdm_name = "l4per2_clkdm",
373 .main_clk = "sys_clkin1",
374 .flags = HWMOD_CLKDM_NOAUTO,
375 .prcm = {
376 .omap4 = {
377 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
378 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
379 .modulemode = MODULEMODE_SWCTRL,
380 },
381 },
382 };
384 /* pwmss */
385 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
386 .rev_offs = 0x0,
387 .sysc_offs = 0x4,
388 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
389 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
390 .sysc_fields = &omap_hwmod_sysc_type2,
391 };
393 /*
394 * epwmss class
395 */
396 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
397 .name = "epwmss",
398 .sysc = &dra7xx_epwmss_sysc,
399 };
401 /* epwmss0 */
402 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
403 .name = "epwmss0",
404 .class = &dra7xx_epwmss_hwmod_class,
405 .clkdm_name = "l4per2_clkdm",
406 .main_clk = "l4_root_clk_div",
407 .prcm = {
408 .omap4 = {
409 .modulemode = MODULEMODE_SWCTRL,
410 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
412 },
413 },
414 };
416 /* epwmss1 */
417 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
418 .name = "epwmss1",
419 .class = &dra7xx_epwmss_hwmod_class,
420 .clkdm_name = "l4per2_clkdm",
421 .main_clk = "l4_root_clk_div",
422 .prcm = {
423 .omap4 = {
424 .modulemode = MODULEMODE_SWCTRL,
425 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
427 },
428 },
429 };
431 /* epwmss2 */
432 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
433 .name = "epwmss2",
434 .class = &dra7xx_epwmss_hwmod_class,
435 .clkdm_name = "l4per2_clkdm",
436 .main_clk = "l4_root_clk_div",
437 .prcm = {
438 .omap4 = {
439 .modulemode = MODULEMODE_SWCTRL,
440 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
441 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
442 },
443 },
444 };
446 /*
447 * 'dma' class
448 *
449 */
451 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
452 .rev_offs = 0x0000,
453 .sysc_offs = 0x002c,
454 .syss_offs = 0x0028,
455 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
456 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
457 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
458 SYSS_HAS_RESET_STATUS),
459 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
460 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
461 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
462 .sysc_fields = &omap_hwmod_sysc_type1,
463 };
465 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
466 .name = "dma",
467 .sysc = &dra7xx_dma_sysc,
468 };
470 /* dma dev_attr */
471 static struct omap_dma_dev_attr dma_dev_attr = {
472 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
473 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
474 .lch_count = 32,
475 };
477 /* dma_system */
478 static struct omap_hwmod dra7xx_dma_system_hwmod = {
479 .name = "dma_system",
480 .class = &dra7xx_dma_hwmod_class,
481 .clkdm_name = "dma_clkdm",
482 .main_clk = "l3_iclk_div",
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
486 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
487 },
488 },
489 .dev_attr = &dma_dev_attr,
490 };
492 /*
493 * 'tpcc' class
494 *
495 */
496 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
497 .name = "tpcc",
498 };
500 static struct omap_hwmod dra7xx_tpcc_hwmod = {
501 .name = "tpcc",
502 .class = &dra7xx_tpcc_hwmod_class,
503 .clkdm_name = "l3main1_clkdm",
504 .main_clk = "l3_iclk_div",
505 .prcm = {
506 .omap4 = {
507 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
508 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
509 },
510 },
511 };
513 /*
514 * 'tptc' class
515 *
516 */
517 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
518 .name = "tptc",
519 };
521 /* tptc0 */
522 static struct omap_hwmod dra7xx_tptc0_hwmod = {
523 .name = "tptc0",
524 .class = &dra7xx_tptc_hwmod_class,
525 .clkdm_name = "l3main1_clkdm",
526 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
527 .main_clk = "l3_iclk_div",
528 .prcm = {
529 .omap4 = {
530 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
531 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
532 .modulemode = MODULEMODE_HWCTRL,
533 },
534 },
535 };
537 /* tptc1 */
538 static struct omap_hwmod dra7xx_tptc1_hwmod = {
539 .name = "tptc1",
540 .class = &dra7xx_tptc_hwmod_class,
541 .clkdm_name = "l3main1_clkdm",
542 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
543 .main_clk = "l3_iclk_div",
544 .prcm = {
545 .omap4 = {
546 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
547 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
548 .modulemode = MODULEMODE_HWCTRL,
549 },
550 },
551 };
553 /*
554 * 'dss' class
555 *
556 */
558 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
559 .rev_offs = 0x0000,
560 .syss_offs = 0x0014,
561 .sysc_flags = SYSS_HAS_RESET_STATUS,
562 };
564 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
565 .name = "dss",
566 .sysc = &dra7xx_dss_sysc,
567 .reset = omap_dss_reset,
568 };
570 /* dss */
571 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
572 { .role = "dss_clk", .clk = "dss_dss_clk" },
573 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
574 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
575 { .role = "video2_clk", .clk = "dss_video2_clk" },
576 { .role = "video1_clk", .clk = "dss_video1_clk" },
577 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
578 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
579 };
581 static struct omap_hwmod dra7xx_dss_hwmod = {
582 .name = "dss_core",
583 .class = &dra7xx_dss_hwmod_class,
584 .clkdm_name = "dss_clkdm",
585 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
586 .main_clk = "dss_dss_clk",
587 .prcm = {
588 .omap4 = {
589 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
590 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
591 .modulemode = MODULEMODE_SWCTRL,
592 },
593 },
594 .opt_clks = dss_opt_clks,
595 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
596 };
598 /*
599 * 'dispc' class
600 * display controller
601 */
603 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
604 .rev_offs = 0x0000,
605 .sysc_offs = 0x0010,
606 .syss_offs = 0x0014,
607 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
608 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
609 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
610 SYSS_HAS_RESET_STATUS),
611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
612 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
613 .sysc_fields = &omap_hwmod_sysc_type1,
614 };
616 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
617 .name = "dispc",
618 .sysc = &dra7xx_dispc_sysc,
619 };
621 /* dss_dispc */
622 /* dss_dispc dev_attr */
623 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
624 .has_framedonetv_irq = 1,
625 .manager_count = 4,
626 };
628 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
629 .name = "dss_dispc",
630 .class = &dra7xx_dispc_hwmod_class,
631 .clkdm_name = "dss_clkdm",
632 .main_clk = "dss_dss_clk",
633 .prcm = {
634 .omap4 = {
635 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
636 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
637 },
638 },
639 .dev_attr = &dss_dispc_dev_attr,
640 .parent_hwmod = &dra7xx_dss_hwmod,
641 };
643 /*
644 * 'hdmi' class
645 * hdmi controller
646 */
648 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
649 .rev_offs = 0x0000,
650 .sysc_offs = 0x0010,
651 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
652 SYSC_HAS_SOFTRESET),
653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
654 SIDLE_SMART_WKUP),
655 .sysc_fields = &omap_hwmod_sysc_type2,
656 };
658 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
659 .name = "hdmi",
660 .sysc = &dra7xx_hdmi_sysc,
661 };
663 /* dss_hdmi */
665 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
666 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
667 };
669 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
670 .name = "dss_hdmi",
671 .class = &dra7xx_hdmi_hwmod_class,
672 .clkdm_name = "dss_clkdm",
673 .main_clk = "dss_48mhz_clk",
674 .prcm = {
675 .omap4 = {
676 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
677 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
678 },
679 },
680 .opt_clks = dss_hdmi_opt_clks,
681 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
682 .parent_hwmod = &dra7xx_dss_hwmod,
683 };
685 /* AES (the 'P' (public) device) */
686 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
687 .rev_offs = 0x0080,
688 .sysc_offs = 0x0084,
689 .syss_offs = 0x0088,
690 .sysc_flags = SYSS_HAS_RESET_STATUS,
691 };
693 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
694 .name = "aes",
695 .sysc = &dra7xx_aes_sysc,
696 .rev = 2,
697 };
699 /* AES1 */
700 static struct omap_hwmod dra7xx_aes1_hwmod = {
701 .name = "aes1",
702 .class = &dra7xx_aes_hwmod_class,
703 .clkdm_name = "l4sec_clkdm",
704 .main_clk = "l3_iclk_div",
705 .prcm = {
706 .omap4 = {
707 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
708 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
709 .modulemode = MODULEMODE_HWCTRL,
710 },
711 },
712 };
714 /* AES2 */
715 static struct omap_hwmod dra7xx_aes2_hwmod = {
716 .name = "aes2",
717 .class = &dra7xx_aes_hwmod_class,
718 .clkdm_name = "l4sec_clkdm",
719 .main_clk = "l3_iclk_div",
720 .prcm = {
721 .omap4 = {
722 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
723 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
724 .modulemode = MODULEMODE_HWCTRL,
725 },
726 },
727 };
729 /* sha0 HIB2 (the 'P' (public) device) */
730 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
731 .rev_offs = 0x100,
732 .sysc_offs = 0x110,
733 .syss_offs = 0x114,
734 .sysc_flags = SYSS_HAS_RESET_STATUS,
735 };
737 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
738 .name = "sham",
739 .sysc = &dra7xx_sha0_sysc,
740 .rev = 2,
741 };
743 struct omap_hwmod dra7xx_sha0_hwmod = {
744 .name = "sham",
745 .class = &dra7xx_sha0_hwmod_class,
746 .clkdm_name = "l4sec_clkdm",
747 .main_clk = "l3_iclk_div",
748 .prcm = {
749 .omap4 = {
750 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
751 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
752 .modulemode = MODULEMODE_HWCTRL,
753 },
754 },
755 };
757 /*
758 * 'elm' class
759 *
760 */
762 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
763 .rev_offs = 0x0000,
764 .sysc_offs = 0x0010,
765 .syss_offs = 0x0014,
766 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
767 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
768 SYSS_HAS_RESET_STATUS),
769 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
770 SIDLE_SMART_WKUP),
771 .sysc_fields = &omap_hwmod_sysc_type1,
772 };
774 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
775 .name = "elm",
776 .sysc = &dra7xx_elm_sysc,
777 };
779 /* elm */
781 static struct omap_hwmod dra7xx_elm_hwmod = {
782 .name = "elm",
783 .class = &dra7xx_elm_hwmod_class,
784 .clkdm_name = "l4per_clkdm",
785 .main_clk = "l3_iclk_div",
786 .prcm = {
787 .omap4 = {
788 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
789 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
790 },
791 },
792 };
794 /*
795 * 'gpio' class
796 *
797 */
799 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
800 .rev_offs = 0x0000,
801 .sysc_offs = 0x0010,
802 .syss_offs = 0x0114,
803 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
804 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
805 SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
807 SIDLE_SMART_WKUP),
808 .sysc_fields = &omap_hwmod_sysc_type1,
809 };
811 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
812 .name = "gpio",
813 .sysc = &dra7xx_gpio_sysc,
814 .rev = 2,
815 };
817 /* gpio1 */
818 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
819 { .role = "dbclk", .clk = "gpio1_dbclk" },
820 };
822 static struct omap_hwmod dra7xx_gpio1_hwmod = {
823 .name = "gpio1",
824 .class = &dra7xx_gpio_hwmod_class,
825 .clkdm_name = "wkupaon_clkdm",
826 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
827 .main_clk = "wkupaon_iclk_mux",
828 .prcm = {
829 .omap4 = {
830 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
831 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
832 .modulemode = MODULEMODE_HWCTRL,
833 },
834 },
835 .opt_clks = gpio1_opt_clks,
836 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
837 };
839 /* gpio2 */
840 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
841 { .role = "dbclk", .clk = "gpio2_dbclk" },
842 };
844 static struct omap_hwmod dra7xx_gpio2_hwmod = {
845 .name = "gpio2",
846 .class = &dra7xx_gpio_hwmod_class,
847 .clkdm_name = "l4per_clkdm",
848 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
849 .main_clk = "l3_iclk_div",
850 .prcm = {
851 .omap4 = {
852 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
853 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
854 .modulemode = MODULEMODE_HWCTRL,
855 },
856 },
857 .opt_clks = gpio2_opt_clks,
858 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
859 };
861 /* gpio3 */
862 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
863 { .role = "dbclk", .clk = "gpio3_dbclk" },
864 };
866 static struct omap_hwmod dra7xx_gpio3_hwmod = {
867 .name = "gpio3",
868 .class = &dra7xx_gpio_hwmod_class,
869 .clkdm_name = "l4per_clkdm",
870 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
871 .main_clk = "l3_iclk_div",
872 .prcm = {
873 .omap4 = {
874 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
875 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
876 .modulemode = MODULEMODE_HWCTRL,
877 },
878 },
879 .opt_clks = gpio3_opt_clks,
880 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
881 };
883 /* gpio4 */
884 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
885 { .role = "dbclk", .clk = "gpio4_dbclk" },
886 };
888 static struct omap_hwmod dra7xx_gpio4_hwmod = {
889 .name = "gpio4",
890 .class = &dra7xx_gpio_hwmod_class,
891 .clkdm_name = "l4per_clkdm",
892 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
893 .main_clk = "l3_iclk_div",
894 .prcm = {
895 .omap4 = {
896 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
897 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
898 .modulemode = MODULEMODE_HWCTRL,
899 },
900 },
901 .opt_clks = gpio4_opt_clks,
902 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
903 };
905 /* gpio5 */
906 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
907 { .role = "dbclk", .clk = "gpio5_dbclk" },
908 };
910 static struct omap_hwmod dra7xx_gpio5_hwmod = {
911 .name = "gpio5",
912 .class = &dra7xx_gpio_hwmod_class,
913 .clkdm_name = "l4per_clkdm",
914 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
915 .main_clk = "l3_iclk_div",
916 .prcm = {
917 .omap4 = {
918 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
919 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
920 .modulemode = MODULEMODE_HWCTRL,
921 },
922 },
923 .opt_clks = gpio5_opt_clks,
924 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
925 };
927 /* gpio6 */
928 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
929 { .role = "dbclk", .clk = "gpio6_dbclk" },
930 };
932 static struct omap_hwmod dra7xx_gpio6_hwmod = {
933 .name = "gpio6",
934 .class = &dra7xx_gpio_hwmod_class,
935 .clkdm_name = "l4per_clkdm",
936 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
937 .main_clk = "l3_iclk_div",
938 .prcm = {
939 .omap4 = {
940 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
941 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
942 .modulemode = MODULEMODE_HWCTRL,
943 },
944 },
945 .opt_clks = gpio6_opt_clks,
946 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
947 };
949 /* gpio7 */
950 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
951 { .role = "dbclk", .clk = "gpio7_dbclk" },
952 };
954 static struct omap_hwmod dra7xx_gpio7_hwmod = {
955 .name = "gpio7",
956 .class = &dra7xx_gpio_hwmod_class,
957 .clkdm_name = "l4per_clkdm",
958 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
959 .main_clk = "l3_iclk_div",
960 .prcm = {
961 .omap4 = {
962 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
963 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
964 .modulemode = MODULEMODE_HWCTRL,
965 },
966 },
967 .opt_clks = gpio7_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
969 };
971 /* gpio8 */
972 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
973 { .role = "dbclk", .clk = "gpio8_dbclk" },
974 };
976 static struct omap_hwmod dra7xx_gpio8_hwmod = {
977 .name = "gpio8",
978 .class = &dra7xx_gpio_hwmod_class,
979 .clkdm_name = "l4per_clkdm",
980 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
981 .main_clk = "l3_iclk_div",
982 .prcm = {
983 .omap4 = {
984 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
985 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
986 .modulemode = MODULEMODE_HWCTRL,
987 },
988 },
989 .opt_clks = gpio8_opt_clks,
990 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
991 };
993 /*
994 * 'gpmc' class
995 *
996 */
998 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
999 .rev_offs = 0x0000,
1000 .sysc_offs = 0x0010,
1001 .syss_offs = 0x0014,
1002 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1003 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1005 .sysc_fields = &omap_hwmod_sysc_type1,
1006 };
1008 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1009 .name = "gpmc",
1010 .sysc = &dra7xx_gpmc_sysc,
1011 };
1013 /* gpmc */
1015 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1016 .name = "gpmc",
1017 .class = &dra7xx_gpmc_hwmod_class,
1018 .clkdm_name = "l3main1_clkdm",
1019 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1020 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1021 .main_clk = "l3_iclk_div",
1022 .prcm = {
1023 .omap4 = {
1024 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1025 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1026 .modulemode = MODULEMODE_HWCTRL,
1027 },
1028 },
1029 };
1031 /*
1032 * 'hdq1w' class
1033 *
1034 */
1036 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1037 .rev_offs = 0x0000,
1038 .sysc_offs = 0x0014,
1039 .syss_offs = 0x0018,
1040 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1041 SYSS_HAS_RESET_STATUS),
1042 .sysc_fields = &omap_hwmod_sysc_type1,
1043 };
1045 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1046 .name = "hdq1w",
1047 .sysc = &dra7xx_hdq1w_sysc,
1048 };
1050 /* hdq1w */
1052 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1053 .name = "hdq1w",
1054 .class = &dra7xx_hdq1w_hwmod_class,
1055 .clkdm_name = "l4per_clkdm",
1056 .flags = HWMOD_INIT_NO_RESET,
1057 .main_clk = "func_12m_fclk",
1058 .prcm = {
1059 .omap4 = {
1060 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1061 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1062 .modulemode = MODULEMODE_SWCTRL,
1063 },
1064 },
1065 };
1067 /*
1068 * 'i2c' class
1069 *
1070 */
1072 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1073 .rev_offs = 0,
1074 .sysc_offs = 0x0010,
1075 .syss_offs = 0x0090,
1076 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1077 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1078 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1079 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1080 SIDLE_SMART_WKUP),
1081 .sysc_fields = &omap_hwmod_sysc_type1,
1082 };
1084 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1085 .name = "i2c",
1086 .sysc = &dra7xx_i2c_sysc,
1087 .reset = &omap_i2c_reset,
1088 .rev = OMAP_I2C_IP_VERSION_2,
1089 };
1091 /* i2c1 */
1092 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1093 .name = "i2c1",
1094 .class = &dra7xx_i2c_hwmod_class,
1095 .clkdm_name = "l4per_clkdm",
1096 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1097 .main_clk = "func_96m_fclk",
1098 .prcm = {
1099 .omap4 = {
1100 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1101 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1102 .modulemode = MODULEMODE_SWCTRL,
1103 },
1104 },
1105 };
1107 /* i2c2 */
1108 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1109 .name = "i2c2",
1110 .class = &dra7xx_i2c_hwmod_class,
1111 .clkdm_name = "l4per_clkdm",
1112 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1113 .main_clk = "func_96m_fclk",
1114 .prcm = {
1115 .omap4 = {
1116 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1117 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1118 .modulemode = MODULEMODE_SWCTRL,
1119 },
1120 },
1121 };
1123 /* i2c3 */
1124 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1125 .name = "i2c3",
1126 .class = &dra7xx_i2c_hwmod_class,
1127 .clkdm_name = "l4per_clkdm",
1128 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1129 .main_clk = "func_96m_fclk",
1130 .prcm = {
1131 .omap4 = {
1132 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1133 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1134 .modulemode = MODULEMODE_SWCTRL,
1135 },
1136 },
1137 };
1139 /* i2c4 */
1140 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1141 .name = "i2c4",
1142 .class = &dra7xx_i2c_hwmod_class,
1143 .clkdm_name = "l4per_clkdm",
1144 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1145 .main_clk = "func_96m_fclk",
1146 .prcm = {
1147 .omap4 = {
1148 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1149 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1150 .modulemode = MODULEMODE_SWCTRL,
1151 },
1152 },
1153 };
1155 /* i2c5 */
1156 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1157 .name = "i2c5",
1158 .class = &dra7xx_i2c_hwmod_class,
1159 .clkdm_name = "ipu_clkdm",
1160 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1161 .main_clk = "func_96m_fclk",
1162 .prcm = {
1163 .omap4 = {
1164 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1165 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1166 .modulemode = MODULEMODE_SWCTRL,
1167 },
1168 },
1169 };
1171 /*
1172 * 'mailbox' class
1173 *
1174 */
1176 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1177 .rev_offs = 0x0000,
1178 .sysc_offs = 0x0010,
1179 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1180 SYSC_HAS_SOFTRESET),
1181 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1182 .sysc_fields = &omap_hwmod_sysc_type2,
1183 };
1185 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1186 .name = "mailbox",
1187 .sysc = &dra7xx_mailbox_sysc,
1188 };
1190 /* mailbox1 */
1191 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1192 .name = "mailbox1",
1193 .class = &dra7xx_mailbox_hwmod_class,
1194 .clkdm_name = "l4cfg_clkdm",
1195 .prcm = {
1196 .omap4 = {
1197 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1198 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1199 },
1200 },
1201 };
1203 /* mailbox2 */
1204 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1205 .name = "mailbox2",
1206 .class = &dra7xx_mailbox_hwmod_class,
1207 .clkdm_name = "l4cfg_clkdm",
1208 .prcm = {
1209 .omap4 = {
1210 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1211 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1212 },
1213 },
1214 };
1216 /* mailbox3 */
1217 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1218 .name = "mailbox3",
1219 .class = &dra7xx_mailbox_hwmod_class,
1220 .clkdm_name = "l4cfg_clkdm",
1221 .prcm = {
1222 .omap4 = {
1223 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1224 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1225 },
1226 },
1227 };
1229 /* mailbox4 */
1230 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1231 .name = "mailbox4",
1232 .class = &dra7xx_mailbox_hwmod_class,
1233 .clkdm_name = "l4cfg_clkdm",
1234 .prcm = {
1235 .omap4 = {
1236 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1237 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1238 },
1239 },
1240 };
1242 /* mailbox5 */
1243 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1244 .name = "mailbox5",
1245 .class = &dra7xx_mailbox_hwmod_class,
1246 .clkdm_name = "l4cfg_clkdm",
1247 .prcm = {
1248 .omap4 = {
1249 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1250 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1251 },
1252 },
1253 };
1255 /* mailbox6 */
1256 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1257 .name = "mailbox6",
1258 .class = &dra7xx_mailbox_hwmod_class,
1259 .clkdm_name = "l4cfg_clkdm",
1260 .prcm = {
1261 .omap4 = {
1262 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1263 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1264 },
1265 },
1266 };
1268 /* mailbox7 */
1269 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1270 .name = "mailbox7",
1271 .class = &dra7xx_mailbox_hwmod_class,
1272 .clkdm_name = "l4cfg_clkdm",
1273 .prcm = {
1274 .omap4 = {
1275 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1276 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1277 },
1278 },
1279 };
1281 /* mailbox8 */
1282 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1283 .name = "mailbox8",
1284 .class = &dra7xx_mailbox_hwmod_class,
1285 .clkdm_name = "l4cfg_clkdm",
1286 .prcm = {
1287 .omap4 = {
1288 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1289 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1290 },
1291 },
1292 };
1294 /* mailbox9 */
1295 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1296 .name = "mailbox9",
1297 .class = &dra7xx_mailbox_hwmod_class,
1298 .clkdm_name = "l4cfg_clkdm",
1299 .prcm = {
1300 .omap4 = {
1301 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1302 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1303 },
1304 },
1305 };
1307 /* mailbox10 */
1308 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1309 .name = "mailbox10",
1310 .class = &dra7xx_mailbox_hwmod_class,
1311 .clkdm_name = "l4cfg_clkdm",
1312 .prcm = {
1313 .omap4 = {
1314 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1315 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1316 },
1317 },
1318 };
1320 /* mailbox11 */
1321 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1322 .name = "mailbox11",
1323 .class = &dra7xx_mailbox_hwmod_class,
1324 .clkdm_name = "l4cfg_clkdm",
1325 .prcm = {
1326 .omap4 = {
1327 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1328 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1329 },
1330 },
1331 };
1333 /* mailbox12 */
1334 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1335 .name = "mailbox12",
1336 .class = &dra7xx_mailbox_hwmod_class,
1337 .clkdm_name = "l4cfg_clkdm",
1338 .prcm = {
1339 .omap4 = {
1340 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1341 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1342 },
1343 },
1344 };
1346 /* mailbox13 */
1347 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1348 .name = "mailbox13",
1349 .class = &dra7xx_mailbox_hwmod_class,
1350 .clkdm_name = "l4cfg_clkdm",
1351 .prcm = {
1352 .omap4 = {
1353 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1354 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1355 },
1356 },
1357 };
1359 /*
1360 * 'mcspi' class
1361 *
1362 */
1364 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010,
1367 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1368 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1369 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1370 SIDLE_SMART_WKUP),
1371 .sysc_fields = &omap_hwmod_sysc_type2,
1372 };
1374 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1375 .name = "mcspi",
1376 .sysc = &dra7xx_mcspi_sysc,
1377 };
1379 /* mcspi1 */
1380 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1381 .name = "mcspi1",
1382 .class = &dra7xx_mcspi_hwmod_class,
1383 .clkdm_name = "l4per_clkdm",
1384 .main_clk = "func_48m_fclk",
1385 .prcm = {
1386 .omap4 = {
1387 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1388 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1389 .modulemode = MODULEMODE_SWCTRL,
1390 },
1391 },
1392 };
1394 /* mcspi2 */
1395 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1396 .name = "mcspi2",
1397 .class = &dra7xx_mcspi_hwmod_class,
1398 .clkdm_name = "l4per_clkdm",
1399 .main_clk = "func_48m_fclk",
1400 .prcm = {
1401 .omap4 = {
1402 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1403 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1404 .modulemode = MODULEMODE_SWCTRL,
1405 },
1406 },
1407 };
1409 /* mcspi3 */
1410 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1411 .name = "mcspi3",
1412 .class = &dra7xx_mcspi_hwmod_class,
1413 .clkdm_name = "l4per_clkdm",
1414 .main_clk = "func_48m_fclk",
1415 .prcm = {
1416 .omap4 = {
1417 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1418 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1419 .modulemode = MODULEMODE_SWCTRL,
1420 },
1421 },
1422 };
1424 /* mcspi4 */
1425 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1426 .name = "mcspi4",
1427 .class = &dra7xx_mcspi_hwmod_class,
1428 .clkdm_name = "l4per_clkdm",
1429 .main_clk = "func_48m_fclk",
1430 .prcm = {
1431 .omap4 = {
1432 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1433 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1434 .modulemode = MODULEMODE_SWCTRL,
1435 },
1436 },
1437 };
1439 /*
1440 * 'mcasp' class
1441 *
1442 */
1443 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1444 .rev_offs = 0,
1445 .sysc_offs = 0x0004,
1446 .sysc_flags = SYSC_HAS_SIDLEMODE,
1447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1448 .sysc_fields = &omap_hwmod_sysc_type3,
1449 };
1451 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1452 .name = "mcasp",
1453 .sysc = &dra7xx_mcasp_sysc,
1454 };
1456 /* mcasp1 */
1457 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1458 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1459 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1460 };
1462 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1463 .name = "mcasp1",
1464 .class = &dra7xx_mcasp_hwmod_class,
1465 .clkdm_name = "ipu_clkdm",
1466 .main_clk = "mcasp1_aux_gfclk_mux",
1467 .flags = HWMOD_OPT_CLKS_NEEDED,
1468 .prcm = {
1469 .omap4 = {
1470 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1471 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1472 .modulemode = MODULEMODE_SWCTRL,
1473 },
1474 },
1475 .opt_clks = mcasp1_opt_clks,
1476 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1477 };
1479 /* mcasp2 */
1480 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1481 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1482 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1483 };
1485 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1486 .name = "mcasp2",
1487 .class = &dra7xx_mcasp_hwmod_class,
1488 .clkdm_name = "l4per2_clkdm",
1489 .main_clk = "mcasp2_aux_gfclk_mux",
1490 .flags = HWMOD_OPT_CLKS_NEEDED,
1491 .prcm = {
1492 .omap4 = {
1493 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1494 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1495 .modulemode = MODULEMODE_SWCTRL,
1496 },
1497 },
1498 .opt_clks = mcasp2_opt_clks,
1499 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1500 };
1502 /* mcasp3 */
1503 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1504 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1505 };
1507 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1508 .name = "mcasp3",
1509 .class = &dra7xx_mcasp_hwmod_class,
1510 .clkdm_name = "l4per2_clkdm",
1511 .main_clk = "mcasp3_aux_gfclk_mux",
1512 .flags = HWMOD_OPT_CLKS_NEEDED,
1513 .prcm = {
1514 .omap4 = {
1515 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1516 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL,
1518 },
1519 },
1520 .opt_clks = mcasp3_opt_clks,
1521 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1522 };
1524 /* mcasp4 */
1525 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1526 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1527 };
1529 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1530 .name = "mcasp4",
1531 .class = &dra7xx_mcasp_hwmod_class,
1532 .clkdm_name = "l4per2_clkdm",
1533 .main_clk = "mcasp4_aux_gfclk_mux",
1534 .flags = HWMOD_OPT_CLKS_NEEDED,
1535 .prcm = {
1536 .omap4 = {
1537 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1538 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1539 .modulemode = MODULEMODE_SWCTRL,
1540 },
1541 },
1542 .opt_clks = mcasp4_opt_clks,
1543 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1544 };
1546 /* mcasp5 */
1547 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1548 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1549 };
1551 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1552 .name = "mcasp5",
1553 .class = &dra7xx_mcasp_hwmod_class,
1554 .clkdm_name = "l4per2_clkdm",
1555 .main_clk = "mcasp5_aux_gfclk_mux",
1556 .flags = HWMOD_OPT_CLKS_NEEDED,
1557 .prcm = {
1558 .omap4 = {
1559 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1560 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1561 .modulemode = MODULEMODE_SWCTRL,
1562 },
1563 },
1564 .opt_clks = mcasp5_opt_clks,
1565 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1566 };
1568 /* mcasp6 */
1569 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1570 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1571 };
1573 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1574 .name = "mcasp6",
1575 .class = &dra7xx_mcasp_hwmod_class,
1576 .clkdm_name = "l4per2_clkdm",
1577 .main_clk = "mcasp6_aux_gfclk_mux",
1578 .flags = HWMOD_OPT_CLKS_NEEDED,
1579 .prcm = {
1580 .omap4 = {
1581 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1582 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1583 .modulemode = MODULEMODE_SWCTRL,
1584 },
1585 },
1586 .opt_clks = mcasp6_opt_clks,
1587 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1588 };
1590 /* mcasp7 */
1591 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1592 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1593 };
1595 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1596 .name = "mcasp7",
1597 .class = &dra7xx_mcasp_hwmod_class,
1598 .clkdm_name = "l4per2_clkdm",
1599 .main_clk = "mcasp7_aux_gfclk_mux",
1600 .flags = HWMOD_OPT_CLKS_NEEDED,
1601 .prcm = {
1602 .omap4 = {
1603 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1604 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1605 .modulemode = MODULEMODE_SWCTRL,
1606 },
1607 },
1608 .opt_clks = mcasp7_opt_clks,
1609 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1610 };
1612 /* mcasp8 */
1613 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1614 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1615 };
1617 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1618 .name = "mcasp8",
1619 .class = &dra7xx_mcasp_hwmod_class,
1620 .clkdm_name = "l4per2_clkdm",
1621 .main_clk = "mcasp8_aux_gfclk_mux",
1622 .flags = HWMOD_OPT_CLKS_NEEDED,
1623 .prcm = {
1624 .omap4 = {
1625 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1626 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1627 .modulemode = MODULEMODE_SWCTRL,
1628 },
1629 },
1630 .opt_clks = mcasp8_opt_clks,
1631 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1632 };
1634 /*
1635 * 'mmc' class
1636 *
1637 */
1639 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1640 .rev_offs = 0x0000,
1641 .sysc_offs = 0x0010,
1642 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1643 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1644 SYSC_HAS_SOFTRESET),
1645 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1646 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1647 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1648 .sysc_fields = &omap_hwmod_sysc_type2,
1649 };
1651 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1652 .name = "mmc",
1653 .sysc = &dra7xx_mmc_sysc,
1654 };
1656 /* mmc1 */
1657 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1658 { .role = "clk32k", .clk = "mmc1_clk32k" },
1659 };
1661 /* mmc1 dev_attr */
1662 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1663 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1664 };
1666 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1667 .name = "mmc1",
1668 .class = &dra7xx_mmc_hwmod_class,
1669 .clkdm_name = "l3init_clkdm",
1670 .main_clk = "mmc1_fclk_div",
1671 .prcm = {
1672 .omap4 = {
1673 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1674 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1675 .modulemode = MODULEMODE_SWCTRL,
1676 },
1677 },
1678 .opt_clks = mmc1_opt_clks,
1679 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1680 .dev_attr = &mmc1_dev_attr,
1681 };
1683 /* mmc2 */
1684 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1685 { .role = "clk32k", .clk = "mmc2_clk32k" },
1686 };
1688 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1689 .name = "mmc2",
1690 .class = &dra7xx_mmc_hwmod_class,
1691 .clkdm_name = "l3init_clkdm",
1692 .main_clk = "mmc2_fclk_div",
1693 .prcm = {
1694 .omap4 = {
1695 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1696 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1697 .modulemode = MODULEMODE_SWCTRL,
1698 },
1699 },
1700 .opt_clks = mmc2_opt_clks,
1701 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1702 };
1704 /* mmc3 */
1705 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1706 { .role = "clk32k", .clk = "mmc3_clk32k" },
1707 };
1709 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1710 .name = "mmc3",
1711 .class = &dra7xx_mmc_hwmod_class,
1712 .clkdm_name = "l4per_clkdm",
1713 .main_clk = "mmc3_gfclk_div",
1714 .prcm = {
1715 .omap4 = {
1716 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1717 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1718 .modulemode = MODULEMODE_SWCTRL,
1719 },
1720 },
1721 .opt_clks = mmc3_opt_clks,
1722 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1723 };
1725 /* mmc4 */
1726 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1727 { .role = "clk32k", .clk = "mmc4_clk32k" },
1728 };
1730 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1731 .name = "mmc4",
1732 .class = &dra7xx_mmc_hwmod_class,
1733 .clkdm_name = "l4per_clkdm",
1734 .main_clk = "mmc4_gfclk_div",
1735 .prcm = {
1736 .omap4 = {
1737 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1738 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1739 .modulemode = MODULEMODE_SWCTRL,
1740 },
1741 },
1742 .opt_clks = mmc4_opt_clks,
1743 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1744 };
1746 /*
1747 * 'mpu' class
1748 *
1749 */
1751 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1752 .name = "mpu",
1753 };
1755 /* mpu */
1756 static struct omap_hwmod dra7xx_mpu_hwmod = {
1757 .name = "mpu",
1758 .class = &dra7xx_mpu_hwmod_class,
1759 .clkdm_name = "mpu_clkdm",
1760 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1761 .main_clk = "dpll_mpu_m2_ck",
1762 .prcm = {
1763 .omap4 = {
1764 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1765 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1766 },
1767 },
1768 };
1770 /*
1771 * 'ocp2scp' class
1772 *
1773 */
1775 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1776 .rev_offs = 0x0000,
1777 .sysc_offs = 0x0010,
1778 .syss_offs = 0x0014,
1779 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1780 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1781 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1782 .sysc_fields = &omap_hwmod_sysc_type1,
1783 };
1785 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1786 .name = "ocp2scp",
1787 .sysc = &dra7xx_ocp2scp_sysc,
1788 };
1790 /* ocp2scp1 */
1791 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1792 .name = "ocp2scp1",
1793 .class = &dra7xx_ocp2scp_hwmod_class,
1794 .clkdm_name = "l3init_clkdm",
1795 .main_clk = "l4_root_clk_div",
1796 .prcm = {
1797 .omap4 = {
1798 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1799 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1800 .modulemode = MODULEMODE_HWCTRL,
1801 },
1802 },
1803 };
1805 /* ocp2scp3 */
1806 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1807 .name = "ocp2scp3",
1808 .class = &dra7xx_ocp2scp_hwmod_class,
1809 .clkdm_name = "l3init_clkdm",
1810 .main_clk = "l4_root_clk_div",
1811 .prcm = {
1812 .omap4 = {
1813 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1814 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1815 .modulemode = MODULEMODE_HWCTRL,
1816 },
1817 },
1818 };
1820 /*
1821 * 'PCIE' class
1822 *
1823 */
1825 /*
1826 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1827 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1828 * associated with an IP automatically leaving the driver to handle that
1829 * by itself. This does not work for PCIeSS which needs the reset lines
1830 * deasserted for the driver to start accessing registers.
1831 *
1832 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1833 * lines after asserting them.
1834 */
1835 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1836 {
1837 int i;
1839 for (i = 0; i < oh->rst_lines_cnt; i++) {
1840 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1841 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1842 }
1844 return 0;
1845 }
1847 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1848 .name = "pcie",
1849 .reset = dra7xx_pciess_reset,
1850 };
1852 /* pcie1 */
1853 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1854 { .name = "pcie", .rst_shift = 0 },
1855 };
1857 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1858 .name = "pcie1",
1859 .class = &dra7xx_pciess_hwmod_class,
1860 .clkdm_name = "pcie_clkdm",
1861 .rst_lines = dra7xx_pciess1_resets,
1862 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1863 .main_clk = "l4_root_clk_div",
1864 .prcm = {
1865 .omap4 = {
1866 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1867 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1868 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1869 .modulemode = MODULEMODE_SWCTRL,
1870 },
1871 },
1872 };
1874 /* pcie2 */
1875 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1876 { .name = "pcie", .rst_shift = 1 },
1877 };
1879 /* pcie2 */
1880 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1881 .name = "pcie2",
1882 .class = &dra7xx_pciess_hwmod_class,
1883 .clkdm_name = "pcie_clkdm",
1884 .rst_lines = dra7xx_pciess2_resets,
1885 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1886 .main_clk = "l4_root_clk_div",
1887 .prcm = {
1888 .omap4 = {
1889 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1890 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1891 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1892 .modulemode = MODULEMODE_SWCTRL,
1893 },
1894 },
1895 };
1897 /*
1898 * 'pru-icss' class
1899 * Programmable Real-Time Unit and Industrial Communication Subsystem
1900 */
1901 static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
1902 .name = "pruss",
1903 };
1905 /* pru-icss1 */
1906 static struct omap_hwmod dra7xx_pruss1_hwmod = {
1907 .name = "pruss1",
1908 .class = &dra7xx_pruss_hwmod_class,
1909 .clkdm_name = "l4per2_clkdm",
1910 .prcm = {
1911 .omap4 = {
1912 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
1913 .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
1914 .modulemode = MODULEMODE_SWCTRL,
1915 },
1916 },
1917 };
1919 /* pru-icss2 */
1920 static struct omap_hwmod dra7xx_pruss2_hwmod = {
1921 .name = "pruss2",
1922 .class = &dra7xx_pruss_hwmod_class,
1923 .clkdm_name = "l4per2_clkdm",
1924 .prcm = {
1925 .omap4 = {
1926 .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
1927 .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
1928 .modulemode = MODULEMODE_SWCTRL,
1929 },
1930 },
1931 };
1933 /*
1934 * 'qspi' class
1935 *
1936 */
1938 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1939 .rev_offs = 0,
1940 .sysc_offs = 0x0010,
1941 .sysc_flags = SYSC_HAS_SIDLEMODE,
1942 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1943 SIDLE_SMART_WKUP),
1944 .sysc_fields = &omap_hwmod_sysc_type2,
1945 };
1947 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1948 .name = "qspi",
1949 .sysc = &dra7xx_qspi_sysc,
1950 };
1952 /* qspi */
1953 static struct omap_hwmod dra7xx_qspi_hwmod = {
1954 .name = "qspi",
1955 .class = &dra7xx_qspi_hwmod_class,
1956 .clkdm_name = "l4per2_clkdm",
1957 .main_clk = "qspi_gfclk_div",
1958 .prcm = {
1959 .omap4 = {
1960 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1961 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1962 .modulemode = MODULEMODE_SWCTRL,
1963 },
1964 },
1965 };
1967 /*
1968 * 'rtcss' class
1969 *
1970 */
1971 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1972 .rev_offs = 0x0074,
1973 .sysc_offs = 0x0078,
1974 .sysc_flags = SYSC_HAS_SIDLEMODE,
1975 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1976 SIDLE_SMART_WKUP),
1977 .sysc_fields = &omap_hwmod_sysc_type3,
1978 };
1980 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1981 .name = "rtcss",
1982 .sysc = &dra7xx_rtcss_sysc,
1983 .unlock = &omap_hwmod_rtc_unlock,
1984 .lock = &omap_hwmod_rtc_lock,
1985 };
1987 /* rtcss */
1988 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1989 .name = "rtcss",
1990 .class = &dra7xx_rtcss_hwmod_class,
1991 .clkdm_name = "rtc_clkdm",
1992 .main_clk = "sys_32k_ck",
1993 .prcm = {
1994 .omap4 = {
1995 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1996 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1997 .modulemode = MODULEMODE_SWCTRL,
1998 },
1999 },
2000 };
2002 /*
2003 * 'sata' class
2004 *
2005 */
2007 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2008 .rev_offs = 0x00fc,
2009 .sysc_offs = 0x0000,
2010 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2011 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2012 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2013 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2014 .sysc_fields = &omap_hwmod_sysc_type2,
2015 };
2017 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2018 .name = "sata",
2019 .sysc = &dra7xx_sata_sysc,
2020 };
2022 /* sata */
2024 static struct omap_hwmod dra7xx_sata_hwmod = {
2025 .name = "sata",
2026 .class = &dra7xx_sata_hwmod_class,
2027 .clkdm_name = "l3init_clkdm",
2028 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2029 .main_clk = "func_48m_fclk",
2030 .mpu_rt_idx = 1,
2031 .prcm = {
2032 .omap4 = {
2033 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2034 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2035 .modulemode = MODULEMODE_SWCTRL,
2036 },
2037 },
2038 };
2040 /*
2041 * 'smartreflex' class
2042 *
2043 */
2045 /* The IP is not compliant to type1 / type2 scheme */
2046 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2047 .rev_offs = -ENODEV,
2048 .sysc_offs = 0x0038,
2049 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2050 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2051 SIDLE_SMART_WKUP),
2052 .sysc_fields = &omap36xx_sr_sysc_fields,
2053 };
2055 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2056 .name = "smartreflex",
2057 .sysc = &dra7xx_smartreflex_sysc,
2058 .rev = 2,
2059 };
2061 /* smartreflex_core */
2062 /* smartreflex_core dev_attr */
2063 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2064 .sensor_voltdm_name = "core",
2065 };
2067 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2068 .name = "smartreflex_core",
2069 .class = &dra7xx_smartreflex_hwmod_class,
2070 .clkdm_name = "coreaon_clkdm",
2071 .main_clk = "wkupaon_iclk_mux",
2072 .prcm = {
2073 .omap4 = {
2074 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2075 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2076 .modulemode = MODULEMODE_SWCTRL,
2077 },
2078 },
2079 .dev_attr = &smartreflex_core_dev_attr,
2080 };
2082 /* smartreflex_mpu */
2083 /* smartreflex_mpu dev_attr */
2084 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2085 .sensor_voltdm_name = "mpu",
2086 };
2088 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2089 .name = "smartreflex_mpu",
2090 .class = &dra7xx_smartreflex_hwmod_class,
2091 .clkdm_name = "coreaon_clkdm",
2092 .main_clk = "wkupaon_iclk_mux",
2093 .prcm = {
2094 .omap4 = {
2095 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2096 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2097 .modulemode = MODULEMODE_SWCTRL,
2098 },
2099 },
2100 .dev_attr = &smartreflex_mpu_dev_attr,
2101 };
2103 /*
2104 * 'spinlock' class
2105 *
2106 */
2108 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2109 .rev_offs = 0x0000,
2110 .sysc_offs = 0x0010,
2111 .syss_offs = 0x0014,
2112 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2113 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2114 SYSS_HAS_RESET_STATUS),
2115 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2116 .sysc_fields = &omap_hwmod_sysc_type1,
2117 };
2119 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2120 .name = "spinlock",
2121 .sysc = &dra7xx_spinlock_sysc,
2122 };
2124 /* spinlock */
2125 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2126 .name = "spinlock",
2127 .class = &dra7xx_spinlock_hwmod_class,
2128 .clkdm_name = "l4cfg_clkdm",
2129 .main_clk = "l3_iclk_div",
2130 .prcm = {
2131 .omap4 = {
2132 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2133 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2134 },
2135 },
2136 };
2138 /*
2139 * 'timer' class
2140 *
2141 * This class contains several variants: ['timer_1ms', 'timer_secure',
2142 * 'timer']
2143 */
2145 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2146 .rev_offs = 0x0000,
2147 .sysc_offs = 0x0010,
2148 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2149 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2150 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2151 SIDLE_SMART_WKUP),
2152 .sysc_fields = &omap_hwmod_sysc_type2,
2153 };
2155 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2156 .name = "timer",
2157 .sysc = &dra7xx_timer_1ms_sysc,
2158 };
2160 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2161 .rev_offs = 0x0000,
2162 .sysc_offs = 0x0010,
2163 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2164 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2166 SIDLE_SMART_WKUP),
2167 .sysc_fields = &omap_hwmod_sysc_type2,
2168 };
2170 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2171 .name = "timer",
2172 .sysc = &dra7xx_timer_sysc,
2173 };
2175 /* timer1 */
2176 static struct omap_hwmod dra7xx_timer1_hwmod = {
2177 .name = "timer1",
2178 .class = &dra7xx_timer_1ms_hwmod_class,
2179 .clkdm_name = "wkupaon_clkdm",
2180 .main_clk = "timer1_gfclk_mux",
2181 .prcm = {
2182 .omap4 = {
2183 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2184 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2185 .modulemode = MODULEMODE_SWCTRL,
2186 },
2187 },
2188 };
2190 /* timer2 */
2191 static struct omap_hwmod dra7xx_timer2_hwmod = {
2192 .name = "timer2",
2193 .class = &dra7xx_timer_1ms_hwmod_class,
2194 .clkdm_name = "l4per_clkdm",
2195 .main_clk = "timer2_gfclk_mux",
2196 .prcm = {
2197 .omap4 = {
2198 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2199 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2200 .modulemode = MODULEMODE_SWCTRL,
2201 },
2202 },
2203 };
2205 /* timer3 */
2206 static struct omap_hwmod dra7xx_timer3_hwmod = {
2207 .name = "timer3",
2208 .class = &dra7xx_timer_hwmod_class,
2209 .clkdm_name = "l4per_clkdm",
2210 .main_clk = "timer3_gfclk_mux",
2211 .prcm = {
2212 .omap4 = {
2213 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2214 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2215 .modulemode = MODULEMODE_SWCTRL,
2216 },
2217 },
2218 };
2220 /* timer4 */
2221 static struct omap_hwmod dra7xx_timer4_hwmod = {
2222 .name = "timer4",
2223 .class = &dra7xx_timer_hwmod_class,
2224 .clkdm_name = "l4per_clkdm",
2225 .main_clk = "timer4_gfclk_mux",
2226 .prcm = {
2227 .omap4 = {
2228 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2229 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2230 .modulemode = MODULEMODE_SWCTRL,
2231 },
2232 },
2233 };
2235 /* timer5 */
2236 static struct omap_hwmod dra7xx_timer5_hwmod = {
2237 .name = "timer5",
2238 .class = &dra7xx_timer_hwmod_class,
2239 .clkdm_name = "ipu_clkdm",
2240 .main_clk = "timer5_gfclk_mux",
2241 .prcm = {
2242 .omap4 = {
2243 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2244 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2245 .modulemode = MODULEMODE_SWCTRL,
2246 },
2247 },
2248 };
2250 /* timer6 */
2251 static struct omap_hwmod dra7xx_timer6_hwmod = {
2252 .name = "timer6",
2253 .class = &dra7xx_timer_hwmod_class,
2254 .clkdm_name = "ipu_clkdm",
2255 .main_clk = "timer6_gfclk_mux",
2256 .prcm = {
2257 .omap4 = {
2258 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2259 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2260 .modulemode = MODULEMODE_SWCTRL,
2261 },
2262 },
2263 };
2265 /* timer7 */
2266 static struct omap_hwmod dra7xx_timer7_hwmod = {
2267 .name = "timer7",
2268 .class = &dra7xx_timer_hwmod_class,
2269 .clkdm_name = "ipu_clkdm",
2270 .main_clk = "timer7_gfclk_mux",
2271 .prcm = {
2272 .omap4 = {
2273 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2274 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2275 .modulemode = MODULEMODE_SWCTRL,
2276 },
2277 },
2278 };
2280 /* timer8 */
2281 static struct omap_hwmod dra7xx_timer8_hwmod = {
2282 .name = "timer8",
2283 .class = &dra7xx_timer_hwmod_class,
2284 .clkdm_name = "ipu_clkdm",
2285 .main_clk = "timer8_gfclk_mux",
2286 .prcm = {
2287 .omap4 = {
2288 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2289 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2290 .modulemode = MODULEMODE_SWCTRL,
2291 },
2292 },
2293 };
2295 /* timer9 */
2296 static struct omap_hwmod dra7xx_timer9_hwmod = {
2297 .name = "timer9",
2298 .class = &dra7xx_timer_hwmod_class,
2299 .clkdm_name = "l4per_clkdm",
2300 .main_clk = "timer9_gfclk_mux",
2301 .prcm = {
2302 .omap4 = {
2303 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2304 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2305 .modulemode = MODULEMODE_SWCTRL,
2306 },
2307 },
2308 };
2310 /* timer10 */
2311 static struct omap_hwmod dra7xx_timer10_hwmod = {
2312 .name = "timer10",
2313 .class = &dra7xx_timer_1ms_hwmod_class,
2314 .clkdm_name = "l4per_clkdm",
2315 .main_clk = "timer10_gfclk_mux",
2316 .prcm = {
2317 .omap4 = {
2318 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2319 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2320 .modulemode = MODULEMODE_SWCTRL,
2321 },
2322 },
2323 };
2325 /* timer11 */
2326 static struct omap_hwmod dra7xx_timer11_hwmod = {
2327 .name = "timer11",
2328 .class = &dra7xx_timer_hwmod_class,
2329 .clkdm_name = "l4per_clkdm",
2330 .main_clk = "timer11_gfclk_mux",
2331 .prcm = {
2332 .omap4 = {
2333 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2334 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2335 .modulemode = MODULEMODE_SWCTRL,
2336 },
2337 },
2338 };
2340 /* timer12 */
2341 static struct omap_hwmod dra7xx_timer12_hwmod = {
2342 .name = "timer12",
2343 .class = &dra7xx_timer_hwmod_class,
2344 .clkdm_name = "wkupaon_clkdm",
2345 .main_clk = "secure_32k_clk_src_ck",
2346 .prcm = {
2347 .omap4 = {
2348 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2349 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2350 },
2351 },
2352 };
2354 /* timer13 */
2355 static struct omap_hwmod dra7xx_timer13_hwmod = {
2356 .name = "timer13",
2357 .class = &dra7xx_timer_hwmod_class,
2358 .clkdm_name = "l4per3_clkdm",
2359 .main_clk = "timer13_gfclk_mux",
2360 .prcm = {
2361 .omap4 = {
2362 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2363 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2364 .modulemode = MODULEMODE_SWCTRL,
2365 },
2366 },
2367 };
2369 /* timer14 */
2370 static struct omap_hwmod dra7xx_timer14_hwmod = {
2371 .name = "timer14",
2372 .class = &dra7xx_timer_hwmod_class,
2373 .clkdm_name = "l4per3_clkdm",
2374 .main_clk = "timer14_gfclk_mux",
2375 .prcm = {
2376 .omap4 = {
2377 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2378 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2379 .modulemode = MODULEMODE_SWCTRL,
2380 },
2381 },
2382 };
2384 /* timer15 */
2385 static struct omap_hwmod dra7xx_timer15_hwmod = {
2386 .name = "timer15",
2387 .class = &dra7xx_timer_hwmod_class,
2388 .clkdm_name = "l4per3_clkdm",
2389 .main_clk = "timer15_gfclk_mux",
2390 .prcm = {
2391 .omap4 = {
2392 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2393 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2394 .modulemode = MODULEMODE_SWCTRL,
2395 },
2396 },
2397 };
2399 /* timer16 */
2400 static struct omap_hwmod dra7xx_timer16_hwmod = {
2401 .name = "timer16",
2402 .class = &dra7xx_timer_hwmod_class,
2403 .clkdm_name = "l4per3_clkdm",
2404 .main_clk = "timer16_gfclk_mux",
2405 .prcm = {
2406 .omap4 = {
2407 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2408 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2409 .modulemode = MODULEMODE_SWCTRL,
2410 },
2411 },
2412 };
2414 /*
2415 * 'uart' class
2416 *
2417 */
2419 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2420 .rev_offs = 0x0050,
2421 .sysc_offs = 0x0054,
2422 .syss_offs = 0x0058,
2423 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2424 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2425 SYSS_HAS_RESET_STATUS),
2426 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2427 SIDLE_SMART_WKUP),
2428 .sysc_fields = &omap_hwmod_sysc_type1,
2429 };
2431 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2432 .name = "uart",
2433 .sysc = &dra7xx_uart_sysc,
2434 };
2436 /* uart1 */
2437 static struct omap_hwmod dra7xx_uart1_hwmod = {
2438 .name = "uart1",
2439 .class = &dra7xx_uart_hwmod_class,
2440 .clkdm_name = "l4per_clkdm",
2441 .main_clk = "uart1_gfclk_mux",
2442 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2443 .prcm = {
2444 .omap4 = {
2445 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2446 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2447 .modulemode = MODULEMODE_SWCTRL,
2448 },
2449 },
2450 };
2452 /* uart2 */
2453 static struct omap_hwmod dra7xx_uart2_hwmod = {
2454 .name = "uart2",
2455 .class = &dra7xx_uart_hwmod_class,
2456 .clkdm_name = "l4per_clkdm",
2457 .main_clk = "uart2_gfclk_mux",
2458 .flags = HWMOD_SWSUP_SIDLE_ACT,
2459 .prcm = {
2460 .omap4 = {
2461 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2462 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2463 .modulemode = MODULEMODE_SWCTRL,
2464 },
2465 },
2466 };
2468 /* uart3 */
2469 static struct omap_hwmod dra7xx_uart3_hwmod = {
2470 .name = "uart3",
2471 .class = &dra7xx_uart_hwmod_class,
2472 .clkdm_name = "l4per_clkdm",
2473 .main_clk = "uart3_gfclk_mux",
2474 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2475 .prcm = {
2476 .omap4 = {
2477 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2478 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2479 .modulemode = MODULEMODE_SWCTRL,
2480 },
2481 },
2482 };
2484 /* uart4 */
2485 static struct omap_hwmod dra7xx_uart4_hwmod = {
2486 .name = "uart4",
2487 .class = &dra7xx_uart_hwmod_class,
2488 .clkdm_name = "l4per_clkdm",
2489 .main_clk = "uart4_gfclk_mux",
2490 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2491 .prcm = {
2492 .omap4 = {
2493 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2494 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2495 .modulemode = MODULEMODE_SWCTRL,
2496 },
2497 },
2498 };
2500 /* uart5 */
2501 static struct omap_hwmod dra7xx_uart5_hwmod = {
2502 .name = "uart5",
2503 .class = &dra7xx_uart_hwmod_class,
2504 .clkdm_name = "l4per_clkdm",
2505 .main_clk = "uart5_gfclk_mux",
2506 .flags = HWMOD_SWSUP_SIDLE_ACT,
2507 .prcm = {
2508 .omap4 = {
2509 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2510 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2511 .modulemode = MODULEMODE_SWCTRL,
2512 },
2513 },
2514 };
2516 /* uart6 */
2517 static struct omap_hwmod dra7xx_uart6_hwmod = {
2518 .name = "uart6",
2519 .class = &dra7xx_uart_hwmod_class,
2520 .clkdm_name = "ipu_clkdm",
2521 .main_clk = "uart6_gfclk_mux",
2522 .flags = HWMOD_SWSUP_SIDLE_ACT,
2523 .prcm = {
2524 .omap4 = {
2525 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2526 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2527 .modulemode = MODULEMODE_SWCTRL,
2528 },
2529 },
2530 };
2532 /* uart7 */
2533 static struct omap_hwmod dra7xx_uart7_hwmod = {
2534 .name = "uart7",
2535 .class = &dra7xx_uart_hwmod_class,
2536 .clkdm_name = "l4per2_clkdm",
2537 .main_clk = "uart7_gfclk_mux",
2538 .flags = HWMOD_SWSUP_SIDLE_ACT,
2539 .prcm = {
2540 .omap4 = {
2541 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2542 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2543 .modulemode = MODULEMODE_SWCTRL,
2544 },
2545 },
2546 };
2548 /* uart8 */
2549 static struct omap_hwmod dra7xx_uart8_hwmod = {
2550 .name = "uart8",
2551 .class = &dra7xx_uart_hwmod_class,
2552 .clkdm_name = "l4per2_clkdm",
2553 .main_clk = "uart8_gfclk_mux",
2554 .flags = HWMOD_SWSUP_SIDLE_ACT,
2555 .prcm = {
2556 .omap4 = {
2557 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2558 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2559 .modulemode = MODULEMODE_SWCTRL,
2560 },
2561 },
2562 };
2564 /* uart9 */
2565 static struct omap_hwmod dra7xx_uart9_hwmod = {
2566 .name = "uart9",
2567 .class = &dra7xx_uart_hwmod_class,
2568 .clkdm_name = "l4per2_clkdm",
2569 .main_clk = "uart9_gfclk_mux",
2570 .flags = HWMOD_SWSUP_SIDLE_ACT,
2571 .prcm = {
2572 .omap4 = {
2573 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2574 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2575 .modulemode = MODULEMODE_SWCTRL,
2576 },
2577 },
2578 };
2580 /* uart10 */
2581 static struct omap_hwmod dra7xx_uart10_hwmod = {
2582 .name = "uart10",
2583 .class = &dra7xx_uart_hwmod_class,
2584 .clkdm_name = "wkupaon_clkdm",
2585 .main_clk = "uart10_gfclk_mux",
2586 .flags = HWMOD_SWSUP_SIDLE_ACT,
2587 .prcm = {
2588 .omap4 = {
2589 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2590 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2591 .modulemode = MODULEMODE_SWCTRL,
2592 },
2593 },
2594 };
2596 /* DES (the 'P' (public) device) */
2597 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2598 .rev_offs = 0x0030,
2599 .sysc_offs = 0x0034,
2600 .syss_offs = 0x0038,
2601 .sysc_flags = SYSS_HAS_RESET_STATUS,
2602 };
2604 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2605 .name = "des",
2606 .sysc = &dra7xx_des_sysc,
2607 };
2609 /* DES */
2610 static struct omap_hwmod dra7xx_des_hwmod = {
2611 .name = "des",
2612 .class = &dra7xx_des_hwmod_class,
2613 .clkdm_name = "l4sec_clkdm",
2614 .main_clk = "l3_iclk_div",
2615 .prcm = {
2616 .omap4 = {
2617 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2618 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2619 .modulemode = MODULEMODE_HWCTRL,
2620 },
2621 },
2622 };
2624 /* rng */
2625 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2626 .rev_offs = 0x1fe0,
2627 .sysc_offs = 0x1fe4,
2628 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2629 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2630 .sysc_fields = &omap_hwmod_sysc_type1,
2631 };
2633 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2634 .name = "rng",
2635 .sysc = &dra7xx_rng_sysc,
2636 };
2638 static struct omap_hwmod dra7xx_rng_hwmod = {
2639 .name = "rng",
2640 .class = &dra7xx_rng_hwmod_class,
2641 .flags = HWMOD_SWSUP_SIDLE,
2642 .clkdm_name = "l4sec_clkdm",
2643 .prcm = {
2644 .omap4 = {
2645 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2646 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2647 .modulemode = MODULEMODE_HWCTRL,
2648 },
2649 },
2650 };
2652 /*
2653 * 'usb_otg_ss' class
2654 *
2655 */
2657 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2658 .rev_offs = 0x0000,
2659 .sysc_offs = 0x0010,
2660 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2661 SYSC_HAS_SIDLEMODE),
2662 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2663 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2664 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2665 .sysc_fields = &omap_hwmod_sysc_type2,
2666 };
2668 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2669 .name = "usb_otg_ss",
2670 .sysc = &dra7xx_usb_otg_ss_sysc,
2671 };
2673 /* usb_otg_ss1 */
2674 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2675 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2676 };
2678 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2679 .name = "usb_otg_ss1",
2680 .class = &dra7xx_usb_otg_ss_hwmod_class,
2681 .clkdm_name = "l3init_clkdm",
2682 .main_clk = "dpll_core_h13x2_ck",
2683 .flags = HWMOD_CLKDM_NOAUTO,
2684 .prcm = {
2685 .omap4 = {
2686 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2687 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2688 .modulemode = MODULEMODE_HWCTRL,
2689 },
2690 },
2691 .opt_clks = usb_otg_ss1_opt_clks,
2692 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2693 };
2695 /* usb_otg_ss2 */
2696 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2697 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2698 };
2700 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2701 .name = "usb_otg_ss2",
2702 .class = &dra7xx_usb_otg_ss_hwmod_class,
2703 .clkdm_name = "l3init_clkdm",
2704 .main_clk = "dpll_core_h13x2_ck",
2705 .flags = HWMOD_CLKDM_NOAUTO,
2706 .prcm = {
2707 .omap4 = {
2708 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2709 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2710 .modulemode = MODULEMODE_HWCTRL,
2711 },
2712 },
2713 .opt_clks = usb_otg_ss2_opt_clks,
2714 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2715 };
2717 /* usb_otg_ss3 */
2718 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2719 .name = "usb_otg_ss3",
2720 .class = &dra7xx_usb_otg_ss_hwmod_class,
2721 .clkdm_name = "l3init_clkdm",
2722 .main_clk = "dpll_core_h13x2_ck",
2723 .prcm = {
2724 .omap4 = {
2725 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2726 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2727 .modulemode = MODULEMODE_HWCTRL,
2728 },
2729 },
2730 };
2732 /* usb_otg_ss4 */
2733 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2734 .name = "usb_otg_ss4",
2735 .class = &dra7xx_usb_otg_ss_hwmod_class,
2736 .clkdm_name = "l3init_clkdm",
2737 .main_clk = "dpll_core_h13x2_ck",
2738 .prcm = {
2739 .omap4 = {
2740 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2741 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2742 .modulemode = MODULEMODE_HWCTRL,
2743 },
2744 },
2745 };
2747 /*
2748 * 'vcp' class
2749 *
2750 */
2752 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2753 .name = "vcp",
2754 };
2756 /* vcp1 */
2757 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2758 .name = "vcp1",
2759 .class = &dra7xx_vcp_hwmod_class,
2760 .clkdm_name = "l3main1_clkdm",
2761 .main_clk = "l3_iclk_div",
2762 .prcm = {
2763 .omap4 = {
2764 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2765 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2766 },
2767 },
2768 };
2770 /* vcp2 */
2771 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2772 .name = "vcp2",
2773 .class = &dra7xx_vcp_hwmod_class,
2774 .clkdm_name = "l3main1_clkdm",
2775 .main_clk = "l3_iclk_div",
2776 .prcm = {
2777 .omap4 = {
2778 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2779 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2780 },
2781 },
2782 };
2784 /*
2785 * 'wd_timer' class
2786 *
2787 */
2789 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2790 .rev_offs = 0x0000,
2791 .sysc_offs = 0x0010,
2792 .syss_offs = 0x0014,
2793 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2794 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2795 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2796 SIDLE_SMART_WKUP),
2797 .sysc_fields = &omap_hwmod_sysc_type1,
2798 };
2800 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2801 .name = "wd_timer",
2802 .sysc = &dra7xx_wd_timer_sysc,
2803 .pre_shutdown = &omap2_wd_timer_disable,
2804 .reset = &omap2_wd_timer_reset,
2805 };
2807 /* wd_timer2 */
2808 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2809 .name = "wd_timer2",
2810 .class = &dra7xx_wd_timer_hwmod_class,
2811 .clkdm_name = "wkupaon_clkdm",
2812 .main_clk = "sys_32k_ck",
2813 .prcm = {
2814 .omap4 = {
2815 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2816 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2817 .modulemode = MODULEMODE_SWCTRL,
2818 },
2819 },
2820 };
2823 /*
2824 * Interfaces
2825 */
2827 /* l3_main_1 -> dmm */
2828 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2829 .master = &dra7xx_l3_main_1_hwmod,
2830 .slave = &dra7xx_dmm_hwmod,
2831 .clk = "l3_iclk_div",
2832 .user = OCP_USER_SDMA,
2833 };
2835 /* l3_main_2 -> l3_instr */
2836 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2837 .master = &dra7xx_l3_main_2_hwmod,
2838 .slave = &dra7xx_l3_instr_hwmod,
2839 .clk = "l3_iclk_div",
2840 .user = OCP_USER_MPU | OCP_USER_SDMA,
2841 };
2843 /* l4_cfg -> l3_main_1 */
2844 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2845 .master = &dra7xx_l4_cfg_hwmod,
2846 .slave = &dra7xx_l3_main_1_hwmod,
2847 .clk = "l3_iclk_div",
2848 .user = OCP_USER_MPU | OCP_USER_SDMA,
2849 };
2851 /* mpu -> l3_main_1 */
2852 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2853 .master = &dra7xx_mpu_hwmod,
2854 .slave = &dra7xx_l3_main_1_hwmod,
2855 .clk = "l3_iclk_div",
2856 .user = OCP_USER_MPU,
2857 };
2859 /* l3_main_1 -> l3_main_2 */
2860 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2861 .master = &dra7xx_l3_main_1_hwmod,
2862 .slave = &dra7xx_l3_main_2_hwmod,
2863 .clk = "l3_iclk_div",
2864 .user = OCP_USER_MPU,
2865 };
2867 /* l4_cfg -> l3_main_2 */
2868 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2869 .master = &dra7xx_l4_cfg_hwmod,
2870 .slave = &dra7xx_l3_main_2_hwmod,
2871 .clk = "l3_iclk_div",
2872 .user = OCP_USER_MPU | OCP_USER_SDMA,
2873 };
2875 /* l3_main_1 -> l4_cfg */
2876 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2877 .master = &dra7xx_l3_main_1_hwmod,
2878 .slave = &dra7xx_l4_cfg_hwmod,
2879 .clk = "l3_iclk_div",
2880 .user = OCP_USER_MPU | OCP_USER_SDMA,
2881 };
2883 /* l3_main_1 -> l4_per1 */
2884 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2885 .master = &dra7xx_l3_main_1_hwmod,
2886 .slave = &dra7xx_l4_per1_hwmod,
2887 .clk = "l3_iclk_div",
2888 .user = OCP_USER_MPU | OCP_USER_SDMA,
2889 };
2891 /* l3_main_1 -> l4_per2 */
2892 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2893 .master = &dra7xx_l3_main_1_hwmod,
2894 .slave = &dra7xx_l4_per2_hwmod,
2895 .clk = "l3_iclk_div",
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897 };
2899 /* l3_main_1 -> l4_per3 */
2900 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2901 .master = &dra7xx_l3_main_1_hwmod,
2902 .slave = &dra7xx_l4_per3_hwmod,
2903 .clk = "l3_iclk_div",
2904 .user = OCP_USER_MPU | OCP_USER_SDMA,
2905 };
2907 /* l3_main_1 -> l4_wkup */
2908 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2909 .master = &dra7xx_l3_main_1_hwmod,
2910 .slave = &dra7xx_l4_wkup_hwmod,
2911 .clk = "wkupaon_iclk_mux",
2912 .user = OCP_USER_MPU | OCP_USER_SDMA,
2913 };
2915 /* l4_per2 -> atl */
2916 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2917 .master = &dra7xx_l4_per2_hwmod,
2918 .slave = &dra7xx_atl_hwmod,
2919 .clk = "l3_iclk_div",
2920 .user = OCP_USER_MPU | OCP_USER_SDMA,
2921 };
2923 /* l3_main_1 -> bb2d */
2924 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2925 .master = &dra7xx_l3_main_1_hwmod,
2926 .slave = &dra7xx_bb2d_hwmod,
2927 .clk = "l3_iclk_div",
2928 .user = OCP_USER_MPU | OCP_USER_SDMA,
2929 };
2931 /* l4_wkup -> counter_32k */
2932 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2933 .master = &dra7xx_l4_wkup_hwmod,
2934 .slave = &dra7xx_counter_32k_hwmod,
2935 .clk = "wkupaon_iclk_mux",
2936 .user = OCP_USER_MPU | OCP_USER_SDMA,
2937 };
2939 /* l4_wkup -> ctrl_module_wkup */
2940 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2941 .master = &dra7xx_l4_wkup_hwmod,
2942 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2943 .clk = "wkupaon_iclk_mux",
2944 .user = OCP_USER_MPU | OCP_USER_SDMA,
2945 };
2947 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2948 .master = &dra7xx_l4_per2_hwmod,
2949 .slave = &dra7xx_gmac_hwmod,
2950 .clk = "dpll_gmac_ck",
2951 .user = OCP_USER_MPU,
2952 };
2954 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2955 .master = &dra7xx_gmac_hwmod,
2956 .slave = &dra7xx_mdio_hwmod,
2957 .user = OCP_USER_MPU,
2958 };
2960 /* l4_wkup -> dcan1 */
2961 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2962 .master = &dra7xx_l4_wkup_hwmod,
2963 .slave = &dra7xx_dcan1_hwmod,
2964 .clk = "wkupaon_iclk_mux",
2965 .user = OCP_USER_MPU | OCP_USER_SDMA,
2966 };
2968 /* l4_per2 -> dcan2 */
2969 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2970 .master = &dra7xx_l4_per2_hwmod,
2971 .slave = &dra7xx_dcan2_hwmod,
2972 .clk = "l3_iclk_div",
2973 .user = OCP_USER_MPU | OCP_USER_SDMA,
2974 };
2976 /* l4_cfg -> dma_system */
2977 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2978 .master = &dra7xx_l4_cfg_hwmod,
2979 .slave = &dra7xx_dma_system_hwmod,
2980 .clk = "l3_iclk_div",
2981 .user = OCP_USER_MPU | OCP_USER_SDMA,
2982 };
2984 /* l3_main_1 -> tpcc */
2985 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2986 .master = &dra7xx_l3_main_1_hwmod,
2987 .slave = &dra7xx_tpcc_hwmod,
2988 .clk = "l3_iclk_div",
2989 .user = OCP_USER_MPU,
2990 };
2992 /* l3_main_1 -> tptc0 */
2993 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2994 .master = &dra7xx_l3_main_1_hwmod,
2995 .slave = &dra7xx_tptc0_hwmod,
2996 .clk = "l3_iclk_div",
2997 .user = OCP_USER_MPU,
2998 };
3000 /* l3_main_1 -> tptc1 */
3001 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3002 .master = &dra7xx_l3_main_1_hwmod,
3003 .slave = &dra7xx_tptc1_hwmod,
3004 .clk = "l3_iclk_div",
3005 .user = OCP_USER_MPU,
3006 };
3008 /* l3_main_1 -> dss */
3009 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3010 .master = &dra7xx_l3_main_1_hwmod,
3011 .slave = &dra7xx_dss_hwmod,
3012 .clk = "l3_iclk_div",
3013 .user = OCP_USER_MPU | OCP_USER_SDMA,
3014 };
3016 /* l3_main_1 -> dispc */
3017 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3018 .master = &dra7xx_l3_main_1_hwmod,
3019 .slave = &dra7xx_dss_dispc_hwmod,
3020 .clk = "l3_iclk_div",
3021 .user = OCP_USER_MPU | OCP_USER_SDMA,
3022 };
3024 /* l3_main_1 -> dispc */
3025 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3026 .master = &dra7xx_l3_main_1_hwmod,
3027 .slave = &dra7xx_dss_hdmi_hwmod,
3028 .clk = "l3_iclk_div",
3029 .user = OCP_USER_MPU | OCP_USER_SDMA,
3030 };
3032 /* l3_main_1 -> aes1 */
3033 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3034 .master = &dra7xx_l3_main_1_hwmod,
3035 .slave = &dra7xx_aes1_hwmod,
3036 .clk = "l3_iclk_div",
3037 .user = OCP_USER_MPU | OCP_USER_SDMA,
3038 };
3040 /* l3_main_1 -> aes2 */
3041 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3042 .master = &dra7xx_l3_main_1_hwmod,
3043 .slave = &dra7xx_aes2_hwmod,
3044 .clk = "l3_iclk_div",
3045 .user = OCP_USER_MPU | OCP_USER_SDMA,
3046 };
3048 /* l3_main_1 -> sha0 */
3049 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3050 .master = &dra7xx_l3_main_1_hwmod,
3051 .slave = &dra7xx_sha0_hwmod,
3052 .clk = "l3_iclk_div",
3053 .user = OCP_USER_MPU | OCP_USER_SDMA,
3054 };
3056 /* l4_per2 -> mcasp1 */
3057 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3058 .master = &dra7xx_l4_per2_hwmod,
3059 .slave = &dra7xx_mcasp1_hwmod,
3060 .clk = "l4_root_clk_div",
3061 .user = OCP_USER_MPU | OCP_USER_SDMA,
3062 };
3064 /* l3_main_1 -> mcasp1 */
3065 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3066 .master = &dra7xx_l3_main_1_hwmod,
3067 .slave = &dra7xx_mcasp1_hwmod,
3068 .clk = "l3_iclk_div",
3069 .user = OCP_USER_MPU | OCP_USER_SDMA,
3070 };
3072 /* l4_per2 -> mcasp2 */
3073 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3074 .master = &dra7xx_l4_per2_hwmod,
3075 .slave = &dra7xx_mcasp2_hwmod,
3076 .clk = "l4_root_clk_div",
3077 .user = OCP_USER_MPU | OCP_USER_SDMA,
3078 };
3080 /* l3_main_1 -> mcasp2 */
3081 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3082 .master = &dra7xx_l3_main_1_hwmod,
3083 .slave = &dra7xx_mcasp2_hwmod,
3084 .clk = "l3_iclk_div",
3085 .user = OCP_USER_MPU | OCP_USER_SDMA,
3086 };
3088 /* l4_per2 -> mcasp3 */
3089 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3090 .master = &dra7xx_l4_per2_hwmod,
3091 .slave = &dra7xx_mcasp3_hwmod,
3092 .clk = "l4_root_clk_div",
3093 .user = OCP_USER_MPU | OCP_USER_SDMA,
3094 };
3096 /* l3_main_1 -> mcasp3 */
3097 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3098 .master = &dra7xx_l3_main_1_hwmod,
3099 .slave = &dra7xx_mcasp3_hwmod,
3100 .clk = "l3_iclk_div",
3101 .user = OCP_USER_MPU | OCP_USER_SDMA,
3102 };
3104 /* l4_per2 -> mcasp4 */
3105 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3106 .master = &dra7xx_l4_per2_hwmod,
3107 .slave = &dra7xx_mcasp4_hwmod,
3108 .clk = "l4_root_clk_div",
3109 .user = OCP_USER_MPU | OCP_USER_SDMA,
3110 };
3112 /* l4_per2 -> mcasp5 */
3113 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3114 .master = &dra7xx_l4_per2_hwmod,
3115 .slave = &dra7xx_mcasp5_hwmod,
3116 .clk = "l4_root_clk_div",
3117 .user = OCP_USER_MPU | OCP_USER_SDMA,
3118 };
3120 /* l4_per2 -> mcasp6 */
3121 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3122 .master = &dra7xx_l4_per2_hwmod,
3123 .slave = &dra7xx_mcasp6_hwmod,
3124 .clk = "l4_root_clk_div",
3125 .user = OCP_USER_MPU | OCP_USER_SDMA,
3126 };
3128 /* l4_per2 -> mcasp7 */
3129 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3130 .master = &dra7xx_l4_per2_hwmod,
3131 .slave = &dra7xx_mcasp7_hwmod,
3132 .clk = "l4_root_clk_div",
3133 .user = OCP_USER_MPU | OCP_USER_SDMA,
3134 };
3136 /* l4_per2 -> mcasp8 */
3137 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3138 .master = &dra7xx_l4_per2_hwmod,
3139 .slave = &dra7xx_mcasp8_hwmod,
3140 .clk = "l4_root_clk_div",
3141 .user = OCP_USER_MPU | OCP_USER_SDMA,
3142 };
3144 /* l4_per1 -> elm */
3145 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3146 .master = &dra7xx_l4_per1_hwmod,
3147 .slave = &dra7xx_elm_hwmod,
3148 .clk = "l3_iclk_div",
3149 .user = OCP_USER_MPU | OCP_USER_SDMA,
3150 };
3152 /* l4_wkup -> gpio1 */
3153 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3154 .master = &dra7xx_l4_wkup_hwmod,
3155 .slave = &dra7xx_gpio1_hwmod,
3156 .clk = "wkupaon_iclk_mux",
3157 .user = OCP_USER_MPU | OCP_USER_SDMA,
3158 };
3160 /* l4_per1 -> gpio2 */
3161 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3162 .master = &dra7xx_l4_per1_hwmod,
3163 .slave = &dra7xx_gpio2_hwmod,
3164 .clk = "l3_iclk_div",
3165 .user = OCP_USER_MPU | OCP_USER_SDMA,
3166 };
3168 /* l4_per1 -> gpio3 */
3169 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3170 .master = &dra7xx_l4_per1_hwmod,
3171 .slave = &dra7xx_gpio3_hwmod,
3172 .clk = "l3_iclk_div",
3173 .user = OCP_USER_MPU | OCP_USER_SDMA,
3174 };
3176 /* l4_per1 -> gpio4 */
3177 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3178 .master = &dra7xx_l4_per1_hwmod,
3179 .slave = &dra7xx_gpio4_hwmod,
3180 .clk = "l3_iclk_div",
3181 .user = OCP_USER_MPU | OCP_USER_SDMA,
3182 };
3184 /* l4_per1 -> gpio5 */
3185 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3186 .master = &dra7xx_l4_per1_hwmod,
3187 .slave = &dra7xx_gpio5_hwmod,
3188 .clk = "l3_iclk_div",
3189 .user = OCP_USER_MPU | OCP_USER_SDMA,
3190 };
3192 /* l4_per1 -> gpio6 */
3193 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3194 .master = &dra7xx_l4_per1_hwmod,
3195 .slave = &dra7xx_gpio6_hwmod,
3196 .clk = "l3_iclk_div",
3197 .user = OCP_USER_MPU | OCP_USER_SDMA,
3198 };
3200 /* l4_per1 -> gpio7 */
3201 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3202 .master = &dra7xx_l4_per1_hwmod,
3203 .slave = &dra7xx_gpio7_hwmod,
3204 .clk = "l3_iclk_div",
3205 .user = OCP_USER_MPU | OCP_USER_SDMA,
3206 };
3208 /* l4_per1 -> gpio8 */
3209 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3210 .master = &dra7xx_l4_per1_hwmod,
3211 .slave = &dra7xx_gpio8_hwmod,
3212 .clk = "l3_iclk_div",
3213 .user = OCP_USER_MPU | OCP_USER_SDMA,
3214 };
3216 /* l3_main_1 -> gpmc */
3217 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3218 .master = &dra7xx_l3_main_1_hwmod,
3219 .slave = &dra7xx_gpmc_hwmod,
3220 .clk = "l3_iclk_div",
3221 .user = OCP_USER_MPU | OCP_USER_SDMA,
3222 };
3224 /* l4_per1 -> hdq1w */
3225 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3226 .master = &dra7xx_l4_per1_hwmod,
3227 .slave = &dra7xx_hdq1w_hwmod,
3228 .clk = "l3_iclk_div",
3229 .user = OCP_USER_MPU | OCP_USER_SDMA,
3230 };
3232 /* l4_per1 -> i2c1 */
3233 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3234 .master = &dra7xx_l4_per1_hwmod,
3235 .slave = &dra7xx_i2c1_hwmod,
3236 .clk = "l3_iclk_div",
3237 .user = OCP_USER_MPU | OCP_USER_SDMA,
3238 };
3240 /* l4_per1 -> i2c2 */
3241 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3242 .master = &dra7xx_l4_per1_hwmod,
3243 .slave = &dra7xx_i2c2_hwmod,
3244 .clk = "l3_iclk_div",
3245 .user = OCP_USER_MPU | OCP_USER_SDMA,
3246 };
3248 /* l4_per1 -> i2c3 */
3249 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3250 .master = &dra7xx_l4_per1_hwmod,
3251 .slave = &dra7xx_i2c3_hwmod,
3252 .clk = "l3_iclk_div",
3253 .user = OCP_USER_MPU | OCP_USER_SDMA,
3254 };
3256 /* l4_per1 -> i2c4 */
3257 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3258 .master = &dra7xx_l4_per1_hwmod,
3259 .slave = &dra7xx_i2c4_hwmod,
3260 .clk = "l3_iclk_div",
3261 .user = OCP_USER_MPU | OCP_USER_SDMA,
3262 };
3264 /* l4_per1 -> i2c5 */
3265 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3266 .master = &dra7xx_l4_per1_hwmod,
3267 .slave = &dra7xx_i2c5_hwmod,
3268 .clk = "l3_iclk_div",
3269 .user = OCP_USER_MPU | OCP_USER_SDMA,
3270 };
3272 /* l4_cfg -> mailbox1 */
3273 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3274 .master = &dra7xx_l4_cfg_hwmod,
3275 .slave = &dra7xx_mailbox1_hwmod,
3276 .clk = "l3_iclk_div",
3277 .user = OCP_USER_MPU | OCP_USER_SDMA,
3278 };
3280 /* l4_per3 -> mailbox2 */
3281 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3282 .master = &dra7xx_l4_per3_hwmod,
3283 .slave = &dra7xx_mailbox2_hwmod,
3284 .clk = "l3_iclk_div",
3285 .user = OCP_USER_MPU | OCP_USER_SDMA,
3286 };
3288 /* l4_per3 -> mailbox3 */
3289 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3290 .master = &dra7xx_l4_per3_hwmod,
3291 .slave = &dra7xx_mailbox3_hwmod,
3292 .clk = "l3_iclk_div",
3293 .user = OCP_USER_MPU | OCP_USER_SDMA,
3294 };
3296 /* l4_per3 -> mailbox4 */
3297 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3298 .master = &dra7xx_l4_per3_hwmod,
3299 .slave = &dra7xx_mailbox4_hwmod,
3300 .clk = "l3_iclk_div",
3301 .user = OCP_USER_MPU | OCP_USER_SDMA,
3302 };
3304 /* l4_per3 -> mailbox5 */
3305 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3306 .master = &dra7xx_l4_per3_hwmod,
3307 .slave = &dra7xx_mailbox5_hwmod,
3308 .clk = "l3_iclk_div",
3309 .user = OCP_USER_MPU | OCP_USER_SDMA,
3310 };
3312 /* l4_per3 -> mailbox6 */
3313 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3314 .master = &dra7xx_l4_per3_hwmod,
3315 .slave = &dra7xx_mailbox6_hwmod,
3316 .clk = "l3_iclk_div",
3317 .user = OCP_USER_MPU | OCP_USER_SDMA,
3318 };
3320 /* l4_per3 -> mailbox7 */
3321 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3322 .master = &dra7xx_l4_per3_hwmod,
3323 .slave = &dra7xx_mailbox7_hwmod,
3324 .clk = "l3_iclk_div",
3325 .user = OCP_USER_MPU | OCP_USER_SDMA,
3326 };
3328 /* l4_per3 -> mailbox8 */
3329 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3330 .master = &dra7xx_l4_per3_hwmod,
3331 .slave = &dra7xx_mailbox8_hwmod,
3332 .clk = "l3_iclk_div",
3333 .user = OCP_USER_MPU | OCP_USER_SDMA,
3334 };
3336 /* l4_per3 -> mailbox9 */
3337 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3338 .master = &dra7xx_l4_per3_hwmod,
3339 .slave = &dra7xx_mailbox9_hwmod,
3340 .clk = "l3_iclk_div",
3341 .user = OCP_USER_MPU | OCP_USER_SDMA,
3342 };
3344 /* l4_per3 -> mailbox10 */
3345 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3346 .master = &dra7xx_l4_per3_hwmod,
3347 .slave = &dra7xx_mailbox10_hwmod,
3348 .clk = "l3_iclk_div",
3349 .user = OCP_USER_MPU | OCP_USER_SDMA,
3350 };
3352 /* l4_per3 -> mailbox11 */
3353 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3354 .master = &dra7xx_l4_per3_hwmod,
3355 .slave = &dra7xx_mailbox11_hwmod,
3356 .clk = "l3_iclk_div",
3357 .user = OCP_USER_MPU | OCP_USER_SDMA,
3358 };
3360 /* l4_per3 -> mailbox12 */
3361 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3362 .master = &dra7xx_l4_per3_hwmod,
3363 .slave = &dra7xx_mailbox12_hwmod,
3364 .clk = "l3_iclk_div",
3365 .user = OCP_USER_MPU | OCP_USER_SDMA,
3366 };
3368 /* l4_per3 -> mailbox13 */
3369 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3370 .master = &dra7xx_l4_per3_hwmod,
3371 .slave = &dra7xx_mailbox13_hwmod,
3372 .clk = "l3_iclk_div",
3373 .user = OCP_USER_MPU | OCP_USER_SDMA,
3374 };
3376 /* l4_per1 -> mcspi1 */
3377 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3378 .master = &dra7xx_l4_per1_hwmod,
3379 .slave = &dra7xx_mcspi1_hwmod,
3380 .clk = "l3_iclk_div",
3381 .user = OCP_USER_MPU | OCP_USER_SDMA,
3382 };
3384 /* l4_per1 -> mcspi2 */
3385 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3386 .master = &dra7xx_l4_per1_hwmod,
3387 .slave = &dra7xx_mcspi2_hwmod,
3388 .clk = "l3_iclk_div",
3389 .user = OCP_USER_MPU | OCP_USER_SDMA,
3390 };
3392 /* l4_per1 -> mcspi3 */
3393 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3394 .master = &dra7xx_l4_per1_hwmod,
3395 .slave = &dra7xx_mcspi3_hwmod,
3396 .clk = "l3_iclk_div",
3397 .user = OCP_USER_MPU | OCP_USER_SDMA,
3398 };
3400 /* l4_per1 -> mcspi4 */
3401 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3402 .master = &dra7xx_l4_per1_hwmod,
3403 .slave = &dra7xx_mcspi4_hwmod,
3404 .clk = "l3_iclk_div",
3405 .user = OCP_USER_MPU | OCP_USER_SDMA,
3406 };
3408 /* l4_per1 -> mmc1 */
3409 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3410 .master = &dra7xx_l4_per1_hwmod,
3411 .slave = &dra7xx_mmc1_hwmod,
3412 .clk = "l3_iclk_div",
3413 .user = OCP_USER_MPU | OCP_USER_SDMA,
3414 };
3416 /* l4_per1 -> mmc2 */
3417 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3418 .master = &dra7xx_l4_per1_hwmod,
3419 .slave = &dra7xx_mmc2_hwmod,
3420 .clk = "l3_iclk_div",
3421 .user = OCP_USER_MPU | OCP_USER_SDMA,
3422 };
3424 /* l4_per1 -> mmc3 */
3425 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3426 .master = &dra7xx_l4_per1_hwmod,
3427 .slave = &dra7xx_mmc3_hwmod,
3428 .clk = "l3_iclk_div",
3429 .user = OCP_USER_MPU | OCP_USER_SDMA,
3430 };
3432 /* l4_per1 -> mmc4 */
3433 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3434 .master = &dra7xx_l4_per1_hwmod,
3435 .slave = &dra7xx_mmc4_hwmod,
3436 .clk = "l3_iclk_div",
3437 .user = OCP_USER_MPU | OCP_USER_SDMA,
3438 };
3440 /* l4_cfg -> mpu */
3441 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3442 .master = &dra7xx_l4_cfg_hwmod,
3443 .slave = &dra7xx_mpu_hwmod,
3444 .clk = "l3_iclk_div",
3445 .user = OCP_USER_MPU | OCP_USER_SDMA,
3446 };
3448 /* l4_cfg -> ocp2scp1 */
3449 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3450 .master = &dra7xx_l4_cfg_hwmod,
3451 .slave = &dra7xx_ocp2scp1_hwmod,
3452 .clk = "l4_root_clk_div",
3453 .user = OCP_USER_MPU | OCP_USER_SDMA,
3454 };
3456 /* l4_cfg -> ocp2scp3 */
3457 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3458 .master = &dra7xx_l4_cfg_hwmod,
3459 .slave = &dra7xx_ocp2scp3_hwmod,
3460 .clk = "l4_root_clk_div",
3461 .user = OCP_USER_MPU | OCP_USER_SDMA,
3462 };
3464 /* l3_main_1 -> pciess1 */
3465 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3466 .master = &dra7xx_l3_main_1_hwmod,
3467 .slave = &dra7xx_pciess1_hwmod,
3468 .clk = "l3_iclk_div",
3469 .user = OCP_USER_MPU | OCP_USER_SDMA,
3470 };
3472 /* l4_cfg -> pciess1 */
3473 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3474 .master = &dra7xx_l4_cfg_hwmod,
3475 .slave = &dra7xx_pciess1_hwmod,
3476 .clk = "l4_root_clk_div",
3477 .user = OCP_USER_MPU | OCP_USER_SDMA,
3478 };
3480 /* l3_main_1 -> pciess2 */
3481 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3482 .master = &dra7xx_l3_main_1_hwmod,
3483 .slave = &dra7xx_pciess2_hwmod,
3484 .clk = "l3_iclk_div",
3485 .user = OCP_USER_MPU | OCP_USER_SDMA,
3486 };
3488 /* l4_cfg -> pciess2 */
3489 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3490 .master = &dra7xx_l4_cfg_hwmod,
3491 .slave = &dra7xx_pciess2_hwmod,
3492 .clk = "l4_root_clk_div",
3493 .user = OCP_USER_MPU | OCP_USER_SDMA,
3494 };
3496 /* l4_cfg -> pruss1 */
3497 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = {
3498 .master = &dra7xx_l4_cfg_hwmod,
3499 .slave = &dra7xx_pruss1_hwmod,
3500 .clk = "dpll_gmac_h13x2_ck",
3501 .user = OCP_USER_MPU | OCP_USER_SDMA,
3502 };
3504 /* l4_cfg -> pruss2 */
3505 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = {
3506 .master = &dra7xx_l4_cfg_hwmod,
3507 .slave = &dra7xx_pruss2_hwmod,
3508 .clk = "dpll_gmac_h13x2_ck",
3509 .user = OCP_USER_MPU | OCP_USER_SDMA,
3510 };
3512 /* l3_main_1 -> qspi */
3513 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3514 .master = &dra7xx_l3_main_1_hwmod,
3515 .slave = &dra7xx_qspi_hwmod,
3516 .clk = "l3_iclk_div",
3517 .user = OCP_USER_MPU | OCP_USER_SDMA,
3518 };
3520 /* l4_per3 -> rtcss */
3521 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3522 .master = &dra7xx_l4_per3_hwmod,
3523 .slave = &dra7xx_rtcss_hwmod,
3524 .clk = "l4_root_clk_div",
3525 .user = OCP_USER_MPU | OCP_USER_SDMA,
3526 };
3528 /* l4_cfg -> sata */
3529 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3530 .master = &dra7xx_l4_cfg_hwmod,
3531 .slave = &dra7xx_sata_hwmod,
3532 .clk = "l3_iclk_div",
3533 .user = OCP_USER_MPU | OCP_USER_SDMA,
3534 };
3536 /* l4_cfg -> smartreflex_core */
3537 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3538 .master = &dra7xx_l4_cfg_hwmod,
3539 .slave = &dra7xx_smartreflex_core_hwmod,
3540 .clk = "l4_root_clk_div",
3541 .user = OCP_USER_MPU | OCP_USER_SDMA,
3542 };
3544 /* l4_cfg -> smartreflex_mpu */
3545 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3546 .master = &dra7xx_l4_cfg_hwmod,
3547 .slave = &dra7xx_smartreflex_mpu_hwmod,
3548 .clk = "l4_root_clk_div",
3549 .user = OCP_USER_MPU | OCP_USER_SDMA,
3550 };
3552 /* l4_cfg -> spinlock */
3553 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3554 .master = &dra7xx_l4_cfg_hwmod,
3555 .slave = &dra7xx_spinlock_hwmod,
3556 .clk = "l3_iclk_div",
3557 .user = OCP_USER_MPU | OCP_USER_SDMA,
3558 };
3560 /* l4_wkup -> timer1 */
3561 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3562 .master = &dra7xx_l4_wkup_hwmod,
3563 .slave = &dra7xx_timer1_hwmod,
3564 .clk = "wkupaon_iclk_mux",
3565 .user = OCP_USER_MPU | OCP_USER_SDMA,
3566 };
3568 /* l4_per1 -> timer2 */
3569 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3570 .master = &dra7xx_l4_per1_hwmod,
3571 .slave = &dra7xx_timer2_hwmod,
3572 .clk = "l3_iclk_div",
3573 .user = OCP_USER_MPU | OCP_USER_SDMA,
3574 };
3576 /* l4_per1 -> timer3 */
3577 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3578 .master = &dra7xx_l4_per1_hwmod,
3579 .slave = &dra7xx_timer3_hwmod,
3580 .clk = "l3_iclk_div",
3581 .user = OCP_USER_MPU | OCP_USER_SDMA,
3582 };
3584 /* l4_per1 -> timer4 */
3585 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3586 .master = &dra7xx_l4_per1_hwmod,
3587 .slave = &dra7xx_timer4_hwmod,
3588 .clk = "l3_iclk_div",
3589 .user = OCP_USER_MPU | OCP_USER_SDMA,
3590 };
3592 /* l4_per3 -> timer5 */
3593 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3594 .master = &dra7xx_l4_per3_hwmod,
3595 .slave = &dra7xx_timer5_hwmod,
3596 .clk = "l3_iclk_div",
3597 .user = OCP_USER_MPU | OCP_USER_SDMA,
3598 };
3600 /* l4_per3 -> timer6 */
3601 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3602 .master = &dra7xx_l4_per3_hwmod,
3603 .slave = &dra7xx_timer6_hwmod,
3604 .clk = "l3_iclk_div",
3605 .user = OCP_USER_MPU | OCP_USER_SDMA,
3606 };
3608 /* l4_per3 -> timer7 */
3609 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3610 .master = &dra7xx_l4_per3_hwmod,
3611 .slave = &dra7xx_timer7_hwmod,
3612 .clk = "l3_iclk_div",
3613 .user = OCP_USER_MPU | OCP_USER_SDMA,
3614 };
3616 /* l4_per3 -> timer8 */
3617 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3618 .master = &dra7xx_l4_per3_hwmod,
3619 .slave = &dra7xx_timer8_hwmod,
3620 .clk = "l3_iclk_div",
3621 .user = OCP_USER_MPU | OCP_USER_SDMA,
3622 };
3624 /* l4_per1 -> timer9 */
3625 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3626 .master = &dra7xx_l4_per1_hwmod,
3627 .slave = &dra7xx_timer9_hwmod,
3628 .clk = "l3_iclk_div",
3629 .user = OCP_USER_MPU | OCP_USER_SDMA,
3630 };
3632 /* l4_per1 -> timer10 */
3633 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3634 .master = &dra7xx_l4_per1_hwmod,
3635 .slave = &dra7xx_timer10_hwmod,
3636 .clk = "l3_iclk_div",
3637 .user = OCP_USER_MPU | OCP_USER_SDMA,
3638 };
3640 /* l4_per1 -> timer11 */
3641 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3642 .master = &dra7xx_l4_per1_hwmod,
3643 .slave = &dra7xx_timer11_hwmod,
3644 .clk = "l3_iclk_div",
3645 .user = OCP_USER_MPU | OCP_USER_SDMA,
3646 };
3648 /* l4_wkup -> timer12 */
3649 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3650 .master = &dra7xx_l4_wkup_hwmod,
3651 .slave = &dra7xx_timer12_hwmod,
3652 .clk = "wkupaon_iclk_mux",
3653 .user = OCP_USER_MPU | OCP_USER_SDMA,
3654 };
3656 /* l4_per3 -> timer13 */
3657 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3658 .master = &dra7xx_l4_per3_hwmod,
3659 .slave = &dra7xx_timer13_hwmod,
3660 .clk = "l3_iclk_div",
3661 .user = OCP_USER_MPU | OCP_USER_SDMA,
3662 };
3664 /* l4_per3 -> timer14 */
3665 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3666 .master = &dra7xx_l4_per3_hwmod,
3667 .slave = &dra7xx_timer14_hwmod,
3668 .clk = "l3_iclk_div",
3669 .user = OCP_USER_MPU | OCP_USER_SDMA,
3670 };
3672 /* l4_per3 -> timer15 */
3673 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3674 .master = &dra7xx_l4_per3_hwmod,
3675 .slave = &dra7xx_timer15_hwmod,
3676 .clk = "l3_iclk_div",
3677 .user = OCP_USER_MPU | OCP_USER_SDMA,
3678 };
3680 /* l4_per3 -> timer16 */
3681 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3682 .master = &dra7xx_l4_per3_hwmod,
3683 .slave = &dra7xx_timer16_hwmod,
3684 .clk = "l3_iclk_div",
3685 .user = OCP_USER_MPU | OCP_USER_SDMA,
3686 };
3688 /* l4_per1 -> uart1 */
3689 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3690 .master = &dra7xx_l4_per1_hwmod,
3691 .slave = &dra7xx_uart1_hwmod,
3692 .clk = "l3_iclk_div",
3693 .user = OCP_USER_MPU | OCP_USER_SDMA,
3694 };
3696 /* l4_per1 -> uart2 */
3697 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3698 .master = &dra7xx_l4_per1_hwmod,
3699 .slave = &dra7xx_uart2_hwmod,
3700 .clk = "l3_iclk_div",
3701 .user = OCP_USER_MPU | OCP_USER_SDMA,
3702 };
3704 /* l4_per1 -> uart3 */
3705 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3706 .master = &dra7xx_l4_per1_hwmod,
3707 .slave = &dra7xx_uart3_hwmod,
3708 .clk = "l3_iclk_div",
3709 .user = OCP_USER_MPU | OCP_USER_SDMA,
3710 };
3712 /* l4_per1 -> uart4 */
3713 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3714 .master = &dra7xx_l4_per1_hwmod,
3715 .slave = &dra7xx_uart4_hwmod,
3716 .clk = "l3_iclk_div",
3717 .user = OCP_USER_MPU | OCP_USER_SDMA,
3718 };
3720 /* l4_per1 -> uart5 */
3721 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3722 .master = &dra7xx_l4_per1_hwmod,
3723 .slave = &dra7xx_uart5_hwmod,
3724 .clk = "l3_iclk_div",
3725 .user = OCP_USER_MPU | OCP_USER_SDMA,
3726 };
3728 /* l4_per1 -> uart6 */
3729 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3730 .master = &dra7xx_l4_per1_hwmod,
3731 .slave = &dra7xx_uart6_hwmod,
3732 .clk = "l3_iclk_div",
3733 .user = OCP_USER_MPU | OCP_USER_SDMA,
3734 };
3736 /* l4_per2 -> uart7 */
3737 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3738 .master = &dra7xx_l4_per2_hwmod,
3739 .slave = &dra7xx_uart7_hwmod,
3740 .clk = "l3_iclk_div",
3741 .user = OCP_USER_MPU | OCP_USER_SDMA,
3742 };
3744 /* l4_per1 -> des */
3745 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3746 .master = &dra7xx_l4_per1_hwmod,
3747 .slave = &dra7xx_des_hwmod,
3748 .clk = "l3_iclk_div",
3749 .user = OCP_USER_MPU | OCP_USER_SDMA,
3750 };
3752 /* l4_per2 -> uart8 */
3753 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3754 .master = &dra7xx_l4_per2_hwmod,
3755 .slave = &dra7xx_uart8_hwmod,
3756 .clk = "l3_iclk_div",
3757 .user = OCP_USER_MPU | OCP_USER_SDMA,
3758 };
3760 /* l4_per2 -> uart9 */
3761 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3762 .master = &dra7xx_l4_per2_hwmod,
3763 .slave = &dra7xx_uart9_hwmod,
3764 .clk = "l3_iclk_div",
3765 .user = OCP_USER_MPU | OCP_USER_SDMA,
3766 };
3768 /* l4_wkup -> uart10 */
3769 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3770 .master = &dra7xx_l4_wkup_hwmod,
3771 .slave = &dra7xx_uart10_hwmod,
3772 .clk = "wkupaon_iclk_mux",
3773 .user = OCP_USER_MPU | OCP_USER_SDMA,
3774 };
3776 /* l4_per1 -> rng */
3777 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3778 .master = &dra7xx_l4_per1_hwmod,
3779 .slave = &dra7xx_rng_hwmod,
3780 .user = OCP_USER_MPU,
3781 };
3783 /* l4_per3 -> usb_otg_ss1 */
3784 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3785 .master = &dra7xx_l4_per3_hwmod,
3786 .slave = &dra7xx_usb_otg_ss1_hwmod,
3787 .clk = "dpll_core_h13x2_ck",
3788 .user = OCP_USER_MPU | OCP_USER_SDMA,
3789 };
3791 /* l4_per3 -> usb_otg_ss2 */
3792 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3793 .master = &dra7xx_l4_per3_hwmod,
3794 .slave = &dra7xx_usb_otg_ss2_hwmod,
3795 .clk = "dpll_core_h13x2_ck",
3796 .user = OCP_USER_MPU | OCP_USER_SDMA,
3797 };
3799 /* l4_per3 -> usb_otg_ss3 */
3800 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3801 .master = &dra7xx_l4_per3_hwmod,
3802 .slave = &dra7xx_usb_otg_ss3_hwmod,
3803 .clk = "dpll_core_h13x2_ck",
3804 .user = OCP_USER_MPU | OCP_USER_SDMA,
3805 };
3807 /* l4_per3 -> usb_otg_ss4 */
3808 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3809 .master = &dra7xx_l4_per3_hwmod,
3810 .slave = &dra7xx_usb_otg_ss4_hwmod,
3811 .clk = "dpll_core_h13x2_ck",
3812 .user = OCP_USER_MPU | OCP_USER_SDMA,
3813 };
3815 /* l3_main_1 -> vcp1 */
3816 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3817 .master = &dra7xx_l3_main_1_hwmod,
3818 .slave = &dra7xx_vcp1_hwmod,
3819 .clk = "l3_iclk_div",
3820 .user = OCP_USER_MPU | OCP_USER_SDMA,
3821 };
3823 /* l4_per2 -> vcp1 */
3824 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3825 .master = &dra7xx_l4_per2_hwmod,
3826 .slave = &dra7xx_vcp1_hwmod,
3827 .clk = "l3_iclk_div",
3828 .user = OCP_USER_MPU | OCP_USER_SDMA,
3829 };
3831 /* l3_main_1 -> vcp2 */
3832 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3833 .master = &dra7xx_l3_main_1_hwmod,
3834 .slave = &dra7xx_vcp2_hwmod,
3835 .clk = "l3_iclk_div",
3836 .user = OCP_USER_MPU | OCP_USER_SDMA,
3837 };
3839 /* l4_per2 -> vcp2 */
3840 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3841 .master = &dra7xx_l4_per2_hwmod,
3842 .slave = &dra7xx_vcp2_hwmod,
3843 .clk = "l3_iclk_div",
3844 .user = OCP_USER_MPU | OCP_USER_SDMA,
3845 };
3847 /* l4_wkup -> wd_timer2 */
3848 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3849 .master = &dra7xx_l4_wkup_hwmod,
3850 .slave = &dra7xx_wd_timer2_hwmod,
3851 .clk = "wkupaon_iclk_mux",
3852 .user = OCP_USER_MPU | OCP_USER_SDMA,
3853 };
3855 /* l4_per2 -> epwmss0 */
3856 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3857 .master = &dra7xx_l4_per2_hwmod,
3858 .slave = &dra7xx_epwmss0_hwmod,
3859 .clk = "l4_root_clk_div",
3860 .user = OCP_USER_MPU,
3861 };
3863 /* l4_per2 -> epwmss1 */
3864 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3865 .master = &dra7xx_l4_per2_hwmod,
3866 .slave = &dra7xx_epwmss1_hwmod,
3867 .clk = "l4_root_clk_div",
3868 .user = OCP_USER_MPU,
3869 };
3871 /* l4_per2 -> epwmss2 */
3872 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3873 .master = &dra7xx_l4_per2_hwmod,
3874 .slave = &dra7xx_epwmss2_hwmod,
3875 .clk = "l4_root_clk_div",
3876 .user = OCP_USER_MPU,
3877 };
3879 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3880 &dra7xx_l3_main_1__dmm,
3881 &dra7xx_l3_main_2__l3_instr,
3882 &dra7xx_l4_cfg__l3_main_1,
3883 &dra7xx_mpu__l3_main_1,
3884 &dra7xx_l3_main_1__l3_main_2,
3885 &dra7xx_l4_cfg__l3_main_2,
3886 &dra7xx_l3_main_1__l4_cfg,
3887 &dra7xx_l3_main_1__l4_per1,
3888 &dra7xx_l3_main_1__l4_per2,
3889 &dra7xx_l3_main_1__l4_per3,
3890 &dra7xx_l3_main_1__l4_wkup,
3891 &dra7xx_l4_per2__atl,
3892 &dra7xx_l3_main_1__bb2d,
3893 &dra7xx_l4_wkup__counter_32k,
3894 &dra7xx_l4_wkup__ctrl_module_wkup,
3895 &dra7xx_l4_wkup__dcan1,
3896 &dra7xx_l4_per2__dcan2,
3897 &dra7xx_l4_per2__cpgmac0,
3898 &dra7xx_l4_per2__mcasp1,
3899 &dra7xx_l3_main_1__mcasp1,
3900 &dra7xx_l4_per2__mcasp2,
3901 &dra7xx_l3_main_1__mcasp2,
3902 &dra7xx_l4_per2__mcasp3,
3903 &dra7xx_l3_main_1__mcasp3,
3904 &dra7xx_l4_per2__mcasp4,
3905 &dra7xx_l4_per2__mcasp5,
3906 &dra7xx_l4_per2__mcasp6,
3907 &dra7xx_l4_per2__mcasp7,
3908 &dra7xx_l4_per2__mcasp8,
3909 &dra7xx_gmac__mdio,
3910 &dra7xx_l4_cfg__dma_system,
3911 &dra7xx_l3_main_1__tpcc,
3912 &dra7xx_l3_main_1__tptc0,
3913 &dra7xx_l3_main_1__tptc1,
3914 &dra7xx_l3_main_1__dss,
3915 &dra7xx_l3_main_1__dispc,
3916 &dra7xx_l3_main_1__hdmi,
3917 &dra7xx_l3_main_1__aes1,
3918 &dra7xx_l3_main_1__aes2,
3919 &dra7xx_l3_main_1__sha0,
3920 &dra7xx_l4_per1__elm,
3921 &dra7xx_l4_wkup__gpio1,
3922 &dra7xx_l4_per1__gpio2,
3923 &dra7xx_l4_per1__gpio3,
3924 &dra7xx_l4_per1__gpio4,
3925 &dra7xx_l4_per1__gpio5,
3926 &dra7xx_l4_per1__gpio6,
3927 &dra7xx_l4_per1__gpio7,
3928 &dra7xx_l4_per1__gpio8,
3929 &dra7xx_l3_main_1__gpmc,
3930 &dra7xx_l4_per1__hdq1w,
3931 &dra7xx_l4_per1__i2c1,
3932 &dra7xx_l4_per1__i2c2,
3933 &dra7xx_l4_per1__i2c3,
3934 &dra7xx_l4_per1__i2c4,
3935 &dra7xx_l4_per1__i2c5,
3936 &dra7xx_l4_cfg__mailbox1,
3937 &dra7xx_l4_per3__mailbox2,
3938 &dra7xx_l4_per3__mailbox3,
3939 &dra7xx_l4_per3__mailbox4,
3940 &dra7xx_l4_per3__mailbox5,
3941 &dra7xx_l4_per3__mailbox6,
3942 &dra7xx_l4_per3__mailbox7,
3943 &dra7xx_l4_per3__mailbox8,
3944 &dra7xx_l4_per3__mailbox9,
3945 &dra7xx_l4_per3__mailbox10,
3946 &dra7xx_l4_per3__mailbox11,
3947 &dra7xx_l4_per3__mailbox12,
3948 &dra7xx_l4_per3__mailbox13,
3949 &dra7xx_l4_per1__mcspi1,
3950 &dra7xx_l4_per1__mcspi2,
3951 &dra7xx_l4_per1__mcspi3,
3952 &dra7xx_l4_per1__mcspi4,
3953 &dra7xx_l4_per1__mmc1,
3954 &dra7xx_l4_per1__mmc2,
3955 &dra7xx_l4_per1__mmc3,
3956 &dra7xx_l4_per1__mmc4,
3957 &dra7xx_l4_cfg__mpu,
3958 &dra7xx_l4_cfg__ocp2scp1,
3959 &dra7xx_l4_cfg__ocp2scp3,
3960 &dra7xx_l3_main_1__pciess1,
3961 &dra7xx_l4_cfg__pciess1,
3962 &dra7xx_l3_main_1__pciess2,
3963 &dra7xx_l4_cfg__pciess2,
3964 &dra7xx_l4_cfg__pruss1,
3965 &dra7xx_l4_cfg__pruss2,
3966 &dra7xx_l3_main_1__qspi,
3967 &dra7xx_l4_cfg__sata,
3968 &dra7xx_l4_cfg__smartreflex_core,
3969 &dra7xx_l4_cfg__smartreflex_mpu,
3970 &dra7xx_l4_cfg__spinlock,
3971 &dra7xx_l4_wkup__timer1,
3972 &dra7xx_l4_per1__timer2,
3973 &dra7xx_l4_per1__timer3,
3974 &dra7xx_l4_per1__timer4,
3975 &dra7xx_l4_per3__timer5,
3976 &dra7xx_l4_per3__timer6,
3977 &dra7xx_l4_per3__timer7,
3978 &dra7xx_l4_per3__timer8,
3979 &dra7xx_l4_per1__timer9,
3980 &dra7xx_l4_per1__timer10,
3981 &dra7xx_l4_per1__timer11,
3982 &dra7xx_l4_per3__timer13,
3983 &dra7xx_l4_per3__timer14,
3984 &dra7xx_l4_per3__timer15,
3985 &dra7xx_l4_per3__timer16,
3986 &dra7xx_l4_per1__uart1,
3987 &dra7xx_l4_per1__uart2,
3988 &dra7xx_l4_per1__uart3,
3989 &dra7xx_l4_per1__uart4,
3990 &dra7xx_l4_per1__uart5,
3991 &dra7xx_l4_per1__uart6,
3992 &dra7xx_l4_per2__uart7,
3993 &dra7xx_l4_per2__uart8,
3994 &dra7xx_l4_per2__uart9,
3995 &dra7xx_l4_wkup__uart10,
3996 &dra7xx_l4_per1__des,
3997 &dra7xx_l4_per3__usb_otg_ss1,
3998 &dra7xx_l4_per3__usb_otg_ss2,
3999 &dra7xx_l4_per3__usb_otg_ss3,
4000 &dra7xx_l3_main_1__vcp1,
4001 &dra7xx_l4_per2__vcp1,
4002 &dra7xx_l3_main_1__vcp2,
4003 &dra7xx_l4_per2__vcp2,
4004 &dra7xx_l4_wkup__wd_timer2,
4005 &dra7xx_l4_per2__epwmss0,
4006 &dra7xx_l4_per2__epwmss1,
4007 &dra7xx_l4_per2__epwmss2,
4008 NULL,
4009 };
4011 /* GP-only hwmod links */
4012 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4013 &dra7xx_l4_wkup__timer12,
4014 &dra7xx_l4_per1__rng,
4015 NULL,
4016 };
4018 /* SoC variant specific hwmod links */
4019 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
4020 &dra7xx_l4_per3__usb_otg_ss4,
4021 NULL,
4022 };
4024 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
4025 NULL,
4026 };
4028 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4029 &dra7xx_l4_per3__usb_otg_ss4,
4030 NULL,
4031 };
4033 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4034 NULL,
4035 };
4037 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
4038 &dra7xx_l4_per3__rtcss,
4039 NULL,
4040 };
4042 int __init dra7xx_hwmod_init(void)
4043 {
4044 int ret;
4046 omap_hwmod_init();
4047 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4049 if (!ret && soc_is_dra74x()) {
4050 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4051 if (!ret)
4052 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4053 } else if (!ret && soc_is_dra72x()) {
4054 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4055 if (!ret && !of_machine_is_compatible("ti,dra718"))
4056 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4057 } else if (!ret && soc_is_dra76x()) {
4058 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
4060 if (!ret && soc_is_dra76x_acd()) {
4061 ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
4062 } else if (!ret && soc_is_dra76x_abz()) {
4063 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4064 }
4065 }
4067 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4068 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4070 return ret;
4071 }