arch/x86/hyperv/hv_apic.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Hyper-V specific APIC code.
   5  *
   6  * Copyright (C) 2018, Microsoft, Inc.
   7  *
   8  * Author : K. Y. Srinivasan <kys@microsoft.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  17  * NON INFRINGEMENT.  See the GNU General Public License for more
  18  * details.
  19  *
  20  */
  21
  22 #include <linux/types.h>
  23 #include <linux/version.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/mm.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/hyperv.h>
  28 #include <linux/slab.h>
  29 #include <linux/cpuhotplug.h>
  30 #include <asm/hypervisor.h>
  31 #include <asm/mshyperv.h>
  32 #include <asm/apic.h>
  33
  34 #include <asm/trace/hyperv.h>
  35
  36 static struct apic orig_apic;
  37
  38 static u64 hv_apic_icr_read(void)
  39 {
  40         u64 reg_val;
  41
  42         rdmsrl(HV_X64_MSR_ICR, reg_val);
  43         return reg_val;
  44 }
  45
  46 static void hv_apic_icr_write(u32 low, u32 id)
  47 {
  48         u64 reg_val;
  49
  50         reg_val = SET_APIC_DEST_FIELD(id);
  51         reg_val = reg_val << 32;
  52         reg_val |= low;
  53
  54         wrmsrl(HV_X64_MSR_ICR, reg_val);
  55 }
  56
  57 static u32 hv_apic_read(u32 reg)
  58 {
  59         u32 reg_val, hi;
  60
  61         switch (reg) {
  62         case APIC_EOI:
  63                 rdmsr(HV_X64_MSR_EOI, reg_val, hi);
  64                 return reg_val;
  65         case APIC_TASKPRI:
  66                 rdmsr(HV_X64_MSR_TPR, reg_val, hi);
  67                 return reg_val;
  68
  69         default:
  70                 return native_apic_mem_read(reg);
  71         }
  72 }
  73
  74 static void hv_apic_write(u32 reg, u32 val)
  75 {
  76         switch (reg) {
  77         case APIC_EOI:
  78                 wrmsr(HV_X64_MSR_EOI, val, 0);
  79                 break;
  80         case APIC_TASKPRI:
  81                 wrmsr(HV_X64_MSR_TPR, val, 0);
  82                 break;
  83         default:
  84                 native_apic_mem_write(reg, val);
  85         }
  86 }
  87
  88 static void hv_apic_eoi_write(u32 reg, u32 val)
  89 {
  90         wrmsr(HV_X64_MSR_EOI, val, 0);
  91 }
  92
  93 /*
  94  * IPI implementation on Hyper-V.
  95  */
  96 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
  97 {
  98         struct hv_send_ipi_ex **arg;
  99         struct hv_send_ipi_ex *ipi_arg;
 100         unsigned long flags;
 101         int nr_bank = 0;
 102         int ret = 1;
 103
 104         if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
 105                 return false;
 106
 107         local_irq_save(flags);
 108         arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
 109
 110         ipi_arg = *arg;
 111         if (unlikely(!ipi_arg))
 112                 goto ipi_mask_ex_done;
 113
 114         ipi_arg->vector = vector;
 115         ipi_arg->reserved = 0;
 116         ipi_arg->vp_set.valid_bank_mask = 0;
 117
 118         if (!cpumask_equal(mask, cpu_present_mask)) {
 119                 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
 120                 nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
 121         }
 122         if (nr_bank < 0)
 123                 goto ipi_mask_ex_done;
 124         if (!nr_bank)
 125                 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
 126
 127         ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
 128                               ipi_arg, NULL);
 129
 130 ipi_mask_ex_done:
 131         local_irq_restore(flags);
 132         return ((ret == 0) ? true : false);
 133 }
 134
 135 static bool __send_ipi_mask(const struct cpumask *mask, int vector)
 136 {
 137         int cur_cpu, vcpu;
 138         struct hv_send_ipi ipi_arg;
 139         int ret = 1;
 140
 141         trace_hyperv_send_ipi_mask(mask, vector);
 142
 143         if (cpumask_empty(mask))
 144                 return true;
 145
 146         if (!hv_hypercall_pg)
 147                 return false;
 148
 149         if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
 150                 return false;
 151
 152         /*
 153          * From the supplied CPU set we need to figure out if we can get away
 154          * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
 155          * highest VP number in the set is < 64. As VP numbers are usually in
 156          * ascending order and match Linux CPU ids, here is an optimization:
 157          * we check the VP number for the highest bit in the supplied set first
 158          * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
 159          * a must. We will also check all VP numbers when walking the supplied
 160          * CPU set to remain correct in all cases.
 161          */
 162         if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
 163                 goto do_ex_hypercall;
 164
 165         ipi_arg.vector = vector;
 166         ipi_arg.cpu_mask = 0;
 167
 168         for_each_cpu(cur_cpu, mask) {
 169                 vcpu = hv_cpu_number_to_vp_number(cur_cpu);
 170                 if (vcpu == VP_INVAL)
 171                         return false;
 172
 173                 /*
 174                  * This particular version of the IPI hypercall can
 175                  * only target upto 64 CPUs.
 176                  */
 177                 if (vcpu >= 64)
 178                         goto do_ex_hypercall;
 179
 180                 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
 181         }
 182
 183         ret = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
 184                                      ipi_arg.cpu_mask);
 185         return ((ret == 0) ? true : false);
 186
 187 do_ex_hypercall:
 188         return __send_ipi_mask_ex(mask, vector);
 189 }
 190
 191 static bool __send_ipi_one(int cpu, int vector)
 192 {
 193         struct cpumask mask = CPU_MASK_NONE;
 194
 195         cpumask_set_cpu(cpu, &mask);
 196         return __send_ipi_mask(&mask, vector);
 197 }
 198
 199 static void hv_send_ipi(int cpu, int vector)
 200 {
 201         if (!__send_ipi_one(cpu, vector))
 202                 orig_apic.send_IPI(cpu, vector);
 203 }
 204
 205 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
 206 {
 207         if (!__send_ipi_mask(mask, vector))
 208                 orig_apic.send_IPI_mask(mask, vector);
 209 }
 210
 211 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
 212 {
 213         unsigned int this_cpu = smp_processor_id();
 214         struct cpumask new_mask;
 215         const struct cpumask *local_mask;
 216
 217         cpumask_copy(&new_mask, mask);
 218         cpumask_clear_cpu(this_cpu, &new_mask);
 219         local_mask = &new_mask;
 220         if (!__send_ipi_mask(local_mask, vector))
 221                 orig_apic.send_IPI_mask_allbutself(mask, vector);
 222 }
 223
 224 static void hv_send_ipi_allbutself(int vector)
 225 {
 226         hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
 227 }
 228
 229 static void hv_send_ipi_all(int vector)
 230 {
 231         if (!__send_ipi_mask(cpu_online_mask, vector))
 232                 orig_apic.send_IPI_all(vector);
 233 }
 234
 235 static void hv_send_ipi_self(int vector)
 236 {
 237         if (!__send_ipi_one(smp_processor_id(), vector))
 238                 orig_apic.send_IPI_self(vector);
 239 }
 240
 241 void __init hv_apic_init(void)
 242 {
 243         if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
 244                 pr_info("Hyper-V: Using IPI hypercalls\n");
 245                 /*
 246                  * Set the IPI entry points.
 247                  */
 248                 orig_apic = *apic;
 249
 250                 apic->send_IPI = hv_send_ipi;
 251                 apic->send_IPI_mask = hv_send_ipi_mask;
 252                 apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
 253                 apic->send_IPI_allbutself = hv_send_ipi_allbutself;
 254                 apic->send_IPI_all = hv_send_ipi_all;
 255                 apic->send_IPI_self = hv_send_ipi_self;
 256         }
 257
 258         if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
 259                 pr_info("Hyper-V: Using MSR based APIC access\n");
 260                 apic_set_eoi_write(hv_apic_eoi_write);
 261                 apic->read      = hv_apic_read;
 262                 apic->write     = hv_apic_write;
 263                 apic->icr_write = hv_apic_icr_write;
 264                 apic->icr_read  = hv_apic_icr_read;
 265         }
 266 }