d7adbc102649619bef817a522e35934d2612a111
1 /*
2 * linux/arch/arm/plat-omap/dmtimer.c
3 *
4 * OMAP Dual-Mode Timers
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * dmtimer adaptation to platform_driver.
11 *
12 * Copyright (C) 2005 Nokia Corporation
13 * OMAP2 support by Juha Yrjola
14 * API improvements and OMAP2 clock framework support by Timo Teras
15 *
16 * Copyright (C) 2009 Texas Instruments
17 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
38 #include <linux/clk.h>
39 #include <linux/clk-provider.h>
40 #include <linux/module.h>
41 #include <linux/io.h>
42 #include <linux/device.h>
43 #include <linux/err.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/of.h>
46 #include <linux/of_device.h>
47 #include <linux/platform_device.h>
48 #include <linux/platform_data/dmtimer-omap.h>
50 #include <clocksource/timer-ti-dm.h>
52 static u32 omap_reserved_systimers;
53 static LIST_HEAD(omap_timer_list);
54 static DEFINE_SPINLOCK(dm_timer_lock);
56 enum {
57 REQUEST_ANY = 0,
58 REQUEST_BY_ID,
59 REQUEST_BY_CAP,
60 REQUEST_BY_NODE,
61 };
63 /**
64 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
65 * @timer: timer pointer over which read operation to perform
66 * @reg: lowest byte holds the register offset
67 *
68 * The posted mode bit is encoded in reg. Note that in posted mode write
69 * pending bit must be checked. Otherwise a read of a non completed write
70 * will produce an error.
71 */
72 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
73 {
74 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
75 return __omap_dm_timer_read(timer, reg, timer->posted);
76 }
78 /**
79 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
80 * @timer: timer pointer over which write operation is to perform
81 * @reg: lowest byte holds the register offset
82 * @value: data to write into the register
83 *
84 * The posted mode bit is encoded in reg. Note that in posted mode the write
85 * pending bit must be checked. Otherwise a write on a register which has a
86 * pending write will be lost.
87 */
88 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
89 u32 value)
90 {
91 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
92 __omap_dm_timer_write(timer, reg, value, timer->posted);
93 }
95 static void omap_timer_restore_context(struct omap_dm_timer *timer)
96 {
97 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
98 timer->context.twer);
99 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
100 timer->context.tcrr);
101 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
102 timer->context.tldr);
103 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
104 timer->context.tmar);
105 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
106 timer->context.tsicr);
107 writel_relaxed(timer->context.tier, timer->irq_ena);
108 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
109 timer->context.tclr);
110 }
112 static int omap_dm_timer_reset(struct omap_dm_timer *timer)
113 {
114 u32 l, timeout = 100000;
116 if (timer->revision != 1)
117 return -EINVAL;
119 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
121 do {
122 l = __omap_dm_timer_read(timer,
123 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
124 } while (!l && timeout--);
126 if (!timeout) {
127 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
128 return -ETIMEDOUT;
129 }
131 /* Configure timer for smart-idle mode */
132 l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
133 l |= 0x2 << 0x3;
134 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
136 timer->posted = 0;
138 return 0;
139 }
141 static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
142 {
143 int ret;
144 const char *parent_name;
145 struct clk *parent;
146 struct dmtimer_platform_data *pdata;
148 if (unlikely(!timer) || IS_ERR(timer->fclk))
149 return -EINVAL;
151 switch (source) {
152 case OMAP_TIMER_SRC_SYS_CLK:
153 parent_name = "timer_sys_ck";
154 break;
155 case OMAP_TIMER_SRC_32_KHZ:
156 parent_name = "timer_32k_ck";
157 break;
158 case OMAP_TIMER_SRC_EXT_CLK:
159 parent_name = "timer_ext_ck";
160 break;
161 default:
162 return -EINVAL;
163 }
165 pdata = timer->pdev->dev.platform_data;
167 /*
168 * FIXME: Used for OMAP1 devices only because they do not currently
169 * use the clock framework to set the parent clock. To be removed
170 * once OMAP1 migrated to using clock framework for dmtimers
171 */
172 if (pdata && pdata->set_timer_src)
173 return pdata->set_timer_src(timer->pdev, source);
175 #if defined(CONFIG_COMMON_CLK)
176 /* Check if the clock has configurable parents */
177 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
178 return 0;
179 #endif
181 parent = clk_get(&timer->pdev->dev, parent_name);
182 if (IS_ERR(parent)) {
183 pr_err("%s: %s not found\n", __func__, parent_name);
184 return -EINVAL;
185 }
187 ret = clk_set_parent(timer->fclk, parent);
188 if (ret < 0)
189 pr_err("%s: failed to set %s as parent\n", __func__,
190 parent_name);
192 clk_put(parent);
194 return ret;
195 }
197 static void omap_dm_timer_enable(struct omap_dm_timer *timer)
198 {
199 int c;
201 pm_runtime_get_sync(&timer->pdev->dev);
203 if (!(timer->capability & OMAP_TIMER_ALWON)) {
204 if (timer->get_context_loss_count) {
205 c = timer->get_context_loss_count(&timer->pdev->dev);
206 if (c != timer->ctx_loss_count) {
207 omap_timer_restore_context(timer);
208 timer->ctx_loss_count = c;
209 }
210 } else {
211 omap_timer_restore_context(timer);
212 }
213 }
214 }
216 static void omap_dm_timer_disable(struct omap_dm_timer *timer)
217 {
218 pm_runtime_put_sync(&timer->pdev->dev);
219 }
221 static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
222 {
223 int rc;
225 /*
226 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
227 * do not call clk_get() for these devices.
228 */
229 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
230 timer->fclk = clk_get(&timer->pdev->dev, "fck");
231 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
232 dev_err(&timer->pdev->dev, ": No fclk handle.\n");
233 return -EINVAL;
234 }
235 }
237 omap_dm_timer_enable(timer);
239 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
240 rc = omap_dm_timer_reset(timer);
241 if (rc) {
242 omap_dm_timer_disable(timer);
243 return rc;
244 }
245 }
247 __omap_dm_timer_enable_posted(timer);
248 omap_dm_timer_disable(timer);
250 rc = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
252 return rc;
253 }
255 static inline u32 omap_dm_timer_reserved_systimer(int id)
256 {
257 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
258 }
260 int omap_dm_timer_reserve_systimer(int id)
261 {
262 if (omap_dm_timer_reserved_systimer(id))
263 return -ENODEV;
265 omap_reserved_systimers |= (1 << (id - 1));
267 return 0;
268 }
270 static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
271 {
272 struct omap_dm_timer *timer = NULL, *t;
273 struct device_node *np = NULL;
274 unsigned long flags;
275 u32 cap = 0;
276 int id = 0;
278 switch (req_type) {
279 case REQUEST_BY_ID:
280 id = *(int *)data;
281 break;
282 case REQUEST_BY_CAP:
283 cap = *(u32 *)data;
284 break;
285 case REQUEST_BY_NODE:
286 np = (struct device_node *)data;
287 break;
288 default:
289 /* REQUEST_ANY */
290 break;
291 }
293 spin_lock_irqsave(&dm_timer_lock, flags);
294 list_for_each_entry(t, &omap_timer_list, node) {
295 if (t->reserved)
296 continue;
298 switch (req_type) {
299 case REQUEST_BY_ID:
300 if (id == t->pdev->id) {
301 timer = t;
302 timer->reserved = 1;
303 goto found;
304 }
305 break;
306 case REQUEST_BY_CAP:
307 if (cap == (t->capability & cap)) {
308 /*
309 * If timer is not NULL, we have already found
310 * one timer. But it was not an exact match
311 * because it had more capabilities than what
312 * was required. Therefore, unreserve the last
313 * timer found and see if this one is a better
314 * match.
315 */
316 if (timer)
317 timer->reserved = 0;
318 timer = t;
319 timer->reserved = 1;
321 /* Exit loop early if we find an exact match */
322 if (t->capability == cap)
323 goto found;
324 }
325 break;
326 case REQUEST_BY_NODE:
327 if (np == t->pdev->dev.of_node) {
328 timer = t;
329 timer->reserved = 1;
330 goto found;
331 }
332 break;
333 default:
334 /* REQUEST_ANY */
335 timer = t;
336 timer->reserved = 1;
337 goto found;
338 }
339 }
340 found:
341 spin_unlock_irqrestore(&dm_timer_lock, flags);
343 if (timer && omap_dm_timer_prepare(timer)) {
344 timer->reserved = 0;
345 timer = NULL;
346 }
348 if (!timer)
349 pr_debug("%s: timer request failed!\n", __func__);
351 return timer;
352 }
354 static struct omap_dm_timer *omap_dm_timer_request(void)
355 {
356 return _omap_dm_timer_request(REQUEST_ANY, NULL);
357 }
359 static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
360 {
361 /* Requesting timer by ID is not supported when device tree is used */
362 if (of_have_populated_dt()) {
363 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
364 __func__);
365 return NULL;
366 }
368 return _omap_dm_timer_request(REQUEST_BY_ID, &id);
369 }
371 /**
372 * omap_dm_timer_request_by_cap - Request a timer by capability
373 * @cap: Bit mask of capabilities to match
374 *
375 * Find a timer based upon capabilities bit mask. Callers of this function
376 * should use the definitions found in the plat/dmtimer.h file under the
377 * comment "timer capabilities used in hwmod database". Returns pointer to
378 * timer handle on success and a NULL pointer on failure.
379 */
380 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
381 {
382 return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
383 }
385 /**
386 * omap_dm_timer_request_by_node - Request a timer by device-tree node
387 * @np: Pointer to device-tree timer node
388 *
389 * Request a timer based upon a device node pointer. Returns pointer to
390 * timer handle on success and a NULL pointer on failure.
391 */
392 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
393 {
394 if (!np)
395 return NULL;
397 return _omap_dm_timer_request(REQUEST_BY_NODE, np);
398 }
400 static int omap_dm_timer_free(struct omap_dm_timer *timer)
401 {
402 if (unlikely(!timer))
403 return -EINVAL;
405 clk_put(timer->fclk);
407 WARN_ON(!timer->reserved);
408 timer->reserved = 0;
409 return 0;
410 }
412 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
413 {
414 if (timer)
415 return timer->irq;
416 return -EINVAL;
417 }
419 #if defined(CONFIG_ARCH_OMAP1)
420 #include <mach/hardware.h>
422 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
423 {
424 return NULL;
425 }
427 /**
428 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
429 * @inputmask: current value of idlect mask
430 */
431 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
432 {
433 int i = 0;
434 struct omap_dm_timer *timer = NULL;
435 unsigned long flags;
437 /* If ARMXOR cannot be idled this function call is unnecessary */
438 if (!(inputmask & (1 << 1)))
439 return inputmask;
441 /* If any active timer is using ARMXOR return modified mask */
442 spin_lock_irqsave(&dm_timer_lock, flags);
443 list_for_each_entry(timer, &omap_timer_list, node) {
444 u32 l;
446 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
447 if (l & OMAP_TIMER_CTRL_ST) {
448 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
449 inputmask &= ~(1 << 1);
450 else
451 inputmask &= ~(1 << 2);
452 }
453 i++;
454 }
455 spin_unlock_irqrestore(&dm_timer_lock, flags);
457 return inputmask;
458 }
460 #else
462 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
463 {
464 if (timer && !IS_ERR(timer->fclk))
465 return timer->fclk;
466 return NULL;
467 }
469 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
470 {
471 BUG();
473 return 0;
474 }
476 #endif
478 int omap_dm_timer_trigger(struct omap_dm_timer *timer)
479 {
480 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
481 pr_err("%s: timer not available or enabled.\n", __func__);
482 return -EINVAL;
483 }
485 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
486 return 0;
487 }
489 static int omap_dm_timer_start(struct omap_dm_timer *timer)
490 {
491 u32 l;
493 if (unlikely(!timer))
494 return -EINVAL;
496 omap_dm_timer_enable(timer);
498 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
499 if (!(l & OMAP_TIMER_CTRL_ST)) {
500 l |= OMAP_TIMER_CTRL_ST;
501 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
502 }
504 /* Save the context */
505 timer->context.tclr = l;
506 return 0;
507 }
509 static int omap_dm_timer_stop(struct omap_dm_timer *timer)
510 {
511 unsigned long rate = 0;
513 if (unlikely(!timer))
514 return -EINVAL;
516 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
517 rate = clk_get_rate(timer->fclk);
519 __omap_dm_timer_stop(timer, timer->posted, rate);
521 /*
522 * Since the register values are computed and written within
523 * __omap_dm_timer_stop, we need to use read to retrieve the
524 * context.
525 */
526 timer->context.tclr =
527 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
528 omap_dm_timer_disable(timer);
529 return 0;
530 }
532 static int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
533 unsigned int load)
534 {
535 u32 l;
537 if (unlikely(!timer))
538 return -EINVAL;
540 omap_dm_timer_enable(timer);
541 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
542 if (autoreload)
543 l |= OMAP_TIMER_CTRL_AR;
544 else
545 l &= ~OMAP_TIMER_CTRL_AR;
546 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
547 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
549 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
550 /* Save the context */
551 timer->context.tclr = l;
552 timer->context.tldr = load;
553 omap_dm_timer_disable(timer);
554 return 0;
555 }
557 /* Optimized set_load which removes costly spin wait in timer_start */
558 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
559 unsigned int load)
560 {
561 u32 l;
563 if (unlikely(!timer))
564 return -EINVAL;
566 omap_dm_timer_enable(timer);
568 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
569 if (autoreload) {
570 l |= OMAP_TIMER_CTRL_AR;
571 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
572 } else {
573 l &= ~OMAP_TIMER_CTRL_AR;
574 }
575 l |= OMAP_TIMER_CTRL_ST;
577 __omap_dm_timer_load_start(timer, l, load, timer->posted);
579 /* Save the context */
580 timer->context.tclr = l;
581 timer->context.tldr = load;
582 timer->context.tcrr = load;
583 return 0;
584 }
585 static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
586 unsigned int match)
587 {
588 u32 l;
590 if (unlikely(!timer))
591 return -EINVAL;
593 omap_dm_timer_enable(timer);
594 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
595 if (enable)
596 l |= OMAP_TIMER_CTRL_CE;
597 else
598 l &= ~OMAP_TIMER_CTRL_CE;
599 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
600 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
602 /* Save the context */
603 timer->context.tclr = l;
604 timer->context.tmar = match;
605 omap_dm_timer_disable(timer);
606 return 0;
607 }
609 static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
610 int toggle, int trigger)
611 {
612 u32 l;
614 if (unlikely(!timer))
615 return -EINVAL;
617 omap_dm_timer_enable(timer);
618 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
619 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
620 OMAP_TIMER_CTRL_PT | (0x03 << 10));
621 if (def_on)
622 l |= OMAP_TIMER_CTRL_SCPWM;
623 if (toggle)
624 l |= OMAP_TIMER_CTRL_PT;
625 l |= trigger << 10;
626 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
628 /* Save the context */
629 timer->context.tclr = l;
630 omap_dm_timer_disable(timer);
631 return 0;
632 }
634 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
635 int prescaler)
636 {
637 u32 l;
639 if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
640 return -EINVAL;
642 omap_dm_timer_enable(timer);
643 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
644 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
645 if (prescaler >= 0) {
646 l |= OMAP_TIMER_CTRL_PRE;
647 l |= prescaler << 2;
648 }
649 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
651 /* Save the context */
652 timer->context.tclr = l;
653 omap_dm_timer_disable(timer);
654 return 0;
655 }
657 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
658 unsigned int value)
659 {
660 if (unlikely(!timer))
661 return -EINVAL;
663 omap_dm_timer_enable(timer);
664 __omap_dm_timer_int_enable(timer, value);
666 /* Save the context */
667 timer->context.tier = value;
668 timer->context.twer = value;
669 omap_dm_timer_disable(timer);
670 return 0;
671 }
673 /**
674 * omap_dm_timer_set_int_disable - disable timer interrupts
675 * @timer: pointer to timer handle
676 * @mask: bit mask of interrupts to be disabled
677 *
678 * Disables the specified timer interrupts for a timer.
679 */
680 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
681 {
682 u32 l = mask;
684 if (unlikely(!timer))
685 return -EINVAL;
687 omap_dm_timer_enable(timer);
689 if (timer->revision == 1)
690 l = readl_relaxed(timer->irq_ena) & ~mask;
692 writel_relaxed(l, timer->irq_dis);
693 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
694 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
696 /* Save the context */
697 timer->context.tier &= ~mask;
698 timer->context.twer &= ~mask;
699 omap_dm_timer_disable(timer);
700 return 0;
701 }
703 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
704 {
705 unsigned int l;
707 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
708 pr_err("%s: timer not available or enabled.\n", __func__);
709 return 0;
710 }
712 l = readl_relaxed(timer->irq_stat);
714 return l;
715 }
717 static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
718 {
719 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
720 return -EINVAL;
722 __omap_dm_timer_write_status(timer, value);
724 return 0;
725 }
727 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
728 {
729 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
730 pr_err("%s: timer not iavailable or enabled.\n", __func__);
731 return 0;
732 }
734 return __omap_dm_timer_read_counter(timer, timer->posted);
735 }
737 static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
738 {
739 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
740 pr_err("%s: timer not available or enabled.\n", __func__);
741 return -EINVAL;
742 }
744 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
746 /* Save the context */
747 timer->context.tcrr = value;
748 return 0;
749 }
751 int omap_dm_timers_active(void)
752 {
753 struct omap_dm_timer *timer;
755 list_for_each_entry(timer, &omap_timer_list, node) {
756 if (!timer->reserved)
757 continue;
759 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
760 OMAP_TIMER_CTRL_ST) {
761 return 1;
762 }
763 }
764 return 0;
765 }
767 static const struct of_device_id omap_timer_match[];
769 /**
770 * omap_dm_timer_probe - probe function called for every registered device
771 * @pdev: pointer to current timer platform device
772 *
773 * Called by driver framework at the end of device registration for all
774 * timer devices.
775 */
776 static int omap_dm_timer_probe(struct platform_device *pdev)
777 {
778 unsigned long flags;
779 struct omap_dm_timer *timer;
780 struct resource *mem, *irq;
781 struct device *dev = &pdev->dev;
782 const struct dmtimer_platform_data *pdata;
783 int ret;
785 pdata = of_device_get_match_data(dev);
786 if (!pdata)
787 pdata = dev_get_platdata(dev);
788 else
789 dev->platform_data = (void *)pdata;
791 if (!pdata) {
792 dev_err(dev, "%s: no platform data.\n", __func__);
793 return -ENODEV;
794 }
796 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
797 if (unlikely(!irq)) {
798 dev_err(dev, "%s: no IRQ resource.\n", __func__);
799 return -ENODEV;
800 }
802 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
803 if (unlikely(!mem)) {
804 dev_err(dev, "%s: no memory resource.\n", __func__);
805 return -ENODEV;
806 }
808 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
809 if (!timer)
810 return -ENOMEM;
812 timer->fclk = ERR_PTR(-ENODEV);
813 timer->io_base = devm_ioremap_resource(dev, mem);
814 if (IS_ERR(timer->io_base))
815 return PTR_ERR(timer->io_base);
817 if (dev->of_node) {
818 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
819 timer->capability |= OMAP_TIMER_ALWON;
820 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
821 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
822 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
823 timer->capability |= OMAP_TIMER_HAS_PWM;
824 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
825 timer->capability |= OMAP_TIMER_SECURE;
826 } else {
827 timer->id = pdev->id;
828 timer->capability = pdata->timer_capability;
829 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
830 timer->get_context_loss_count = pdata->get_context_loss_count;
831 }
833 if (pdata)
834 timer->errata = pdata->timer_errata;
836 timer->irq = irq->start;
837 timer->pdev = pdev;
839 pm_runtime_enable(dev);
840 pm_runtime_irq_safe(dev);
842 if (!timer->reserved) {
843 ret = pm_runtime_get_sync(dev);
844 if (ret < 0) {
845 dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
846 __func__);
847 goto err_get_sync;
848 }
849 __omap_dm_timer_init_regs(timer);
850 pm_runtime_put(dev);
851 }
853 /* add the timer element to the list */
854 spin_lock_irqsave(&dm_timer_lock, flags);
855 list_add_tail(&timer->node, &omap_timer_list);
856 spin_unlock_irqrestore(&dm_timer_lock, flags);
858 dev_dbg(dev, "Device Probed.\n");
860 return 0;
862 err_get_sync:
863 pm_runtime_put_noidle(dev);
864 pm_runtime_disable(dev);
865 return ret;
866 }
868 /**
869 * omap_dm_timer_remove - cleanup a registered timer device
870 * @pdev: pointer to current timer platform device
871 *
872 * Called by driver framework whenever a timer device is unregistered.
873 * In addition to freeing platform resources it also deletes the timer
874 * entry from the local list.
875 */
876 static int omap_dm_timer_remove(struct platform_device *pdev)
877 {
878 struct omap_dm_timer *timer;
879 unsigned long flags;
880 int ret = -EINVAL;
882 spin_lock_irqsave(&dm_timer_lock, flags);
883 list_for_each_entry(timer, &omap_timer_list, node)
884 if (!strcmp(dev_name(&timer->pdev->dev),
885 dev_name(&pdev->dev))) {
886 list_del(&timer->node);
887 ret = 0;
888 break;
889 }
890 spin_unlock_irqrestore(&dm_timer_lock, flags);
892 pm_runtime_disable(&pdev->dev);
894 return ret;
895 }
897 const static struct omap_dm_timer_ops dmtimer_ops = {
898 .request_by_node = omap_dm_timer_request_by_node,
899 .request_specific = omap_dm_timer_request_specific,
900 .request = omap_dm_timer_request,
901 .set_source = omap_dm_timer_set_source,
902 .get_irq = omap_dm_timer_get_irq,
903 .set_int_enable = omap_dm_timer_set_int_enable,
904 .set_int_disable = omap_dm_timer_set_int_disable,
905 .free = omap_dm_timer_free,
906 .enable = omap_dm_timer_enable,
907 .disable = omap_dm_timer_disable,
908 .get_fclk = omap_dm_timer_get_fclk,
909 .start = omap_dm_timer_start,
910 .stop = omap_dm_timer_stop,
911 .set_load = omap_dm_timer_set_load,
912 .set_match = omap_dm_timer_set_match,
913 .set_pwm = omap_dm_timer_set_pwm,
914 .set_prescaler = omap_dm_timer_set_prescaler,
915 .read_counter = omap_dm_timer_read_counter,
916 .write_counter = omap_dm_timer_write_counter,
917 .read_status = omap_dm_timer_read_status,
918 .write_status = omap_dm_timer_write_status,
919 };
921 static const struct dmtimer_platform_data omap3plus_pdata = {
922 .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
923 .timer_ops = &dmtimer_ops,
924 };
926 static const struct of_device_id omap_timer_match[] = {
927 {
928 .compatible = "ti,omap2420-timer",
929 },
930 {
931 .compatible = "ti,omap3430-timer",
932 .data = &omap3plus_pdata,
933 },
934 {
935 .compatible = "ti,omap4430-timer",
936 .data = &omap3plus_pdata,
937 },
938 {
939 .compatible = "ti,omap5430-timer",
940 .data = &omap3plus_pdata,
941 },
942 {
943 .compatible = "ti,am335x-timer",
944 .data = &omap3plus_pdata,
945 },
946 {
947 .compatible = "ti,am335x-timer-1ms",
948 .data = &omap3plus_pdata,
949 },
950 {
951 .compatible = "ti,dm816-timer",
952 .data = &omap3plus_pdata,
953 },
954 {},
955 };
956 MODULE_DEVICE_TABLE(of, omap_timer_match);
958 static struct platform_driver omap_dm_timer_driver = {
959 .probe = omap_dm_timer_probe,
960 .remove = omap_dm_timer_remove,
961 .driver = {
962 .name = "omap_timer",
963 .of_match_table = of_match_ptr(omap_timer_match),
964 },
965 };
967 early_platform_init("earlytimer", &omap_dm_timer_driver);
968 module_platform_driver(omap_dm_timer_driver);
970 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
971 MODULE_LICENSE("GPL");
972 MODULE_ALIAS("platform:" DRIVER_NAME);
973 MODULE_AUTHOR("Texas Instruments Inc");