1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
91 static const uint32_t skl_pri_planar_formats[] = {
92 DRM_FORMAT_C8,
93 DRM_FORMAT_RGB565,
94 DRM_FORMAT_XRGB8888,
95 DRM_FORMAT_XBGR8888,
96 DRM_FORMAT_ARGB8888,
97 DRM_FORMAT_ABGR8888,
98 DRM_FORMAT_XRGB2101010,
99 DRM_FORMAT_XBGR2101010,
100 DRM_FORMAT_YUYV,
101 DRM_FORMAT_YVYU,
102 DRM_FORMAT_UYVY,
103 DRM_FORMAT_VYUY,
104 DRM_FORMAT_NV12,
105 };
107 static const uint64_t skl_format_modifiers_noccs[] = {
108 I915_FORMAT_MOD_Yf_TILED,
109 I915_FORMAT_MOD_Y_TILED,
110 I915_FORMAT_MOD_X_TILED,
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_INVALID
113 };
115 static const uint64_t skl_format_modifiers_ccs[] = {
116 I915_FORMAT_MOD_Yf_TILED_CCS,
117 I915_FORMAT_MOD_Y_TILED_CCS,
118 I915_FORMAT_MOD_Yf_TILED,
119 I915_FORMAT_MOD_Y_TILED,
120 I915_FORMAT_MOD_X_TILED,
121 DRM_FORMAT_MOD_LINEAR,
122 DRM_FORMAT_MOD_INVALID
123 };
125 /* Cursor formats */
126 static const uint32_t intel_cursor_formats[] = {
127 DRM_FORMAT_ARGB8888,
128 };
130 static const uint64_t cursor_format_modifiers[] = {
131 DRM_FORMAT_MOD_LINEAR,
132 DRM_FORMAT_MOD_INVALID
133 };
135 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
136 struct intel_crtc_state *pipe_config);
137 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
138 struct intel_crtc_state *pipe_config);
140 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
141 struct drm_i915_gem_object *obj,
142 struct drm_mode_fb_cmd2 *mode_cmd);
143 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
144 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
145 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
147 struct intel_link_m_n *m_n,
148 struct intel_link_m_n *m2_n2);
149 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
150 static void haswell_set_pipeconf(struct drm_crtc *crtc);
151 static void haswell_set_pipemisc(struct drm_crtc *crtc);
152 static void vlv_prepare_pll(struct intel_crtc *crtc,
153 const struct intel_crtc_state *pipe_config);
154 static void chv_prepare_pll(struct intel_crtc *crtc,
155 const struct intel_crtc_state *pipe_config);
156 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
157 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
158 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
159 struct intel_crtc_state *crtc_state);
160 static void skylake_pfit_enable(struct intel_crtc *crtc);
161 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
162 static void ironlake_pfit_enable(struct intel_crtc *crtc);
163 static void intel_modeset_setup_hw_state(struct drm_device *dev,
164 struct drm_modeset_acquire_ctx *ctx);
165 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
167 struct intel_limit {
168 struct {
169 int min, max;
170 } dot, vco, n, m, m1, m2, p, p1;
172 struct {
173 int dot_limit;
174 int p2_slow, p2_fast;
175 } p2;
176 };
178 /* returns HPLL frequency in kHz */
179 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
180 {
181 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
183 /* Obtain SKU information */
184 mutex_lock(&dev_priv->sb_lock);
185 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
186 CCK_FUSE_HPLL_FREQ_MASK;
187 mutex_unlock(&dev_priv->sb_lock);
189 return vco_freq[hpll_freq] * 1000;
190 }
192 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
193 const char *name, u32 reg, int ref_freq)
194 {
195 u32 val;
196 int divider;
198 mutex_lock(&dev_priv->sb_lock);
199 val = vlv_cck_read(dev_priv, reg);
200 mutex_unlock(&dev_priv->sb_lock);
202 divider = val & CCK_FREQUENCY_VALUES;
204 WARN((val & CCK_FREQUENCY_STATUS) !=
205 (divider << CCK_FREQUENCY_STATUS_SHIFT),
206 "%s change in progress\n", name);
208 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
209 }
211 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
212 const char *name, u32 reg)
213 {
214 if (dev_priv->hpll_freq == 0)
215 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
217 return vlv_get_cck_clock(dev_priv, name, reg,
218 dev_priv->hpll_freq);
219 }
221 static void intel_update_czclk(struct drm_i915_private *dev_priv)
222 {
223 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
224 return;
226 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
227 CCK_CZ_CLOCK_CONTROL);
229 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
230 }
232 static inline u32 /* units of 100MHz */
233 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
234 const struct intel_crtc_state *pipe_config)
235 {
236 if (HAS_DDI(dev_priv))
237 return pipe_config->port_clock; /* SPLL */
238 else
239 return dev_priv->fdi_pll_freq;
240 }
242 static const struct intel_limit intel_limits_i8xx_dac = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 908000, .max = 1512000 },
245 .n = { .min = 2, .max = 16 },
246 .m = { .min = 96, .max = 140 },
247 .m1 = { .min = 18, .max = 26 },
248 .m2 = { .min = 6, .max = 16 },
249 .p = { .min = 4, .max = 128 },
250 .p1 = { .min = 2, .max = 33 },
251 .p2 = { .dot_limit = 165000,
252 .p2_slow = 4, .p2_fast = 2 },
253 };
255 static const struct intel_limit intel_limits_i8xx_dvo = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 908000, .max = 1512000 },
258 .n = { .min = 2, .max = 16 },
259 .m = { .min = 96, .max = 140 },
260 .m1 = { .min = 18, .max = 26 },
261 .m2 = { .min = 6, .max = 16 },
262 .p = { .min = 4, .max = 128 },
263 .p1 = { .min = 2, .max = 33 },
264 .p2 = { .dot_limit = 165000,
265 .p2_slow = 4, .p2_fast = 4 },
266 };
268 static const struct intel_limit intel_limits_i8xx_lvds = {
269 .dot = { .min = 25000, .max = 350000 },
270 .vco = { .min = 908000, .max = 1512000 },
271 .n = { .min = 2, .max = 16 },
272 .m = { .min = 96, .max = 140 },
273 .m1 = { .min = 18, .max = 26 },
274 .m2 = { .min = 6, .max = 16 },
275 .p = { .min = 4, .max = 128 },
276 .p1 = { .min = 1, .max = 6 },
277 .p2 = { .dot_limit = 165000,
278 .p2_slow = 14, .p2_fast = 7 },
279 };
281 static const struct intel_limit intel_limits_i9xx_sdvo = {
282 .dot = { .min = 20000, .max = 400000 },
283 .vco = { .min = 1400000, .max = 2800000 },
284 .n = { .min = 1, .max = 6 },
285 .m = { .min = 70, .max = 120 },
286 .m1 = { .min = 8, .max = 18 },
287 .m2 = { .min = 3, .max = 7 },
288 .p = { .min = 5, .max = 80 },
289 .p1 = { .min = 1, .max = 8 },
290 .p2 = { .dot_limit = 200000,
291 .p2_slow = 10, .p2_fast = 5 },
292 };
294 static const struct intel_limit intel_limits_i9xx_lvds = {
295 .dot = { .min = 20000, .max = 400000 },
296 .vco = { .min = 1400000, .max = 2800000 },
297 .n = { .min = 1, .max = 6 },
298 .m = { .min = 70, .max = 120 },
299 .m1 = { .min = 8, .max = 18 },
300 .m2 = { .min = 3, .max = 7 },
301 .p = { .min = 7, .max = 98 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 112000,
304 .p2_slow = 14, .p2_fast = 7 },
305 };
308 static const struct intel_limit intel_limits_g4x_sdvo = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 1750000, .max = 3500000},
311 .n = { .min = 1, .max = 4 },
312 .m = { .min = 104, .max = 138 },
313 .m1 = { .min = 17, .max = 23 },
314 .m2 = { .min = 5, .max = 11 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 1, .max = 3},
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 10,
319 .p2_fast = 10
320 },
321 };
323 static const struct intel_limit intel_limits_g4x_hdmi = {
324 .dot = { .min = 22000, .max = 400000 },
325 .vco = { .min = 1750000, .max = 3500000},
326 .n = { .min = 1, .max = 4 },
327 .m = { .min = 104, .max = 138 },
328 .m1 = { .min = 16, .max = 23 },
329 .m2 = { .min = 5, .max = 11 },
330 .p = { .min = 5, .max = 80 },
331 .p1 = { .min = 1, .max = 8},
332 .p2 = { .dot_limit = 165000,
333 .p2_slow = 10, .p2_fast = 5 },
334 };
336 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
337 .dot = { .min = 20000, .max = 115000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 28, .max = 112 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 14, .p2_fast = 14
347 },
348 };
350 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
351 .dot = { .min = 80000, .max = 224000 },
352 .vco = { .min = 1750000, .max = 3500000 },
353 .n = { .min = 1, .max = 3 },
354 .m = { .min = 104, .max = 138 },
355 .m1 = { .min = 17, .max = 23 },
356 .m2 = { .min = 5, .max = 11 },
357 .p = { .min = 14, .max = 42 },
358 .p1 = { .min = 2, .max = 6 },
359 .p2 = { .dot_limit = 0,
360 .p2_slow = 7, .p2_fast = 7
361 },
362 };
364 static const struct intel_limit intel_limits_pineview_sdvo = {
365 .dot = { .min = 20000, .max = 400000},
366 .vco = { .min = 1700000, .max = 3500000 },
367 /* Pineview's Ncounter is a ring counter */
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 /* Pineview only has one combined m divider, which we treat as m2. */
371 .m1 = { .min = 0, .max = 0 },
372 .m2 = { .min = 0, .max = 254 },
373 .p = { .min = 5, .max = 80 },
374 .p1 = { .min = 1, .max = 8 },
375 .p2 = { .dot_limit = 200000,
376 .p2_slow = 10, .p2_fast = 5 },
377 };
379 static const struct intel_limit intel_limits_pineview_lvds = {
380 .dot = { .min = 20000, .max = 400000 },
381 .vco = { .min = 1700000, .max = 3500000 },
382 .n = { .min = 3, .max = 6 },
383 .m = { .min = 2, .max = 256 },
384 .m1 = { .min = 0, .max = 0 },
385 .m2 = { .min = 0, .max = 254 },
386 .p = { .min = 7, .max = 112 },
387 .p1 = { .min = 1, .max = 8 },
388 .p2 = { .dot_limit = 112000,
389 .p2_slow = 14, .p2_fast = 14 },
390 };
392 /* Ironlake / Sandybridge
393 *
394 * We calculate clock using (register_value + 2) for N/M1/M2, so here
395 * the range value for them is (actual_value - 2).
396 */
397 static const struct intel_limit intel_limits_ironlake_dac = {
398 .dot = { .min = 25000, .max = 350000 },
399 .vco = { .min = 1760000, .max = 3510000 },
400 .n = { .min = 1, .max = 5 },
401 .m = { .min = 79, .max = 127 },
402 .m1 = { .min = 12, .max = 22 },
403 .m2 = { .min = 5, .max = 9 },
404 .p = { .min = 5, .max = 80 },
405 .p1 = { .min = 1, .max = 8 },
406 .p2 = { .dot_limit = 225000,
407 .p2_slow = 10, .p2_fast = 5 },
408 };
410 static const struct intel_limit intel_limits_ironlake_single_lvds = {
411 .dot = { .min = 25000, .max = 350000 },
412 .vco = { .min = 1760000, .max = 3510000 },
413 .n = { .min = 1, .max = 3 },
414 .m = { .min = 79, .max = 118 },
415 .m1 = { .min = 12, .max = 22 },
416 .m2 = { .min = 5, .max = 9 },
417 .p = { .min = 28, .max = 112 },
418 .p1 = { .min = 2, .max = 8 },
419 .p2 = { .dot_limit = 225000,
420 .p2_slow = 14, .p2_fast = 14 },
421 };
423 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 3 },
427 .m = { .min = 79, .max = 127 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 14, .max = 56 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 7, .p2_fast = 7 },
434 };
436 /* LVDS 100mhz refclk limits. */
437 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
438 .dot = { .min = 25000, .max = 350000 },
439 .vco = { .min = 1760000, .max = 3510000 },
440 .n = { .min = 1, .max = 2 },
441 .m = { .min = 79, .max = 126 },
442 .m1 = { .min = 12, .max = 22 },
443 .m2 = { .min = 5, .max = 9 },
444 .p = { .min = 28, .max = 112 },
445 .p1 = { .min = 2, .max = 8 },
446 .p2 = { .dot_limit = 225000,
447 .p2_slow = 14, .p2_fast = 14 },
448 };
450 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
451 .dot = { .min = 25000, .max = 350000 },
452 .vco = { .min = 1760000, .max = 3510000 },
453 .n = { .min = 1, .max = 3 },
454 .m = { .min = 79, .max = 126 },
455 .m1 = { .min = 12, .max = 22 },
456 .m2 = { .min = 5, .max = 9 },
457 .p = { .min = 14, .max = 42 },
458 .p1 = { .min = 2, .max = 6 },
459 .p2 = { .dot_limit = 225000,
460 .p2_slow = 7, .p2_fast = 7 },
461 };
463 static const struct intel_limit intel_limits_vlv = {
464 /*
465 * These are the data rate limits (measured in fast clocks)
466 * since those are the strictest limits we have. The fast
467 * clock and actual rate limits are more relaxed, so checking
468 * them would make no difference.
469 */
470 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
471 .vco = { .min = 4000000, .max = 6000000 },
472 .n = { .min = 1, .max = 7 },
473 .m1 = { .min = 2, .max = 3 },
474 .m2 = { .min = 11, .max = 156 },
475 .p1 = { .min = 2, .max = 3 },
476 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
477 };
479 static const struct intel_limit intel_limits_chv = {
480 /*
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
485 */
486 .dot = { .min = 25000 * 5, .max = 540000 * 5},
487 .vco = { .min = 4800000, .max = 6480000 },
488 .n = { .min = 1, .max = 1 },
489 .m1 = { .min = 2, .max = 2 },
490 .m2 = { .min = 24 << 22, .max = 175 << 22 },
491 .p1 = { .min = 2, .max = 4 },
492 .p2 = { .p2_slow = 1, .p2_fast = 14 },
493 };
495 static const struct intel_limit intel_limits_bxt = {
496 /* FIXME: find real dot limits */
497 .dot = { .min = 0, .max = INT_MAX },
498 .vco = { .min = 4800000, .max = 6700000 },
499 .n = { .min = 1, .max = 1 },
500 .m1 = { .min = 2, .max = 2 },
501 /* FIXME: find real m2 limits */
502 .m2 = { .min = 2 << 22, .max = 255 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 20 },
505 };
507 static void
508 skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
509 {
510 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
511 return;
513 if (enable)
514 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
515 else
516 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
517 }
519 static void
520 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
521 {
522 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
523 return;
525 if (enable)
526 I915_WRITE(CLKGATE_DIS_PSL(pipe),
527 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
528 else
529 I915_WRITE(CLKGATE_DIS_PSL(pipe),
530 I915_READ(CLKGATE_DIS_PSL(pipe)) &
531 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
532 }
534 static bool
535 needs_modeset(const struct drm_crtc_state *state)
536 {
537 return drm_atomic_crtc_needs_modeset(state);
538 }
540 /*
541 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
542 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
543 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
544 * The helpers' return value is the rate of the clock that is fed to the
545 * display engine's pipe which can be the above fast dot clock rate or a
546 * divided-down version of it.
547 */
548 /* m1 is reserved as 0 in Pineview, n is a ring counter */
549 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551 clock->m = clock->m2 + 2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return 0;
555 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 return clock->dot;
559 }
561 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
562 {
563 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
564 }
566 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
567 {
568 clock->m = i9xx_dpll_compute_m(clock);
569 clock->p = clock->p1 * clock->p2;
570 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
571 return 0;
572 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
573 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
575 return clock->dot;
576 }
578 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
579 {
580 clock->m = clock->m1 * clock->m2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
583 return 0;
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587 return clock->dot / 5;
588 }
590 int chv_calc_dpll_params(int refclk, struct dpll *clock)
591 {
592 clock->m = clock->m1 * clock->m2;
593 clock->p = clock->p1 * clock->p2;
594 if (WARN_ON(clock->n == 0 || clock->p == 0))
595 return 0;
596 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
597 clock->n << 22);
598 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
600 return clock->dot / 5;
601 }
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 /*
606 * Returns whether the given set of divisors are valid for a given refclk with
607 * the given connectors.
608 */
609 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
610 const struct intel_limit *limit,
611 const struct dpll *clock)
612 {
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
616 INTELPllInvalid("p1 out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
622 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
623 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
624 if (clock->m1 <= clock->m2)
625 INTELPllInvalid("m1 <= m2\n");
627 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
628 !IS_GEN9_LP(dev_priv)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
643 return true;
644 }
646 static int
647 i9xx_select_p2_div(const struct intel_limit *limit,
648 const struct intel_crtc_state *crtc_state,
649 int target)
650 {
651 struct drm_device *dev = crtc_state->base.crtc->dev;
653 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 return limit->p2.p2_fast;
661 else
662 return limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 return limit->p2.p2_slow;
666 else
667 return limit->p2.p2_fast;
668 }
669 }
671 /*
672 * Returns a set of divisors for the desired target clock with the given
673 * refclk, or FALSE. The returned values represent the clock equation:
674 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
675 *
676 * Target and reference clocks are specified in kHz.
677 *
678 * If match_clock is provided, then best_clock P divider must match the P
679 * divider from @match_clock used for LVDS downclocking.
680 */
681 static bool
682 i9xx_find_best_dpll(const struct intel_limit *limit,
683 struct intel_crtc_state *crtc_state,
684 int target, int refclk, struct dpll *match_clock,
685 struct dpll *best_clock)
686 {
687 struct drm_device *dev = crtc_state->base.crtc->dev;
688 struct dpll clock;
689 int err = target;
691 memset(best_clock, 0, sizeof(*best_clock));
693 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
695 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
696 clock.m1++) {
697 for (clock.m2 = limit->m2.min;
698 clock.m2 <= limit->m2.max; clock.m2++) {
699 if (clock.m2 >= clock.m1)
700 break;
701 for (clock.n = limit->n.min;
702 clock.n <= limit->n.max; clock.n++) {
703 for (clock.p1 = limit->p1.min;
704 clock.p1 <= limit->p1.max; clock.p1++) {
705 int this_err;
707 i9xx_calc_dpll_params(refclk, &clock);
708 if (!intel_PLL_is_valid(to_i915(dev),
709 limit,
710 &clock))
711 continue;
712 if (match_clock &&
713 clock.p != match_clock->p)
714 continue;
716 this_err = abs(clock.dot - target);
717 if (this_err < err) {
718 *best_clock = clock;
719 err = this_err;
720 }
721 }
722 }
723 }
724 }
726 return (err != target);
727 }
729 /*
730 * Returns a set of divisors for the desired target clock with the given
731 * refclk, or FALSE. The returned values represent the clock equation:
732 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
733 *
734 * Target and reference clocks are specified in kHz.
735 *
736 * If match_clock is provided, then best_clock P divider must match the P
737 * divider from @match_clock used for LVDS downclocking.
738 */
739 static bool
740 pnv_find_best_dpll(const struct intel_limit *limit,
741 struct intel_crtc_state *crtc_state,
742 int target, int refclk, struct dpll *match_clock,
743 struct dpll *best_clock)
744 {
745 struct drm_device *dev = crtc_state->base.crtc->dev;
746 struct dpll clock;
747 int err = target;
749 memset(best_clock, 0, sizeof(*best_clock));
751 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
754 clock.m1++) {
755 for (clock.m2 = limit->m2.min;
756 clock.m2 <= limit->m2.max; clock.m2++) {
757 for (clock.n = limit->n.min;
758 clock.n <= limit->n.max; clock.n++) {
759 for (clock.p1 = limit->p1.min;
760 clock.p1 <= limit->p1.max; clock.p1++) {
761 int this_err;
763 pnv_calc_dpll_params(refclk, &clock);
764 if (!intel_PLL_is_valid(to_i915(dev),
765 limit,
766 &clock))
767 continue;
768 if (match_clock &&
769 clock.p != match_clock->p)
770 continue;
772 this_err = abs(clock.dot - target);
773 if (this_err < err) {
774 *best_clock = clock;
775 err = this_err;
776 }
777 }
778 }
779 }
780 }
782 return (err != target);
783 }
785 /*
786 * Returns a set of divisors for the desired target clock with the given
787 * refclk, or FALSE. The returned values represent the clock equation:
788 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
789 *
790 * Target and reference clocks are specified in kHz.
791 *
792 * If match_clock is provided, then best_clock P divider must match the P
793 * divider from @match_clock used for LVDS downclocking.
794 */
795 static bool
796 g4x_find_best_dpll(const struct intel_limit *limit,
797 struct intel_crtc_state *crtc_state,
798 int target, int refclk, struct dpll *match_clock,
799 struct dpll *best_clock)
800 {
801 struct drm_device *dev = crtc_state->base.crtc->dev;
802 struct dpll clock;
803 int max_n;
804 bool found = false;
805 /* approximately equals target * 0.00585 */
806 int err_most = (target >> 8) + (target >> 9);
808 memset(best_clock, 0, sizeof(*best_clock));
810 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
812 max_n = limit->n.max;
813 /* based on hardware requirement, prefer smaller n to precision */
814 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
815 /* based on hardware requirement, prefere larger m1,m2 */
816 for (clock.m1 = limit->m1.max;
817 clock.m1 >= limit->m1.min; clock.m1--) {
818 for (clock.m2 = limit->m2.max;
819 clock.m2 >= limit->m2.min; clock.m2--) {
820 for (clock.p1 = limit->p1.max;
821 clock.p1 >= limit->p1.min; clock.p1--) {
822 int this_err;
824 i9xx_calc_dpll_params(refclk, &clock);
825 if (!intel_PLL_is_valid(to_i915(dev),
826 limit,
827 &clock))
828 continue;
830 this_err = abs(clock.dot - target);
831 if (this_err < err_most) {
832 *best_clock = clock;
833 err_most = this_err;
834 max_n = clock.n;
835 found = true;
836 }
837 }
838 }
839 }
840 }
841 return found;
842 }
844 /*
845 * Check if the calculated PLL configuration is more optimal compared to the
846 * best configuration and error found so far. Return the calculated error.
847 */
848 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
849 const struct dpll *calculated_clock,
850 const struct dpll *best_clock,
851 unsigned int best_error_ppm,
852 unsigned int *error_ppm)
853 {
854 /*
855 * For CHV ignore the error and consider only the P value.
856 * Prefer a bigger P value based on HW requirements.
857 */
858 if (IS_CHERRYVIEW(to_i915(dev))) {
859 *error_ppm = 0;
861 return calculated_clock->p > best_clock->p;
862 }
864 if (WARN_ON_ONCE(!target_freq))
865 return false;
867 *error_ppm = div_u64(1000000ULL *
868 abs(target_freq - calculated_clock->dot),
869 target_freq);
870 /*
871 * Prefer a better P value over a better (smaller) error if the error
872 * is small. Ensure this preference for future configurations too by
873 * setting the error to 0.
874 */
875 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
876 *error_ppm = 0;
878 return true;
879 }
881 return *error_ppm + 10 < best_error_ppm;
882 }
884 /*
885 * Returns a set of divisors for the desired target clock with the given
886 * refclk, or FALSE. The returned values represent the clock equation:
887 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
888 */
889 static bool
890 vlv_find_best_dpll(const struct intel_limit *limit,
891 struct intel_crtc_state *crtc_state,
892 int target, int refclk, struct dpll *match_clock,
893 struct dpll *best_clock)
894 {
895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
896 struct drm_device *dev = crtc->base.dev;
897 struct dpll clock;
898 unsigned int bestppm = 1000000;
899 /* min update 19.2 MHz */
900 int max_n = min(limit->n.max, refclk / 19200);
901 bool found = false;
903 target *= 5; /* fast clock */
905 memset(best_clock, 0, sizeof(*best_clock));
907 /* based on hardware requirement, prefer smaller n to precision */
908 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
909 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
910 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 clock.p = clock.p1 * clock.p2;
913 /* based on hardware requirement, prefer bigger m1,m2 values */
914 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
915 unsigned int ppm;
917 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
918 refclk * clock.m1);
920 vlv_calc_dpll_params(refclk, &clock);
922 if (!intel_PLL_is_valid(to_i915(dev),
923 limit,
924 &clock))
925 continue;
927 if (!vlv_PLL_is_optimal(dev, target,
928 &clock,
929 best_clock,
930 bestppm, &ppm))
931 continue;
933 *best_clock = clock;
934 bestppm = ppm;
935 found = true;
936 }
937 }
938 }
939 }
941 return found;
942 }
944 /*
945 * Returns a set of divisors for the desired target clock with the given
946 * refclk, or FALSE. The returned values represent the clock equation:
947 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
948 */
949 static bool
950 chv_find_best_dpll(const struct intel_limit *limit,
951 struct intel_crtc_state *crtc_state,
952 int target, int refclk, struct dpll *match_clock,
953 struct dpll *best_clock)
954 {
955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
956 struct drm_device *dev = crtc->base.dev;
957 unsigned int best_error_ppm;
958 struct dpll clock;
959 uint64_t m2;
960 int found = false;
962 memset(best_clock, 0, sizeof(*best_clock));
963 best_error_ppm = 1000000;
965 /*
966 * Based on hardware doc, the n always set to 1, and m1 always
967 * set to 2. If requires to support 200Mhz refclk, we need to
968 * revisit this because n may not 1 anymore.
969 */
970 clock.n = 1, clock.m1 = 2;
971 target *= 5; /* fast clock */
973 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
974 for (clock.p2 = limit->p2.p2_fast;
975 clock.p2 >= limit->p2.p2_slow;
976 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
977 unsigned int error_ppm;
979 clock.p = clock.p1 * clock.p2;
981 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
982 clock.n) << 22, refclk * clock.m1);
984 if (m2 > INT_MAX/clock.m1)
985 continue;
987 clock.m2 = m2;
989 chv_calc_dpll_params(refclk, &clock);
991 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
992 continue;
994 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
995 best_error_ppm, &error_ppm))
996 continue;
998 *best_clock = clock;
999 best_error_ppm = error_ppm;
1000 found = true;
1001 }
1002 }
1004 return found;
1005 }
1007 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1008 struct dpll *best_clock)
1009 {
1010 int refclk = 100000;
1011 const struct intel_limit *limit = &intel_limits_bxt;
1013 return chv_find_best_dpll(limit, crtc_state,
1014 target_clock, refclk, NULL, best_clock);
1015 }
1017 bool intel_crtc_active(struct intel_crtc *crtc)
1018 {
1019 /* Be paranoid as we can arrive here with only partial
1020 * state retrieved from the hardware during setup.
1021 *
1022 * We can ditch the adjusted_mode.crtc_clock check as soon
1023 * as Haswell has gained clock readout/fastboot support.
1024 *
1025 * We can ditch the crtc->primary->state->fb check as soon as we can
1026 * properly reconstruct framebuffers.
1027 *
1028 * FIXME: The intel_crtc->active here should be switched to
1029 * crtc->state->active once we have proper CRTC states wired up
1030 * for atomic.
1031 */
1032 return crtc->active && crtc->base.primary->state->fb &&
1033 crtc->config->base.adjusted_mode.crtc_clock;
1034 }
1036 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1037 enum pipe pipe)
1038 {
1039 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1041 return crtc->config->cpu_transcoder;
1042 }
1044 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1045 enum pipe pipe)
1046 {
1047 i915_reg_t reg = PIPEDSL(pipe);
1048 u32 line1, line2;
1049 u32 line_mask;
1051 if (IS_GEN2(dev_priv))
1052 line_mask = DSL_LINEMASK_GEN2;
1053 else
1054 line_mask = DSL_LINEMASK_GEN3;
1056 line1 = I915_READ(reg) & line_mask;
1057 msleep(5);
1058 line2 = I915_READ(reg) & line_mask;
1060 return line1 != line2;
1061 }
1063 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1064 {
1065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1066 enum pipe pipe = crtc->pipe;
1068 /* Wait for the display line to settle/start moving */
1069 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1070 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1071 pipe_name(pipe), onoff(state));
1072 }
1074 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1075 {
1076 wait_for_pipe_scanline_moving(crtc, false);
1077 }
1079 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1080 {
1081 wait_for_pipe_scanline_moving(crtc, true);
1082 }
1084 static void
1085 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1086 {
1087 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1090 if (INTEL_GEN(dev_priv) >= 4) {
1091 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1092 i915_reg_t reg = PIPECONF(cpu_transcoder);
1094 /* Wait for the Pipe State to go off */
1095 if (intel_wait_for_register(dev_priv,
1096 reg, I965_PIPECONF_ACTIVE, 0,
1097 100))
1098 WARN(1, "pipe_off wait timed out\n");
1099 } else {
1100 intel_wait_for_pipe_scanline_stopped(crtc);
1101 }
1102 }
1104 /* Only for pre-ILK configs */
1105 void assert_pll(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 u32 val;
1109 bool cur_state;
1111 val = I915_READ(DPLL(pipe));
1112 cur_state = !!(val & DPLL_VCO_ENABLE);
1113 I915_STATE_WARN(cur_state != state,
1114 "PLL state assertion failure (expected %s, current %s)\n",
1115 onoff(state), onoff(cur_state));
1116 }
1118 /* XXX: the dsi pll is shared between MIPI DSI ports */
1119 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1120 {
1121 u32 val;
1122 bool cur_state;
1124 mutex_lock(&dev_priv->sb_lock);
1125 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1126 mutex_unlock(&dev_priv->sb_lock);
1128 cur_state = val & DSI_PLL_VCO_EN;
1129 I915_STATE_WARN(cur_state != state,
1130 "DSI PLL state assertion failure (expected %s, current %s)\n",
1131 onoff(state), onoff(cur_state));
1132 }
1134 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1136 {
1137 bool cur_state;
1138 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1139 pipe);
1141 if (HAS_DDI(dev_priv)) {
1142 /* DDI does not have a specific FDI_TX register */
1143 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1144 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1145 } else {
1146 u32 val = I915_READ(FDI_TX_CTL(pipe));
1147 cur_state = !!(val & FDI_TX_ENABLE);
1148 }
1149 I915_STATE_WARN(cur_state != state,
1150 "FDI TX state assertion failure (expected %s, current %s)\n",
1151 onoff(state), onoff(cur_state));
1152 }
1153 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1154 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1156 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1157 enum pipe pipe, bool state)
1158 {
1159 u32 val;
1160 bool cur_state;
1162 val = I915_READ(FDI_RX_CTL(pipe));
1163 cur_state = !!(val & FDI_RX_ENABLE);
1164 I915_STATE_WARN(cur_state != state,
1165 "FDI RX state assertion failure (expected %s, current %s)\n",
1166 onoff(state), onoff(cur_state));
1167 }
1168 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1169 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1171 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173 {
1174 u32 val;
1176 /* ILK FDI PLL is always enabled */
1177 if (IS_GEN5(dev_priv))
1178 return;
1180 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181 if (HAS_DDI(dev_priv))
1182 return;
1184 val = I915_READ(FDI_TX_CTL(pipe));
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 u32 val;
1192 bool cur_state;
1194 val = I915_READ(FDI_RX_CTL(pipe));
1195 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1198 onoff(state), onoff(cur_state));
1199 }
1201 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1202 {
1203 i915_reg_t pp_reg;
1204 u32 val;
1205 enum pipe panel_pipe = INVALID_PIPE;
1206 bool locked = true;
1208 if (WARN_ON(HAS_DDI(dev_priv)))
1209 return;
1211 if (HAS_PCH_SPLIT(dev_priv)) {
1212 u32 port_sel;
1214 pp_reg = PP_CONTROL(0);
1215 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1217 switch (port_sel) {
1218 case PANEL_PORT_SELECT_LVDS:
1219 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1220 break;
1221 case PANEL_PORT_SELECT_DPA:
1222 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1223 break;
1224 case PANEL_PORT_SELECT_DPC:
1225 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1226 break;
1227 case PANEL_PORT_SELECT_DPD:
1228 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1229 break;
1230 default:
1231 MISSING_CASE(port_sel);
1232 break;
1233 }
1234 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1235 /* presumably write lock depends on pipe, not port select */
1236 pp_reg = PP_CONTROL(pipe);
1237 panel_pipe = pipe;
1238 } else {
1239 u32 port_sel;
1241 pp_reg = PP_CONTROL(0);
1242 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1244 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1245 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1246 }
1248 val = I915_READ(pp_reg);
1249 if (!(val & PANEL_POWER_ON) ||
1250 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1251 locked = false;
1253 I915_STATE_WARN(panel_pipe == pipe && locked,
1254 "panel assertion failure, pipe %c regs locked\n",
1255 pipe_name(pipe));
1256 }
1258 void assert_pipe(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, bool state)
1260 {
1261 bool cur_state;
1262 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1263 pipe);
1264 enum intel_display_power_domain power_domain;
1266 /* we keep both pipes enabled on 830 */
1267 if (IS_I830(dev_priv))
1268 state = true;
1270 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1271 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1272 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1273 cur_state = !!(val & PIPECONF_ENABLE);
1275 intel_display_power_put(dev_priv, power_domain);
1276 } else {
1277 cur_state = false;
1278 }
1280 I915_STATE_WARN(cur_state != state,
1281 "pipe %c assertion failure (expected %s, current %s)\n",
1282 pipe_name(pipe), onoff(state), onoff(cur_state));
1283 }
1285 static void assert_plane(struct intel_plane *plane, bool state)
1286 {
1287 enum pipe pipe;
1288 bool cur_state;
1290 cur_state = plane->get_hw_state(plane, &pipe);
1292 I915_STATE_WARN(cur_state != state,
1293 "%s assertion failure (expected %s, current %s)\n",
1294 plane->base.name, onoff(state), onoff(cur_state));
1295 }
1297 #define assert_plane_enabled(p) assert_plane(p, true)
1298 #define assert_plane_disabled(p) assert_plane(p, false)
1300 static void assert_planes_disabled(struct intel_crtc *crtc)
1301 {
1302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1303 struct intel_plane *plane;
1305 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1306 assert_plane_disabled(plane);
1307 }
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1310 {
1311 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312 drm_crtc_vblank_put(crtc);
1313 }
1315 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317 {
1318 u32 val;
1319 bool enabled;
1321 val = I915_READ(PCH_TRANSCONF(pipe));
1322 enabled = !!(val & TRANS_ENABLE);
1323 I915_STATE_WARN(enabled,
1324 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1325 pipe_name(pipe));
1326 }
1328 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1329 enum pipe pipe, enum port port,
1330 i915_reg_t dp_reg)
1331 {
1332 enum pipe port_pipe;
1333 bool state;
1335 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1337 I915_STATE_WARN(state && port_pipe == pipe,
1338 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1339 port_name(port), pipe_name(pipe));
1341 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1342 "IBX PCH DP %c still using transcoder B\n",
1343 port_name(port));
1344 }
1346 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, enum port port,
1348 i915_reg_t hdmi_reg)
1349 {
1350 enum pipe port_pipe;
1351 bool state;
1353 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1355 I915_STATE_WARN(state && port_pipe == pipe,
1356 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1357 port_name(port), pipe_name(pipe));
1359 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1360 "IBX PCH HDMI %c still using transcoder B\n",
1361 port_name(port));
1362 }
1364 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 enum pipe port_pipe;
1369 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1370 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1371 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1373 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1374 port_pipe == pipe,
1375 "PCH VGA enabled on transcoder %c, should be disabled\n",
1376 pipe_name(pipe));
1378 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1379 port_pipe == pipe,
1380 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1381 pipe_name(pipe));
1383 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1384 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1385 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1386 }
1388 static void _vlv_enable_pll(struct intel_crtc *crtc,
1389 const struct intel_crtc_state *pipe_config)
1390 {
1391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1392 enum pipe pipe = crtc->pipe;
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1395 POSTING_READ(DPLL(pipe));
1396 udelay(150);
1398 if (intel_wait_for_register(dev_priv,
1399 DPLL(pipe),
1400 DPLL_LOCK_VLV,
1401 DPLL_LOCK_VLV,
1402 1))
1403 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1404 }
1406 static void vlv_enable_pll(struct intel_crtc *crtc,
1407 const struct intel_crtc_state *pipe_config)
1408 {
1409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1410 enum pipe pipe = crtc->pipe;
1412 assert_pipe_disabled(dev_priv, pipe);
1414 /* PLL is protected by panel, make sure we can write it */
1415 assert_panel_unlocked(dev_priv, pipe);
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1418 _vlv_enable_pll(crtc, pipe_config);
1420 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1421 POSTING_READ(DPLL_MD(pipe));
1422 }
1425 static void _chv_enable_pll(struct intel_crtc *crtc,
1426 const struct intel_crtc_state *pipe_config)
1427 {
1428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1429 enum pipe pipe = crtc->pipe;
1430 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1431 u32 tmp;
1433 mutex_lock(&dev_priv->sb_lock);
1435 /* Enable back the 10bit clock to display controller */
1436 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1437 tmp |= DPIO_DCLKP_EN;
1438 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1440 mutex_unlock(&dev_priv->sb_lock);
1442 /*
1443 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1444 */
1445 udelay(1);
1447 /* Enable PLL */
1448 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1450 /* Check PLL is locked */
1451 if (intel_wait_for_register(dev_priv,
1452 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1453 1))
1454 DRM_ERROR("PLL %d failed to lock\n", pipe);
1455 }
1457 static void chv_enable_pll(struct intel_crtc *crtc,
1458 const struct intel_crtc_state *pipe_config)
1459 {
1460 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1461 enum pipe pipe = crtc->pipe;
1463 assert_pipe_disabled(dev_priv, pipe);
1465 /* PLL is protected by panel, make sure we can write it */
1466 assert_panel_unlocked(dev_priv, pipe);
1468 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1469 _chv_enable_pll(crtc, pipe_config);
1471 if (pipe != PIPE_A) {
1472 /*
1473 * WaPixelRepeatModeFixForC0:chv
1474 *
1475 * DPLLCMD is AWOL. Use chicken bits to propagate
1476 * the value from DPLLBMD to either pipe B or C.
1477 */
1478 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1479 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1480 I915_WRITE(CBR4_VLV, 0);
1481 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1483 /*
1484 * DPLLB VGA mode also seems to cause problems.
1485 * We should always have it disabled.
1486 */
1487 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1488 } else {
1489 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1490 POSTING_READ(DPLL_MD(pipe));
1491 }
1492 }
1494 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1495 {
1496 struct intel_crtc *crtc;
1497 int count = 0;
1499 for_each_intel_crtc(&dev_priv->drm, crtc) {
1500 count += crtc->base.state->active &&
1501 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1502 }
1504 return count;
1505 }
1507 static void i9xx_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_state *crtc_state)
1509 {
1510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1511 i915_reg_t reg = DPLL(crtc->pipe);
1512 u32 dpll = crtc_state->dpll_hw_state.dpll;
1513 int i;
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1517 /* PLL is protected by panel, make sure we can write it */
1518 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1519 assert_panel_unlocked(dev_priv, crtc->pipe);
1521 /* Enable DVO 2x clock on both PLLs if necessary */
1522 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1523 /*
1524 * It appears to be important that we don't enable this
1525 * for the current pipe before otherwise configuring the
1526 * PLL. No idea how this should be handled if multiple
1527 * DVO outputs are enabled simultaneosly.
1528 */
1529 dpll |= DPLL_DVO_2X_MODE;
1530 I915_WRITE(DPLL(!crtc->pipe),
1531 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1532 }
1534 /*
1535 * Apparently we need to have VGA mode enabled prior to changing
1536 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1537 * dividers, even though the register value does change.
1538 */
1539 I915_WRITE(reg, 0);
1541 I915_WRITE(reg, dpll);
1543 /* Wait for the clocks to stabilize. */
1544 POSTING_READ(reg);
1545 udelay(150);
1547 if (INTEL_GEN(dev_priv) >= 4) {
1548 I915_WRITE(DPLL_MD(crtc->pipe),
1549 crtc_state->dpll_hw_state.dpll_md);
1550 } else {
1551 /* The pixel multiplier can only be updated once the
1552 * DPLL is enabled and the clocks are stable.
1553 *
1554 * So write it again.
1555 */
1556 I915_WRITE(reg, dpll);
1557 }
1559 /* We do this three times for luck */
1560 for (i = 0; i < 3; i++) {
1561 I915_WRITE(reg, dpll);
1562 POSTING_READ(reg);
1563 udelay(150); /* wait for warmup */
1564 }
1565 }
1567 static void i9xx_disable_pll(struct intel_crtc *crtc)
1568 {
1569 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1570 enum pipe pipe = crtc->pipe;
1572 /* Disable DVO 2x clock on both PLLs if necessary */
1573 if (IS_I830(dev_priv) &&
1574 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1575 !intel_num_dvo_pipes(dev_priv)) {
1576 I915_WRITE(DPLL(PIPE_B),
1577 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1578 I915_WRITE(DPLL(PIPE_A),
1579 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1580 }
1582 /* Don't disable pipe or pipe PLLs if needed */
1583 if (IS_I830(dev_priv))
1584 return;
1586 /* Make sure the pipe isn't still relying on us */
1587 assert_pipe_disabled(dev_priv, pipe);
1589 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1590 POSTING_READ(DPLL(pipe));
1591 }
1593 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1594 {
1595 u32 val;
1597 /* Make sure the pipe isn't still relying on us */
1598 assert_pipe_disabled(dev_priv, pipe);
1600 val = DPLL_INTEGRATED_REF_CLK_VLV |
1601 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1602 if (pipe != PIPE_A)
1603 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1605 I915_WRITE(DPLL(pipe), val);
1606 POSTING_READ(DPLL(pipe));
1607 }
1609 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1610 {
1611 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1612 u32 val;
1614 /* Make sure the pipe isn't still relying on us */
1615 assert_pipe_disabled(dev_priv, pipe);
1617 val = DPLL_SSC_REF_CLK_CHV |
1618 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1619 if (pipe != PIPE_A)
1620 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1622 I915_WRITE(DPLL(pipe), val);
1623 POSTING_READ(DPLL(pipe));
1625 mutex_lock(&dev_priv->sb_lock);
1627 /* Disable 10bit clock to display controller */
1628 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1629 val &= ~DPIO_DCLKP_EN;
1630 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1632 mutex_unlock(&dev_priv->sb_lock);
1633 }
1635 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1636 struct intel_digital_port *dport,
1637 unsigned int expected_mask)
1638 {
1639 u32 port_mask;
1640 i915_reg_t dpll_reg;
1642 switch (dport->base.port) {
1643 case PORT_B:
1644 port_mask = DPLL_PORTB_READY_MASK;
1645 dpll_reg = DPLL(0);
1646 break;
1647 case PORT_C:
1648 port_mask = DPLL_PORTC_READY_MASK;
1649 dpll_reg = DPLL(0);
1650 expected_mask <<= 4;
1651 break;
1652 case PORT_D:
1653 port_mask = DPLL_PORTD_READY_MASK;
1654 dpll_reg = DPIO_PHY_STATUS;
1655 break;
1656 default:
1657 BUG();
1658 }
1660 if (intel_wait_for_register(dev_priv,
1661 dpll_reg, port_mask, expected_mask,
1662 1000))
1663 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1664 port_name(dport->base.port),
1665 I915_READ(dpll_reg) & port_mask, expected_mask);
1666 }
1668 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1669 enum pipe pipe)
1670 {
1671 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1672 pipe);
1673 i915_reg_t reg;
1674 uint32_t val, pipeconf_val;
1676 /* Make sure PCH DPLL is enabled */
1677 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1679 /* FDI must be feeding us bits for PCH ports */
1680 assert_fdi_tx_enabled(dev_priv, pipe);
1681 assert_fdi_rx_enabled(dev_priv, pipe);
1683 if (HAS_PCH_CPT(dev_priv)) {
1684 /* Workaround: Set the timing override bit before enabling the
1685 * pch transcoder. */
1686 reg = TRANS_CHICKEN2(pipe);
1687 val = I915_READ(reg);
1688 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1689 I915_WRITE(reg, val);
1690 }
1692 reg = PCH_TRANSCONF(pipe);
1693 val = I915_READ(reg);
1694 pipeconf_val = I915_READ(PIPECONF(pipe));
1696 if (HAS_PCH_IBX(dev_priv)) {
1697 /*
1698 * Make the BPC in transcoder be consistent with
1699 * that in pipeconf reg. For HDMI we must use 8bpc
1700 * here for both 8bpc and 12bpc.
1701 */
1702 val &= ~PIPECONF_BPC_MASK;
1703 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1704 val |= PIPECONF_8BPC;
1705 else
1706 val |= pipeconf_val & PIPECONF_BPC_MASK;
1707 }
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711 if (HAS_PCH_IBX(dev_priv) &&
1712 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
1716 else
1717 val |= TRANS_PROGRESSIVE;
1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (intel_wait_for_register(dev_priv,
1721 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1722 100))
1723 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1724 }
1726 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1727 enum transcoder cpu_transcoder)
1728 {
1729 u32 val, pipeconf_val;
1731 /* FDI must be feeding us bits for PCH ports */
1732 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1733 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1735 /* Workaround: set timing override bit. */
1736 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1737 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1738 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1740 val = TRANS_ENABLE;
1741 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1743 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1744 PIPECONF_INTERLACED_ILK)
1745 val |= TRANS_INTERLACED;
1746 else
1747 val |= TRANS_PROGRESSIVE;
1749 I915_WRITE(LPT_TRANSCONF, val);
1750 if (intel_wait_for_register(dev_priv,
1751 LPT_TRANSCONF,
1752 TRANS_STATE_ENABLE,
1753 TRANS_STATE_ENABLE,
1754 100))
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
1756 }
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1759 enum pipe pipe)
1760 {
1761 i915_reg_t reg;
1762 uint32_t val;
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1771 reg = PCH_TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (intel_wait_for_register(dev_priv,
1777 reg, TRANS_STATE_ENABLE, 0,
1778 50))
1779 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1781 if (HAS_PCH_CPT(dev_priv)) {
1782 /* Workaround: Clear the timing override chicken bit again. */
1783 reg = TRANS_CHICKEN2(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1786 I915_WRITE(reg, val);
1787 }
1788 }
1790 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1791 {
1792 u32 val;
1794 val = I915_READ(LPT_TRANSCONF);
1795 val &= ~TRANS_ENABLE;
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 /* wait for PCH transcoder off, transcoder state */
1798 if (intel_wait_for_register(dev_priv,
1799 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1800 50))
1801 DRM_ERROR("Failed to disable PCH transcoder\n");
1803 /* Workaround: clear timing override bit. */
1804 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1805 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1806 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1807 }
1809 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1810 {
1811 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1813 if (HAS_PCH_LPT(dev_priv))
1814 return PIPE_A;
1815 else
1816 return crtc->pipe;
1817 }
1819 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1820 {
1821 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1824 enum pipe pipe = crtc->pipe;
1825 i915_reg_t reg;
1826 u32 val;
1828 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1830 assert_planes_disabled(crtc);
1832 /*
1833 * A pipe without a PLL won't actually be able to drive bits from
1834 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1835 * need the check.
1836 */
1837 if (HAS_GMCH_DISPLAY(dev_priv)) {
1838 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1839 assert_dsi_pll_enabled(dev_priv);
1840 else
1841 assert_pll_enabled(dev_priv, pipe);
1842 } else {
1843 if (new_crtc_state->has_pch_encoder) {
1844 /* if driving the PCH, we need FDI enabled */
1845 assert_fdi_rx_pll_enabled(dev_priv,
1846 intel_crtc_pch_transcoder(crtc));
1847 assert_fdi_tx_pll_enabled(dev_priv,
1848 (enum pipe) cpu_transcoder);
1849 }
1850 /* FIXME: assert CPU port conditions for SNB+ */
1851 }
1853 reg = PIPECONF(cpu_transcoder);
1854 val = I915_READ(reg);
1855 if (val & PIPECONF_ENABLE) {
1856 /* we keep both pipes enabled on 830 */
1857 WARN_ON(!IS_I830(dev_priv));
1858 return;
1859 }
1861 I915_WRITE(reg, val | PIPECONF_ENABLE);
1862 POSTING_READ(reg);
1864 /*
1865 * Until the pipe starts PIPEDSL reads will return a stale value,
1866 * which causes an apparent vblank timestamp jump when PIPEDSL
1867 * resets to its proper value. That also messes up the frame count
1868 * when it's derived from the timestamps. So let's wait for the
1869 * pipe to start properly before we call drm_crtc_vblank_on()
1870 */
1871 if (dev_priv->drm.max_vblank_count == 0)
1872 intel_wait_for_pipe_scanline_moving(crtc);
1873 }
1875 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1876 {
1877 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1879 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1880 enum pipe pipe = crtc->pipe;
1881 i915_reg_t reg;
1882 u32 val;
1884 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1886 /*
1887 * Make sure planes won't keep trying to pump pixels to us,
1888 * or we might hang the display.
1889 */
1890 assert_planes_disabled(crtc);
1892 reg = PIPECONF(cpu_transcoder);
1893 val = I915_READ(reg);
1894 if ((val & PIPECONF_ENABLE) == 0)
1895 return;
1897 /*
1898 * Double wide has implications for planes
1899 * so best keep it disabled when not needed.
1900 */
1901 if (old_crtc_state->double_wide)
1902 val &= ~PIPECONF_DOUBLE_WIDE;
1904 /* Don't disable pipe or pipe PLLs if needed */
1905 if (!IS_I830(dev_priv))
1906 val &= ~PIPECONF_ENABLE;
1908 I915_WRITE(reg, val);
1909 if ((val & PIPECONF_ENABLE) == 0)
1910 intel_wait_for_pipe_off(old_crtc_state);
1911 }
1913 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1914 {
1915 return IS_GEN2(dev_priv) ? 2048 : 4096;
1916 }
1918 static unsigned int
1919 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1920 {
1921 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1922 unsigned int cpp = fb->format->cpp[plane];
1924 switch (fb->modifier) {
1925 case DRM_FORMAT_MOD_LINEAR:
1926 return cpp;
1927 case I915_FORMAT_MOD_X_TILED:
1928 if (IS_GEN2(dev_priv))
1929 return 128;
1930 else
1931 return 512;
1932 case I915_FORMAT_MOD_Y_TILED_CCS:
1933 if (plane == 1)
1934 return 128;
1935 /* fall through */
1936 case I915_FORMAT_MOD_Y_TILED:
1937 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1938 return 128;
1939 else
1940 return 512;
1941 case I915_FORMAT_MOD_Yf_TILED_CCS:
1942 if (plane == 1)
1943 return 128;
1944 /* fall through */
1945 case I915_FORMAT_MOD_Yf_TILED:
1946 switch (cpp) {
1947 case 1:
1948 return 64;
1949 case 2:
1950 case 4:
1951 return 128;
1952 case 8:
1953 case 16:
1954 return 256;
1955 default:
1956 MISSING_CASE(cpp);
1957 return cpp;
1958 }
1959 break;
1960 default:
1961 MISSING_CASE(fb->modifier);
1962 return cpp;
1963 }
1964 }
1966 static unsigned int
1967 intel_tile_height(const struct drm_framebuffer *fb, int plane)
1968 {
1969 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1970 return 1;
1971 else
1972 return intel_tile_size(to_i915(fb->dev)) /
1973 intel_tile_width_bytes(fb, plane);
1974 }
1976 /* Return the tile dimensions in pixel units */
1977 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
1978 unsigned int *tile_width,
1979 unsigned int *tile_height)
1980 {
1981 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
1982 unsigned int cpp = fb->format->cpp[plane];
1984 *tile_width = tile_width_bytes / cpp;
1985 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1986 }
1988 unsigned int
1989 intel_fb_align_height(const struct drm_framebuffer *fb,
1990 int plane, unsigned int height)
1991 {
1992 unsigned int tile_height = intel_tile_height(fb, plane);
1994 return ALIGN(height, tile_height);
1995 }
1997 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1998 {
1999 unsigned int size = 0;
2000 int i;
2002 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2003 size += rot_info->plane[i].width * rot_info->plane[i].height;
2005 return size;
2006 }
2008 static void
2009 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2010 const struct drm_framebuffer *fb,
2011 unsigned int rotation)
2012 {
2013 view->type = I915_GGTT_VIEW_NORMAL;
2014 if (drm_rotation_90_or_270(rotation)) {
2015 view->type = I915_GGTT_VIEW_ROTATED;
2016 view->rotated = to_intel_framebuffer(fb)->rot_info;
2017 }
2018 }
2020 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2021 {
2022 if (IS_I830(dev_priv))
2023 return 16 * 1024;
2024 else if (IS_I85X(dev_priv))
2025 return 256;
2026 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2027 return 32;
2028 else
2029 return 4 * 1024;
2030 }
2032 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2033 {
2034 if (INTEL_GEN(dev_priv) >= 9)
2035 return 256 * 1024;
2036 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2037 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2038 return 128 * 1024;
2039 else if (INTEL_GEN(dev_priv) >= 4)
2040 return 4 * 1024;
2041 else
2042 return 0;
2043 }
2045 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2046 int plane)
2047 {
2048 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2050 /* AUX_DIST needs only 4K alignment */
2051 if (plane == 1)
2052 return 4096;
2054 switch (fb->modifier) {
2055 case DRM_FORMAT_MOD_LINEAR:
2056 return intel_linear_alignment(dev_priv);
2057 case I915_FORMAT_MOD_X_TILED:
2058 if (INTEL_GEN(dev_priv) >= 9)
2059 return 256 * 1024;
2060 return 0;
2061 case I915_FORMAT_MOD_Y_TILED_CCS:
2062 case I915_FORMAT_MOD_Yf_TILED_CCS:
2063 case I915_FORMAT_MOD_Y_TILED:
2064 case I915_FORMAT_MOD_Yf_TILED:
2065 return 1 * 1024 * 1024;
2066 default:
2067 MISSING_CASE(fb->modifier);
2068 return 0;
2069 }
2070 }
2072 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2073 {
2074 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2075 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2077 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2078 }
2080 struct i915_vma *
2081 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2082 unsigned int rotation,
2083 bool uses_fence,
2084 unsigned long *out_flags)
2085 {
2086 struct drm_device *dev = fb->dev;
2087 struct drm_i915_private *dev_priv = to_i915(dev);
2088 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2089 struct i915_ggtt_view view;
2090 struct i915_vma *vma;
2091 unsigned int pinctl;
2092 u32 alignment;
2094 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2096 alignment = intel_surf_alignment(fb, 0);
2098 intel_fill_fb_ggtt_view(&view, fb, rotation);
2100 /* Note that the w/a also requires 64 PTE of padding following the
2101 * bo. We currently fill all unused PTE with the shadow page and so
2102 * we should always have valid PTE following the scanout preventing
2103 * the VT-d warning.
2104 */
2105 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2106 alignment = 256 * 1024;
2108 /*
2109 * Global gtt pte registers are special registers which actually forward
2110 * writes to a chunk of system memory. Which means that there is no risk
2111 * that the register values disappear as soon as we call
2112 * intel_runtime_pm_put(), so it is correct to wrap only the
2113 * pin/unpin/fence and not more.
2114 */
2115 intel_runtime_pm_get(dev_priv);
2117 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2119 pinctl = 0;
2121 /* Valleyview is definitely limited to scanning out the first
2122 * 512MiB. Lets presume this behaviour was inherited from the
2123 * g4x display engine and that all earlier gen are similarly
2124 * limited. Testing suggests that it is a little more
2125 * complicated than this. For example, Cherryview appears quite
2126 * happy to scanout from anywhere within its global aperture.
2127 */
2128 if (HAS_GMCH_DISPLAY(dev_priv))
2129 pinctl |= PIN_MAPPABLE;
2131 vma = i915_gem_object_pin_to_display_plane(obj,
2132 alignment, &view, pinctl);
2133 if (IS_ERR(vma))
2134 goto err;
2136 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2137 int ret;
2139 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2140 * fence, whereas 965+ only requires a fence if using
2141 * framebuffer compression. For simplicity, we always, when
2142 * possible, install a fence as the cost is not that onerous.
2143 *
2144 * If we fail to fence the tiled scanout, then either the
2145 * modeset will reject the change (which is highly unlikely as
2146 * the affected systems, all but one, do not have unmappable
2147 * space) or we will not be able to enable full powersaving
2148 * techniques (also likely not to apply due to various limits
2149 * FBC and the like impose on the size of the buffer, which
2150 * presumably we violated anyway with this unmappable buffer).
2151 * Anyway, it is presumably better to stumble onwards with
2152 * something and try to run the system in a "less than optimal"
2153 * mode that matches the user configuration.
2154 */
2155 ret = i915_vma_pin_fence(vma);
2156 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2157 i915_gem_object_unpin_from_display_plane(vma);
2158 vma = ERR_PTR(ret);
2159 goto err;
2160 }
2162 if (ret == 0 && vma->fence)
2163 *out_flags |= PLANE_HAS_FENCE;
2164 }
2166 i915_vma_get(vma);
2167 err:
2168 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2170 intel_runtime_pm_put(dev_priv);
2171 return vma;
2172 }
2174 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2175 {
2176 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2178 if (flags & PLANE_HAS_FENCE)
2179 i915_vma_unpin_fence(vma);
2180 i915_gem_object_unpin_from_display_plane(vma);
2181 i915_vma_put(vma);
2182 }
2184 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2185 unsigned int rotation)
2186 {
2187 if (drm_rotation_90_or_270(rotation))
2188 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2189 else
2190 return fb->pitches[plane];
2191 }
2193 /*
2194 * Convert the x/y offsets into a linear offset.
2195 * Only valid with 0/180 degree rotation, which is fine since linear
2196 * offset is only used with linear buffers on pre-hsw and tiled buffers
2197 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2198 */
2199 u32 intel_fb_xy_to_linear(int x, int y,
2200 const struct intel_plane_state *state,
2201 int plane)
2202 {
2203 const struct drm_framebuffer *fb = state->base.fb;
2204 unsigned int cpp = fb->format->cpp[plane];
2205 unsigned int pitch = fb->pitches[plane];
2207 return y * pitch + x * cpp;
2208 }
2210 /*
2211 * Add the x/y offsets derived from fb->offsets[] to the user
2212 * specified plane src x/y offsets. The resulting x/y offsets
2213 * specify the start of scanout from the beginning of the gtt mapping.
2214 */
2215 void intel_add_fb_offsets(int *x, int *y,
2216 const struct intel_plane_state *state,
2217 int plane)
2219 {
2220 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2221 unsigned int rotation = state->base.rotation;
2223 if (drm_rotation_90_or_270(rotation)) {
2224 *x += intel_fb->rotated[plane].x;
2225 *y += intel_fb->rotated[plane].y;
2226 } else {
2227 *x += intel_fb->normal[plane].x;
2228 *y += intel_fb->normal[plane].y;
2229 }
2230 }
2232 static u32 __intel_adjust_tile_offset(int *x, int *y,
2233 unsigned int tile_width,
2234 unsigned int tile_height,
2235 unsigned int tile_size,
2236 unsigned int pitch_tiles,
2237 u32 old_offset,
2238 u32 new_offset)
2239 {
2240 unsigned int pitch_pixels = pitch_tiles * tile_width;
2241 unsigned int tiles;
2243 WARN_ON(old_offset & (tile_size - 1));
2244 WARN_ON(new_offset & (tile_size - 1));
2245 WARN_ON(new_offset > old_offset);
2247 tiles = (old_offset - new_offset) / tile_size;
2249 *y += tiles / pitch_tiles * tile_height;
2250 *x += tiles % pitch_tiles * tile_width;
2252 /* minimize x in case it got needlessly big */
2253 *y += *x / pitch_pixels * tile_height;
2254 *x %= pitch_pixels;
2256 return new_offset;
2257 }
2259 static u32 _intel_adjust_tile_offset(int *x, int *y,
2260 const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation,
2262 u32 old_offset, u32 new_offset)
2263 {
2264 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2265 unsigned int cpp = fb->format->cpp[plane];
2266 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2268 WARN_ON(new_offset > old_offset);
2270 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2271 unsigned int tile_size, tile_width, tile_height;
2272 unsigned int pitch_tiles;
2274 tile_size = intel_tile_size(dev_priv);
2275 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2277 if (drm_rotation_90_or_270(rotation)) {
2278 pitch_tiles = pitch / tile_height;
2279 swap(tile_width, tile_height);
2280 } else {
2281 pitch_tiles = pitch / (tile_width * cpp);
2282 }
2284 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2285 tile_size, pitch_tiles,
2286 old_offset, new_offset);
2287 } else {
2288 old_offset += *y * pitch + *x * cpp;
2290 *y = (old_offset - new_offset) / pitch;
2291 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2292 }
2294 return new_offset;
2295 }
2297 /*
2298 * Adjust the tile offset by moving the difference into
2299 * the x/y offsets.
2300 */
2301 static u32 intel_adjust_tile_offset(int *x, int *y,
2302 const struct intel_plane_state *state, int plane,
2303 u32 old_offset, u32 new_offset)
2304 {
2305 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2306 state->base.rotation,
2307 old_offset, new_offset);
2308 }
2310 /*
2311 * Computes the linear offset to the base tile and adjusts
2312 * x, y. bytes per pixel is assumed to be a power-of-two.
2313 *
2314 * In the 90/270 rotated case, x and y are assumed
2315 * to be already rotated to match the rotated GTT view, and
2316 * pitch is the tile_height aligned framebuffer height.
2317 *
2318 * This function is used when computing the derived information
2319 * under intel_framebuffer, so using any of that information
2320 * here is not allowed. Anything under drm_framebuffer can be
2321 * used. This is why the user has to pass in the pitch since it
2322 * is specified in the rotated orientation.
2323 */
2324 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2325 int *x, int *y,
2326 const struct drm_framebuffer *fb, int plane,
2327 unsigned int pitch,
2328 unsigned int rotation,
2329 u32 alignment)
2330 {
2331 uint64_t fb_modifier = fb->modifier;
2332 unsigned int cpp = fb->format->cpp[plane];
2333 u32 offset, offset_aligned;
2335 if (alignment)
2336 alignment--;
2338 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2339 unsigned int tile_size, tile_width, tile_height;
2340 unsigned int tile_rows, tiles, pitch_tiles;
2342 tile_size = intel_tile_size(dev_priv);
2343 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2345 if (drm_rotation_90_or_270(rotation)) {
2346 pitch_tiles = pitch / tile_height;
2347 swap(tile_width, tile_height);
2348 } else {
2349 pitch_tiles = pitch / (tile_width * cpp);
2350 }
2352 tile_rows = *y / tile_height;
2353 *y %= tile_height;
2355 tiles = *x / tile_width;
2356 *x %= tile_width;
2358 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2359 offset_aligned = offset & ~alignment;
2361 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2362 tile_size, pitch_tiles,
2363 offset, offset_aligned);
2364 } else {
2365 offset = *y * pitch + *x * cpp;
2366 offset_aligned = offset & ~alignment;
2368 *y = (offset & alignment) / pitch;
2369 *x = ((offset & alignment) - *y * pitch) / cpp;
2370 }
2372 return offset_aligned;
2373 }
2375 u32 intel_compute_tile_offset(int *x, int *y,
2376 const struct intel_plane_state *state,
2377 int plane)
2378 {
2379 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2380 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2381 const struct drm_framebuffer *fb = state->base.fb;
2382 unsigned int rotation = state->base.rotation;
2383 int pitch = intel_fb_pitch(fb, plane, rotation);
2384 u32 alignment;
2386 if (intel_plane->id == PLANE_CURSOR)
2387 alignment = intel_cursor_alignment(dev_priv);
2388 else
2389 alignment = intel_surf_alignment(fb, plane);
2391 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2392 rotation, alignment);
2393 }
2395 /* Convert the fb->offset[] into x/y offsets */
2396 static int intel_fb_offset_to_xy(int *x, int *y,
2397 const struct drm_framebuffer *fb, int plane)
2398 {
2399 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2401 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2402 fb->offsets[plane] % intel_tile_size(dev_priv))
2403 return -EINVAL;
2405 *x = 0;
2406 *y = 0;
2408 _intel_adjust_tile_offset(x, y,
2409 fb, plane, DRM_MODE_ROTATE_0,
2410 fb->offsets[plane], 0);
2412 return 0;
2413 }
2415 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2416 {
2417 switch (fb_modifier) {
2418 case I915_FORMAT_MOD_X_TILED:
2419 return I915_TILING_X;
2420 case I915_FORMAT_MOD_Y_TILED:
2421 case I915_FORMAT_MOD_Y_TILED_CCS:
2422 return I915_TILING_Y;
2423 default:
2424 return I915_TILING_NONE;
2425 }
2426 }
2428 /*
2429 * From the Sky Lake PRM:
2430 * "The Color Control Surface (CCS) contains the compression status of
2431 * the cache-line pairs. The compression state of the cache-line pair
2432 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2433 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2434 * cache-line-pairs. CCS is always Y tiled."
2435 *
2436 * Since cache line pairs refers to horizontally adjacent cache lines,
2437 * each cache line in the CCS corresponds to an area of 32x16 cache
2438 * lines on the main surface. Since each pixel is 4 bytes, this gives
2439 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2440 * main surface.
2441 */
2442 static const struct drm_format_info ccs_formats[] = {
2443 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2444 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2445 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2446 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2447 };
2449 static const struct drm_format_info *
2450 lookup_format_info(const struct drm_format_info formats[],
2451 int num_formats, u32 format)
2452 {
2453 int i;
2455 for (i = 0; i < num_formats; i++) {
2456 if (formats[i].format == format)
2457 return &formats[i];
2458 }
2460 return NULL;
2461 }
2463 static const struct drm_format_info *
2464 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2465 {
2466 switch (cmd->modifier[0]) {
2467 case I915_FORMAT_MOD_Y_TILED_CCS:
2468 case I915_FORMAT_MOD_Yf_TILED_CCS:
2469 return lookup_format_info(ccs_formats,
2470 ARRAY_SIZE(ccs_formats),
2471 cmd->pixel_format);
2472 default:
2473 return NULL;
2474 }
2475 }
2477 static int
2478 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2479 struct drm_framebuffer *fb)
2480 {
2481 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2482 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2483 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2484 u32 gtt_offset_rotated = 0;
2485 unsigned int max_size = 0;
2486 int i, num_planes = fb->format->num_planes;
2487 unsigned int tile_size = intel_tile_size(dev_priv);
2489 for (i = 0; i < num_planes; i++) {
2490 unsigned int width, height;
2491 unsigned int cpp, size;
2492 u32 offset;
2493 int x, y;
2494 int ret;
2496 cpp = fb->format->cpp[i];
2497 width = drm_framebuffer_plane_width(fb->width, fb, i);
2498 height = drm_framebuffer_plane_height(fb->height, fb, i);
2500 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2501 if (ret) {
2502 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2503 i, fb->offsets[i]);
2504 return ret;
2505 }
2507 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2508 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2509 int hsub = fb->format->hsub;
2510 int vsub = fb->format->vsub;
2511 int tile_width, tile_height;
2512 int main_x, main_y;
2513 int ccs_x, ccs_y;
2515 intel_tile_dims(fb, i, &tile_width, &tile_height);
2516 tile_width *= hsub;
2517 tile_height *= vsub;
2519 ccs_x = (x * hsub) % tile_width;
2520 ccs_y = (y * vsub) % tile_height;
2521 main_x = intel_fb->normal[0].x % tile_width;
2522 main_y = intel_fb->normal[0].y % tile_height;
2524 /*
2525 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2526 * x/y offsets must match between CCS and the main surface.
2527 */
2528 if (main_x != ccs_x || main_y != ccs_y) {
2529 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2530 main_x, main_y,
2531 ccs_x, ccs_y,
2532 intel_fb->normal[0].x,
2533 intel_fb->normal[0].y,
2534 x, y);
2535 return -EINVAL;
2536 }
2537 }
2539 /*
2540 * The fence (if used) is aligned to the start of the object
2541 * so having the framebuffer wrap around across the edge of the
2542 * fenced region doesn't really work. We have no API to configure
2543 * the fence start offset within the object (nor could we probably
2544 * on gen2/3). So it's just easier if we just require that the
2545 * fb layout agrees with the fence layout. We already check that the
2546 * fb stride matches the fence stride elsewhere.
2547 */
2548 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2549 (x + width) * cpp > fb->pitches[i]) {
2550 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2551 i, fb->offsets[i]);
2552 return -EINVAL;
2553 }
2555 /*
2556 * First pixel of the framebuffer from
2557 * the start of the normal gtt mapping.
2558 */
2559 intel_fb->normal[i].x = x;
2560 intel_fb->normal[i].y = y;
2562 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2563 fb, i, fb->pitches[i],
2564 DRM_MODE_ROTATE_0, tile_size);
2565 offset /= tile_size;
2567 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2568 unsigned int tile_width, tile_height;
2569 unsigned int pitch_tiles;
2570 struct drm_rect r;
2572 intel_tile_dims(fb, i, &tile_width, &tile_height);
2574 rot_info->plane[i].offset = offset;
2575 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2576 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2577 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2579 intel_fb->rotated[i].pitch =
2580 rot_info->plane[i].height * tile_height;
2582 /* how many tiles does this plane need */
2583 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2584 /*
2585 * If the plane isn't horizontally tile aligned,
2586 * we need one more tile.
2587 */
2588 if (x != 0)
2589 size++;
2591 /* rotate the x/y offsets to match the GTT view */
2592 r.x1 = x;
2593 r.y1 = y;
2594 r.x2 = x + width;
2595 r.y2 = y + height;
2596 drm_rect_rotate(&r,
2597 rot_info->plane[i].width * tile_width,
2598 rot_info->plane[i].height * tile_height,
2599 DRM_MODE_ROTATE_270);
2600 x = r.x1;
2601 y = r.y1;
2603 /* rotate the tile dimensions to match the GTT view */
2604 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2605 swap(tile_width, tile_height);
2607 /*
2608 * We only keep the x/y offsets, so push all of the
2609 * gtt offset into the x/y offsets.
2610 */
2611 __intel_adjust_tile_offset(&x, &y,
2612 tile_width, tile_height,
2613 tile_size, pitch_tiles,
2614 gtt_offset_rotated * tile_size, 0);
2616 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2618 /*
2619 * First pixel of the framebuffer from
2620 * the start of the rotated gtt mapping.
2621 */
2622 intel_fb->rotated[i].x = x;
2623 intel_fb->rotated[i].y = y;
2624 } else {
2625 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2626 x * cpp, tile_size);
2627 }
2629 /* how many tiles in total needed in the bo */
2630 max_size = max(max_size, offset + size);
2631 }
2633 if (max_size * tile_size > obj->base.size) {
2634 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2635 max_size * tile_size, obj->base.size);
2636 return -EINVAL;
2637 }
2639 return 0;
2640 }
2642 static int i9xx_format_to_fourcc(int format)
2643 {
2644 switch (format) {
2645 case DISPPLANE_8BPP:
2646 return DRM_FORMAT_C8;
2647 case DISPPLANE_BGRX555:
2648 return DRM_FORMAT_XRGB1555;
2649 case DISPPLANE_BGRX565:
2650 return DRM_FORMAT_RGB565;
2651 default:
2652 case DISPPLANE_BGRX888:
2653 return DRM_FORMAT_XRGB8888;
2654 case DISPPLANE_RGBX888:
2655 return DRM_FORMAT_XBGR8888;
2656 case DISPPLANE_BGRX101010:
2657 return DRM_FORMAT_XRGB2101010;
2658 case DISPPLANE_RGBX101010:
2659 return DRM_FORMAT_XBGR2101010;
2660 }
2661 }
2663 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2664 {
2665 switch (format) {
2666 case PLANE_CTL_FORMAT_RGB_565:
2667 return DRM_FORMAT_RGB565;
2668 case PLANE_CTL_FORMAT_NV12:
2669 return DRM_FORMAT_NV12;
2670 default:
2671 case PLANE_CTL_FORMAT_XRGB_8888:
2672 if (rgb_order) {
2673 if (alpha)
2674 return DRM_FORMAT_ABGR8888;
2675 else
2676 return DRM_FORMAT_XBGR8888;
2677 } else {
2678 if (alpha)
2679 return DRM_FORMAT_ARGB8888;
2680 else
2681 return DRM_FORMAT_XRGB8888;
2682 }
2683 case PLANE_CTL_FORMAT_XRGB_2101010:
2684 if (rgb_order)
2685 return DRM_FORMAT_XBGR2101010;
2686 else
2687 return DRM_FORMAT_XRGB2101010;
2688 }
2689 }
2691 static bool
2692 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2693 struct intel_initial_plane_config *plane_config)
2694 {
2695 struct drm_device *dev = crtc->base.dev;
2696 struct drm_i915_private *dev_priv = to_i915(dev);
2697 struct drm_i915_gem_object *obj = NULL;
2698 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2699 struct drm_framebuffer *fb = &plane_config->fb->base;
2700 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2701 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2702 PAGE_SIZE);
2704 size_aligned -= base_aligned;
2706 if (plane_config->size == 0)
2707 return false;
2709 /* If the FB is too big, just don't use it since fbdev is not very
2710 * important and we should probably use that space with FBC or other
2711 * features. */
2712 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2713 return false;
2715 mutex_lock(&dev->struct_mutex);
2716 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2717 base_aligned,
2718 base_aligned,
2719 size_aligned);
2720 mutex_unlock(&dev->struct_mutex);
2721 if (!obj)
2722 return false;
2724 if (plane_config->tiling == I915_TILING_X)
2725 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2727 mode_cmd.pixel_format = fb->format->format;
2728 mode_cmd.width = fb->width;
2729 mode_cmd.height = fb->height;
2730 mode_cmd.pitches[0] = fb->pitches[0];
2731 mode_cmd.modifier[0] = fb->modifier;
2732 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2734 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2735 DRM_DEBUG_KMS("intel fb init failed\n");
2736 goto out_unref_obj;
2737 }
2740 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2741 return true;
2743 out_unref_obj:
2744 i915_gem_object_put(obj);
2745 return false;
2746 }
2748 static void
2749 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2750 struct intel_plane_state *plane_state,
2751 bool visible)
2752 {
2753 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2755 plane_state->base.visible = visible;
2757 /* FIXME pre-g4x don't work like this */
2758 if (visible) {
2759 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2760 crtc_state->active_planes |= BIT(plane->id);
2761 } else {
2762 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2763 crtc_state->active_planes &= ~BIT(plane->id);
2764 }
2766 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2767 crtc_state->base.crtc->name,
2768 crtc_state->active_planes);
2769 }
2771 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2772 struct intel_plane *plane)
2773 {
2774 struct intel_crtc_state *crtc_state =
2775 to_intel_crtc_state(crtc->base.state);
2776 struct intel_plane_state *plane_state =
2777 to_intel_plane_state(plane->base.state);
2779 intel_set_plane_visible(crtc_state, plane_state, false);
2781 if (plane->id == PLANE_PRIMARY)
2782 intel_pre_disable_primary_noatomic(&crtc->base);
2784 trace_intel_disable_plane(&plane->base, crtc);
2785 plane->disable_plane(plane, crtc);
2786 }
2788 static void
2789 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2790 struct intel_initial_plane_config *plane_config)
2791 {
2792 struct drm_device *dev = intel_crtc->base.dev;
2793 struct drm_i915_private *dev_priv = to_i915(dev);
2794 struct drm_crtc *c;
2795 struct drm_i915_gem_object *obj;
2796 struct drm_plane *primary = intel_crtc->base.primary;
2797 struct drm_plane_state *plane_state = primary->state;
2798 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2799 struct intel_plane *intel_plane = to_intel_plane(primary);
2800 struct intel_plane_state *intel_state =
2801 to_intel_plane_state(plane_state);
2802 struct drm_framebuffer *fb;
2804 if (!plane_config->fb)
2805 return;
2807 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2808 fb = &plane_config->fb->base;
2809 goto valid_fb;
2810 }
2812 kfree(plane_config->fb);
2814 /*
2815 * Failed to alloc the obj, check to see if we should share
2816 * an fb with another CRTC instead
2817 */
2818 for_each_crtc(dev, c) {
2819 struct intel_plane_state *state;
2821 if (c == &intel_crtc->base)
2822 continue;
2824 if (!to_intel_crtc(c)->active)
2825 continue;
2827 state = to_intel_plane_state(c->primary->state);
2828 if (!state->vma)
2829 continue;
2831 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2832 fb = state->base.fb;
2833 drm_framebuffer_get(fb);
2834 goto valid_fb;
2835 }
2836 }
2838 /*
2839 * We've failed to reconstruct the BIOS FB. Current display state
2840 * indicates that the primary plane is visible, but has a NULL FB,
2841 * which will lead to problems later if we don't fix it up. The
2842 * simplest solution is to just disable the primary plane now and
2843 * pretend the BIOS never had it enabled.
2844 */
2845 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2847 return;
2849 valid_fb:
2850 mutex_lock(&dev->struct_mutex);
2851 intel_state->vma =
2852 intel_pin_and_fence_fb_obj(fb,
2853 primary->state->rotation,
2854 intel_plane_uses_fence(intel_state),
2855 &intel_state->flags);
2856 mutex_unlock(&dev->struct_mutex);
2857 if (IS_ERR(intel_state->vma)) {
2858 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2859 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2861 intel_state->vma = NULL;
2862 drm_framebuffer_put(fb);
2863 return;
2864 }
2866 obj = intel_fb_obj(fb);
2867 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2869 plane_state->src_x = 0;
2870 plane_state->src_y = 0;
2871 plane_state->src_w = fb->width << 16;
2872 plane_state->src_h = fb->height << 16;
2874 plane_state->crtc_x = 0;
2875 plane_state->crtc_y = 0;
2876 plane_state->crtc_w = fb->width;
2877 plane_state->crtc_h = fb->height;
2879 intel_state->base.src = drm_plane_state_src(plane_state);
2880 intel_state->base.dst = drm_plane_state_dest(plane_state);
2882 if (i915_gem_object_is_tiled(obj))
2883 dev_priv->preserve_bios_swizzle = true;
2885 plane_state->fb = fb;
2886 plane_state->crtc = &intel_crtc->base;
2888 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2889 to_intel_plane_state(plane_state),
2890 true);
2892 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2893 &obj->frontbuffer_bits);
2894 }
2896 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2897 unsigned int rotation)
2898 {
2899 int cpp = fb->format->cpp[plane];
2901 switch (fb->modifier) {
2902 case DRM_FORMAT_MOD_LINEAR:
2903 case I915_FORMAT_MOD_X_TILED:
2904 switch (cpp) {
2905 case 8:
2906 return 4096;
2907 case 4:
2908 case 2:
2909 case 1:
2910 return 8192;
2911 default:
2912 MISSING_CASE(cpp);
2913 break;
2914 }
2915 break;
2916 case I915_FORMAT_MOD_Y_TILED_CCS:
2917 case I915_FORMAT_MOD_Yf_TILED_CCS:
2918 /* FIXME AUX plane? */
2919 case I915_FORMAT_MOD_Y_TILED:
2920 case I915_FORMAT_MOD_Yf_TILED:
2921 switch (cpp) {
2922 case 8:
2923 return 2048;
2924 case 4:
2925 return 4096;
2926 case 2:
2927 case 1:
2928 return 8192;
2929 default:
2930 MISSING_CASE(cpp);
2931 break;
2932 }
2933 break;
2934 default:
2935 MISSING_CASE(fb->modifier);
2936 }
2938 return 2048;
2939 }
2941 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2942 int main_x, int main_y, u32 main_offset)
2943 {
2944 const struct drm_framebuffer *fb = plane_state->base.fb;
2945 int hsub = fb->format->hsub;
2946 int vsub = fb->format->vsub;
2947 int aux_x = plane_state->aux.x;
2948 int aux_y = plane_state->aux.y;
2949 u32 aux_offset = plane_state->aux.offset;
2950 u32 alignment = intel_surf_alignment(fb, 1);
2952 while (aux_offset >= main_offset && aux_y <= main_y) {
2953 int x, y;
2955 if (aux_x == main_x && aux_y == main_y)
2956 break;
2958 if (aux_offset == 0)
2959 break;
2961 x = aux_x / hsub;
2962 y = aux_y / vsub;
2963 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2964 aux_offset, aux_offset - alignment);
2965 aux_x = x * hsub + aux_x % hsub;
2966 aux_y = y * vsub + aux_y % vsub;
2967 }
2969 if (aux_x != main_x || aux_y != main_y)
2970 return false;
2972 plane_state->aux.offset = aux_offset;
2973 plane_state->aux.x = aux_x;
2974 plane_state->aux.y = aux_y;
2976 return true;
2977 }
2979 static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
2980 struct intel_plane_state *plane_state)
2981 {
2982 struct drm_i915_private *dev_priv =
2983 to_i915(plane_state->base.plane->dev);
2984 const struct drm_framebuffer *fb = plane_state->base.fb;
2985 unsigned int rotation = plane_state->base.rotation;
2986 int x = plane_state->base.src.x1 >> 16;
2987 int y = plane_state->base.src.y1 >> 16;
2988 int w = drm_rect_width(&plane_state->base.src) >> 16;
2989 int h = drm_rect_height(&plane_state->base.src) >> 16;
2990 int dst_x = plane_state->base.dst.x1;
2991 int dst_w = drm_rect_width(&plane_state->base.dst);
2992 int pipe_src_w = crtc_state->pipe_src_w;
2993 int max_width = skl_max_plane_width(fb, 0, rotation);
2994 int max_height = 4096;
2995 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2997 if (w > max_width || h > max_height) {
2998 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2999 w, h, max_width, max_height);
3000 return -EINVAL;
3001 }
3003 /*
3004 * Display WA #1175: cnl,glk
3005 * Planes other than the cursor may cause FIFO underflow and display
3006 * corruption if starting less than 4 pixels from the right edge of
3007 * the screen.
3008 * Besides the above WA fix the similar problem, where planes other
3009 * than the cursor ending less than 4 pixels from the left edge of the
3010 * screen may cause FIFO underflow and display corruption.
3011 */
3012 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3013 (dst_x + dst_w < 4 || dst_x > pipe_src_w - 4)) {
3014 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
3015 dst_x + dst_w < 4 ? "end" : "start",
3016 dst_x + dst_w < 4 ? dst_x + dst_w : dst_x,
3017 4, pipe_src_w - 4);
3018 return -ERANGE;
3019 }
3021 intel_add_fb_offsets(&x, &y, plane_state, 0);
3022 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3023 alignment = intel_surf_alignment(fb, 0);
3025 /*
3026 * AUX surface offset is specified as the distance from the
3027 * main surface offset, and it must be non-negative. Make
3028 * sure that is what we will get.
3029 */
3030 if (offset > aux_offset)
3031 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3032 offset, aux_offset & ~(alignment - 1));
3034 /*
3035 * When using an X-tiled surface, the plane blows up
3036 * if the x offset + width exceed the stride.
3037 *
3038 * TODO: linear and Y-tiled seem fine, Yf untested,
3039 */
3040 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3041 int cpp = fb->format->cpp[0];
3043 while ((x + w) * cpp > fb->pitches[0]) {
3044 if (offset == 0) {
3045 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3046 return -EINVAL;
3047 }
3049 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3050 offset, offset - alignment);
3051 }
3052 }
3054 /*
3055 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3056 * they match with the main surface x/y offsets.
3057 */
3058 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3059 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3060 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3061 if (offset == 0)
3062 break;
3064 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3065 offset, offset - alignment);
3066 }
3068 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3069 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3070 return -EINVAL;
3071 }
3072 }
3074 plane_state->main.offset = offset;
3075 plane_state->main.x = x;
3076 plane_state->main.y = y;
3078 return 0;
3079 }
3081 static int
3082 skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
3083 struct intel_plane_state *plane_state)
3084 {
3085 /* Display WA #1106 */
3086 if (plane_state->base.rotation !=
3087 (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90) &&
3088 plane_state->base.rotation != DRM_MODE_ROTATE_270)
3089 return 0;
3091 /*
3092 * src coordinates are rotated here.
3093 * We check height but report it as width
3094 */
3095 if (((drm_rect_height(&plane_state->base.src) >> 16) % 4) != 0) {
3096 DRM_DEBUG_KMS("src width must be multiple "
3097 "of 4 for rotated NV12\n");
3098 return -EINVAL;
3099 }
3101 return 0;
3102 }
3104 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3105 {
3106 const struct drm_framebuffer *fb = plane_state->base.fb;
3107 unsigned int rotation = plane_state->base.rotation;
3108 int max_width = skl_max_plane_width(fb, 1, rotation);
3109 int max_height = 4096;
3110 int x = plane_state->base.src.x1 >> 17;
3111 int y = plane_state->base.src.y1 >> 17;
3112 int w = drm_rect_width(&plane_state->base.src) >> 17;
3113 int h = drm_rect_height(&plane_state->base.src) >> 17;
3114 u32 offset;
3116 intel_add_fb_offsets(&x, &y, plane_state, 1);
3117 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3119 /* FIXME not quite sure how/if these apply to the chroma plane */
3120 if (w > max_width || h > max_height) {
3121 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3122 w, h, max_width, max_height);
3123 return -EINVAL;
3124 }
3126 plane_state->aux.offset = offset;
3127 plane_state->aux.x = x;
3128 plane_state->aux.y = y;
3130 return 0;
3131 }
3133 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3134 {
3135 const struct drm_framebuffer *fb = plane_state->base.fb;
3136 int src_x = plane_state->base.src.x1 >> 16;
3137 int src_y = plane_state->base.src.y1 >> 16;
3138 int hsub = fb->format->hsub;
3139 int vsub = fb->format->vsub;
3140 int x = src_x / hsub;
3141 int y = src_y / vsub;
3142 u32 offset;
3144 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3145 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3146 plane_state->base.rotation);
3147 return -EINVAL;
3148 }
3150 intel_add_fb_offsets(&x, &y, plane_state, 1);
3151 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3153 plane_state->aux.offset = offset;
3154 plane_state->aux.x = x * hsub + src_x % hsub;
3155 plane_state->aux.y = y * vsub + src_y % vsub;
3157 return 0;
3158 }
3160 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
3161 struct intel_plane_state *plane_state)
3162 {
3163 const struct drm_framebuffer *fb = plane_state->base.fb;
3164 unsigned int rotation = plane_state->base.rotation;
3165 int ret;
3167 if (rotation & DRM_MODE_REFLECT_X &&
3168 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
3169 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
3170 return -EINVAL;
3171 }
3173 if (!plane_state->base.visible)
3174 return 0;
3176 /* Rotate src coordinates to match rotated GTT view */
3177 if (drm_rotation_90_or_270(rotation))
3178 drm_rect_rotate(&plane_state->base.src,
3179 fb->width << 16, fb->height << 16,
3180 DRM_MODE_ROTATE_270);
3182 /*
3183 * Handle the AUX surface first since
3184 * the main surface setup depends on it.
3185 */
3186 if (fb->format->format == DRM_FORMAT_NV12) {
3187 ret = skl_check_nv12_surface(crtc_state, plane_state);
3188 if (ret)
3189 return ret;
3190 ret = skl_check_nv12_aux_surface(plane_state);
3191 if (ret)
3192 return ret;
3193 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3194 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3195 ret = skl_check_ccs_aux_surface(plane_state);
3196 if (ret)
3197 return ret;
3198 } else {
3199 plane_state->aux.offset = ~0xfff;
3200 plane_state->aux.x = 0;
3201 plane_state->aux.y = 0;
3202 }
3204 ret = skl_check_main_surface(crtc_state, plane_state);
3205 if (ret)
3206 return ret;
3208 return 0;
3209 }
3211 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3212 const struct intel_plane_state *plane_state)
3213 {
3214 struct drm_i915_private *dev_priv =
3215 to_i915(plane_state->base.plane->dev);
3216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3217 const struct drm_framebuffer *fb = plane_state->base.fb;
3218 unsigned int rotation = plane_state->base.rotation;
3219 u32 dspcntr;
3221 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3223 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3224 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3225 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3227 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3228 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3230 if (INTEL_GEN(dev_priv) < 5)
3231 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3233 switch (fb->format->format) {
3234 case DRM_FORMAT_C8:
3235 dspcntr |= DISPPLANE_8BPP;
3236 break;
3237 case DRM_FORMAT_XRGB1555:
3238 dspcntr |= DISPPLANE_BGRX555;
3239 break;
3240 case DRM_FORMAT_RGB565:
3241 dspcntr |= DISPPLANE_BGRX565;
3242 break;
3243 case DRM_FORMAT_XRGB8888:
3244 dspcntr |= DISPPLANE_BGRX888;
3245 break;
3246 case DRM_FORMAT_XBGR8888:
3247 dspcntr |= DISPPLANE_RGBX888;
3248 break;
3249 case DRM_FORMAT_XRGB2101010:
3250 dspcntr |= DISPPLANE_BGRX101010;
3251 break;
3252 case DRM_FORMAT_XBGR2101010:
3253 dspcntr |= DISPPLANE_RGBX101010;
3254 break;
3255 default:
3256 MISSING_CASE(fb->format->format);
3257 return 0;
3258 }
3260 if (INTEL_GEN(dev_priv) >= 4 &&
3261 fb->modifier == I915_FORMAT_MOD_X_TILED)
3262 dspcntr |= DISPPLANE_TILED;
3264 if (rotation & DRM_MODE_ROTATE_180)
3265 dspcntr |= DISPPLANE_ROTATE_180;
3267 if (rotation & DRM_MODE_REFLECT_X)
3268 dspcntr |= DISPPLANE_MIRROR;
3270 return dspcntr;
3271 }
3273 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3274 {
3275 struct drm_i915_private *dev_priv =
3276 to_i915(plane_state->base.plane->dev);
3277 int src_x = plane_state->base.src.x1 >> 16;
3278 int src_y = plane_state->base.src.y1 >> 16;
3279 u32 offset;
3281 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3283 if (INTEL_GEN(dev_priv) >= 4)
3284 offset = intel_compute_tile_offset(&src_x, &src_y,
3285 plane_state, 0);
3286 else
3287 offset = 0;
3289 /* HSW/BDW do this automagically in hardware */
3290 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3291 unsigned int rotation = plane_state->base.rotation;
3292 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3293 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3295 if (rotation & DRM_MODE_ROTATE_180) {
3296 src_x += src_w - 1;
3297 src_y += src_h - 1;
3298 } else if (rotation & DRM_MODE_REFLECT_X) {
3299 src_x += src_w - 1;
3300 }
3301 }
3303 plane_state->main.offset = offset;
3304 plane_state->main.x = src_x;
3305 plane_state->main.y = src_y;
3307 return 0;
3308 }
3310 static void i9xx_update_plane(struct intel_plane *plane,
3311 const struct intel_crtc_state *crtc_state,
3312 const struct intel_plane_state *plane_state)
3313 {
3314 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3315 const struct drm_framebuffer *fb = plane_state->base.fb;
3316 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3317 u32 linear_offset;
3318 u32 dspcntr = plane_state->ctl;
3319 i915_reg_t reg = DSPCNTR(i9xx_plane);
3320 int x = plane_state->main.x;
3321 int y = plane_state->main.y;
3322 unsigned long irqflags;
3323 u32 dspaddr_offset;
3325 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3327 if (INTEL_GEN(dev_priv) >= 4)
3328 dspaddr_offset = plane_state->main.offset;
3329 else
3330 dspaddr_offset = linear_offset;
3332 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3334 if (INTEL_GEN(dev_priv) < 4) {
3335 /* pipesrc and dspsize control the size that is scaled from,
3336 * which should always be the user's requested size.
3337 */
3338 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3339 ((crtc_state->pipe_src_h - 1) << 16) |
3340 (crtc_state->pipe_src_w - 1));
3341 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3342 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3343 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3344 ((crtc_state->pipe_src_h - 1) << 16) |
3345 (crtc_state->pipe_src_w - 1));
3346 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3347 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3348 }
3350 I915_WRITE_FW(reg, dspcntr);
3352 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
3353 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3354 I915_WRITE_FW(DSPSURF(i9xx_plane),
3355 intel_plane_ggtt_offset(plane_state) +
3356 dspaddr_offset);
3357 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3358 } else if (INTEL_GEN(dev_priv) >= 4) {
3359 I915_WRITE_FW(DSPSURF(i9xx_plane),
3360 intel_plane_ggtt_offset(plane_state) +
3361 dspaddr_offset);
3362 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3363 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3364 } else {
3365 I915_WRITE_FW(DSPADDR(i9xx_plane),
3366 intel_plane_ggtt_offset(plane_state) +
3367 dspaddr_offset);
3368 }
3369 POSTING_READ_FW(reg);
3371 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3372 }
3374 static void i9xx_disable_plane(struct intel_plane *plane,
3375 struct intel_crtc *crtc)
3376 {
3377 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3378 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3379 unsigned long irqflags;
3381 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3383 I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3384 if (INTEL_GEN(dev_priv) >= 4)
3385 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3386 else
3387 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3388 POSTING_READ_FW(DSPCNTR(i9xx_plane));
3390 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3391 }
3393 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3394 enum pipe *pipe)
3395 {
3396 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3397 enum intel_display_power_domain power_domain;
3398 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3399 bool ret;
3400 u32 val;
3402 /*
3403 * Not 100% correct for planes that can move between pipes,
3404 * but that's only the case for gen2-4 which don't have any
3405 * display power wells.
3406 */
3407 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3408 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3409 return false;
3411 val = I915_READ(DSPCNTR(i9xx_plane));
3413 ret = val & DISPLAY_PLANE_ENABLE;
3415 if (INTEL_GEN(dev_priv) >= 5)
3416 *pipe = plane->pipe;
3417 else
3418 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3419 DISPPLANE_SEL_PIPE_SHIFT;
3421 intel_display_power_put(dev_priv, power_domain);
3423 return ret;
3424 }
3426 static u32
3427 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3428 {
3429 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3430 return 64;
3431 else
3432 return intel_tile_width_bytes(fb, plane);
3433 }
3435 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3436 {
3437 struct drm_device *dev = intel_crtc->base.dev;
3438 struct drm_i915_private *dev_priv = to_i915(dev);
3440 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3441 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3442 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3443 }
3445 /*
3446 * This function detaches (aka. unbinds) unused scalers in hardware
3447 */
3448 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3449 {
3450 struct intel_crtc_scaler_state *scaler_state;
3451 int i;
3453 scaler_state = &intel_crtc->config->scaler_state;
3455 /* loop through and disable scalers that aren't in use */
3456 for (i = 0; i < intel_crtc->num_scalers; i++) {
3457 if (!scaler_state->scalers[i].in_use)
3458 skl_detach_scaler(intel_crtc, i);
3459 }
3460 }
3462 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3463 unsigned int rotation)
3464 {
3465 u32 stride;
3467 if (plane >= fb->format->num_planes)
3468 return 0;
3470 stride = intel_fb_pitch(fb, plane, rotation);
3472 /*
3473 * The stride is either expressed as a multiple of 64 bytes chunks for
3474 * linear buffers or in number of tiles for tiled buffers.
3475 */
3476 if (drm_rotation_90_or_270(rotation))
3477 stride /= intel_tile_height(fb, plane);
3478 else
3479 stride /= intel_fb_stride_alignment(fb, plane);
3481 return stride;
3482 }
3484 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3485 {
3486 switch (pixel_format) {
3487 case DRM_FORMAT_C8:
3488 return PLANE_CTL_FORMAT_INDEXED;
3489 case DRM_FORMAT_RGB565:
3490 return PLANE_CTL_FORMAT_RGB_565;
3491 case DRM_FORMAT_XBGR8888:
3492 case DRM_FORMAT_ABGR8888:
3493 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3494 case DRM_FORMAT_XRGB8888:
3495 case DRM_FORMAT_ARGB8888:
3496 return PLANE_CTL_FORMAT_XRGB_8888;
3497 case DRM_FORMAT_XRGB2101010:
3498 return PLANE_CTL_FORMAT_XRGB_2101010;
3499 case DRM_FORMAT_XBGR2101010:
3500 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3501 case DRM_FORMAT_YUYV:
3502 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3503 case DRM_FORMAT_YVYU:
3504 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3505 case DRM_FORMAT_UYVY:
3506 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3507 case DRM_FORMAT_VYUY:
3508 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3509 case DRM_FORMAT_NV12:
3510 return PLANE_CTL_FORMAT_NV12;
3511 default:
3512 MISSING_CASE(pixel_format);
3513 }
3515 return 0;
3516 }
3518 /*
3519 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3520 * to be already pre-multiplied. We need to add a knob (or a different
3521 * DRM_FORMAT) for user-space to configure that.
3522 */
3523 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3524 {
3525 switch (pixel_format) {
3526 case DRM_FORMAT_ABGR8888:
3527 case DRM_FORMAT_ARGB8888:
3528 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3529 default:
3530 return PLANE_CTL_ALPHA_DISABLE;
3531 }
3532 }
3534 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3535 {
3536 switch (pixel_format) {
3537 case DRM_FORMAT_ABGR8888:
3538 case DRM_FORMAT_ARGB8888:
3539 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3540 default:
3541 return PLANE_COLOR_ALPHA_DISABLE;
3542 }
3543 }
3545 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3546 {
3547 switch (fb_modifier) {
3548 case DRM_FORMAT_MOD_LINEAR:
3549 break;
3550 case I915_FORMAT_MOD_X_TILED:
3551 return PLANE_CTL_TILED_X;
3552 case I915_FORMAT_MOD_Y_TILED:
3553 return PLANE_CTL_TILED_Y;
3554 case I915_FORMAT_MOD_Y_TILED_CCS:
3555 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3556 case I915_FORMAT_MOD_Yf_TILED:
3557 return PLANE_CTL_TILED_YF;
3558 case I915_FORMAT_MOD_Yf_TILED_CCS:
3559 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3560 default:
3561 MISSING_CASE(fb_modifier);
3562 }
3564 return 0;
3565 }
3567 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3568 {
3569 switch (rotate) {
3570 case DRM_MODE_ROTATE_0:
3571 break;
3572 /*
3573 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3574 * while i915 HW rotation is clockwise, thats why this swapping.
3575 */
3576 case DRM_MODE_ROTATE_90:
3577 return PLANE_CTL_ROTATE_270;
3578 case DRM_MODE_ROTATE_180:
3579 return PLANE_CTL_ROTATE_180;
3580 case DRM_MODE_ROTATE_270:
3581 return PLANE_CTL_ROTATE_90;
3582 default:
3583 MISSING_CASE(rotate);
3584 }
3586 return 0;
3587 }
3589 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3590 {
3591 switch (reflect) {
3592 case 0:
3593 break;
3594 case DRM_MODE_REFLECT_X:
3595 return PLANE_CTL_FLIP_HORIZONTAL;
3596 case DRM_MODE_REFLECT_Y:
3597 default:
3598 MISSING_CASE(reflect);
3599 }
3601 return 0;
3602 }
3604 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3605 const struct intel_plane_state *plane_state)
3606 {
3607 struct drm_i915_private *dev_priv =
3608 to_i915(plane_state->base.plane->dev);
3609 const struct drm_framebuffer *fb = plane_state->base.fb;
3610 unsigned int rotation = plane_state->base.rotation;
3611 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3612 u32 plane_ctl;
3614 plane_ctl = PLANE_CTL_ENABLE;
3616 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3617 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3618 plane_ctl |=
3619 PLANE_CTL_PIPE_GAMMA_ENABLE |
3620 PLANE_CTL_PIPE_CSC_ENABLE |
3621 PLANE_CTL_PLANE_GAMMA_DISABLE;
3623 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3624 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3626 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3627 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3628 }
3630 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3631 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3632 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3634 if (INTEL_GEN(dev_priv) >= 10)
3635 plane_ctl |= cnl_plane_ctl_flip(rotation &
3636 DRM_MODE_REFLECT_MASK);
3638 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3639 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3640 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3641 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3643 return plane_ctl;
3644 }
3646 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3647 const struct intel_plane_state *plane_state)
3648 {
3649 struct drm_i915_private *dev_priv =
3650 to_i915(plane_state->base.plane->dev);
3651 const struct drm_framebuffer *fb = plane_state->base.fb;
3652 u32 plane_color_ctl = 0;
3654 if (INTEL_GEN(dev_priv) < 11) {
3655 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3656 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3657 }
3658 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3659 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3661 if (fb->format->is_yuv) {
3662 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3663 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3664 else
3665 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3667 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3668 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3669 }
3671 return plane_color_ctl;
3672 }
3674 static int
3675 __intel_display_resume(struct drm_device *dev,
3676 struct drm_atomic_state *state,
3677 struct drm_modeset_acquire_ctx *ctx)
3678 {
3679 struct drm_crtc_state *crtc_state;
3680 struct drm_crtc *crtc;
3681 int i, ret;
3683 intel_modeset_setup_hw_state(dev, ctx);
3684 i915_redisable_vga(to_i915(dev));
3686 if (!state)
3687 return 0;
3689 /*
3690 * We've duplicated the state, pointers to the old state are invalid.
3691 *
3692 * Don't attempt to use the old state until we commit the duplicated state.
3693 */
3694 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3695 /*
3696 * Force recalculation even if we restore
3697 * current state. With fast modeset this may not result
3698 * in a modeset when the state is compatible.
3699 */
3700 crtc_state->mode_changed = true;
3701 }
3703 /* ignore any reset values/BIOS leftovers in the WM registers */
3704 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3705 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3707 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3709 WARN_ON(ret == -EDEADLK);
3710 return ret;
3711 }
3713 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3714 {
3715 return intel_has_gpu_reset(dev_priv) &&
3716 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3717 }
3719 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3720 {
3721 struct drm_device *dev = &dev_priv->drm;
3722 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3723 struct drm_atomic_state *state;
3724 int ret;
3726 /* reset doesn't touch the display */
3727 if (!i915_modparams.force_reset_modeset_test &&
3728 !gpu_reset_clobbers_display(dev_priv))
3729 return;
3731 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3732 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3733 wake_up_all(&dev_priv->gpu_error.wait_queue);
3735 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3736 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3737 i915_gem_set_wedged(dev_priv);
3738 }
3740 /*
3741 * Need mode_config.mutex so that we don't
3742 * trample ongoing ->detect() and whatnot.
3743 */
3744 mutex_lock(&dev->mode_config.mutex);
3745 drm_modeset_acquire_init(ctx, 0);
3746 while (1) {
3747 ret = drm_modeset_lock_all_ctx(dev, ctx);
3748 if (ret != -EDEADLK)
3749 break;
3751 drm_modeset_backoff(ctx);
3752 }
3753 /*
3754 * Disabling the crtcs gracefully seems nicer. Also the
3755 * g33 docs say we should at least disable all the planes.
3756 */
3757 state = drm_atomic_helper_duplicate_state(dev, ctx);
3758 if (IS_ERR(state)) {
3759 ret = PTR_ERR(state);
3760 DRM_ERROR("Duplicating state failed with %i\n", ret);
3761 return;
3762 }
3764 ret = drm_atomic_helper_disable_all(dev, ctx);
3765 if (ret) {
3766 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3767 drm_atomic_state_put(state);
3768 return;
3769 }
3771 dev_priv->modeset_restore_state = state;
3772 state->acquire_ctx = ctx;
3773 }
3775 void intel_finish_reset(struct drm_i915_private *dev_priv)
3776 {
3777 struct drm_device *dev = &dev_priv->drm;
3778 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3779 struct drm_atomic_state *state;
3780 int ret;
3782 /* reset doesn't touch the display */
3783 if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3784 return;
3786 state = fetch_and_zero(&dev_priv->modeset_restore_state);
3787 if (!state)
3788 goto unlock;
3790 /* reset doesn't touch the display */
3791 if (!gpu_reset_clobbers_display(dev_priv)) {
3792 /* for testing only restore the display */
3793 ret = __intel_display_resume(dev, state, ctx);
3794 if (ret)
3795 DRM_ERROR("Restoring old state failed with %i\n", ret);
3796 } else {
3797 /*
3798 * The display has been reset as well,
3799 * so need a full re-initialization.
3800 */
3801 intel_runtime_pm_disable_interrupts(dev_priv);
3802 intel_runtime_pm_enable_interrupts(dev_priv);
3804 intel_pps_unlock_regs_wa(dev_priv);
3805 intel_modeset_init_hw(dev);
3806 intel_init_clock_gating(dev_priv);
3808 spin_lock_irq(&dev_priv->irq_lock);
3809 if (dev_priv->display.hpd_irq_setup)
3810 dev_priv->display.hpd_irq_setup(dev_priv);
3811 spin_unlock_irq(&dev_priv->irq_lock);
3813 ret = __intel_display_resume(dev, state, ctx);
3814 if (ret)
3815 DRM_ERROR("Restoring old state failed with %i\n", ret);
3817 intel_hpd_init(dev_priv);
3818 }
3820 drm_atomic_state_put(state);
3821 unlock:
3822 drm_modeset_drop_locks(ctx);
3823 drm_modeset_acquire_fini(ctx);
3824 mutex_unlock(&dev->mode_config.mutex);
3826 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3827 }
3829 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3830 const struct intel_crtc_state *new_crtc_state)
3831 {
3832 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3833 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3835 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3836 crtc->base.mode = new_crtc_state->base.mode;
3838 /*
3839 * Update pipe size and adjust fitter if needed: the reason for this is
3840 * that in compute_mode_changes we check the native mode (not the pfit
3841 * mode) to see if we can flip rather than do a full mode set. In the
3842 * fastboot case, we'll flip, but if we don't update the pipesrc and
3843 * pfit state, we'll end up with a big fb scanned out into the wrong
3844 * sized surface.
3845 */
3847 I915_WRITE(PIPESRC(crtc->pipe),
3848 ((new_crtc_state->pipe_src_w - 1) << 16) |
3849 (new_crtc_state->pipe_src_h - 1));
3851 /* on skylake this is done by detaching scalers */
3852 if (INTEL_GEN(dev_priv) >= 9) {
3853 skl_detach_scalers(crtc);
3855 if (new_crtc_state->pch_pfit.enabled)
3856 skylake_pfit_enable(crtc);
3857 } else if (HAS_PCH_SPLIT(dev_priv)) {
3858 if (new_crtc_state->pch_pfit.enabled)
3859 ironlake_pfit_enable(crtc);
3860 else if (old_crtc_state->pch_pfit.enabled)
3861 ironlake_pfit_disable(crtc, true);
3862 }
3863 }
3865 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3866 {
3867 struct drm_device *dev = crtc->base.dev;
3868 struct drm_i915_private *dev_priv = to_i915(dev);
3869 int pipe = crtc->pipe;
3870 i915_reg_t reg;
3871 u32 temp;
3873 /* enable normal train */
3874 reg = FDI_TX_CTL(pipe);
3875 temp = I915_READ(reg);
3876 if (IS_IVYBRIDGE(dev_priv)) {
3877 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3878 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3879 } else {
3880 temp &= ~FDI_LINK_TRAIN_NONE;
3881 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3882 }
3883 I915_WRITE(reg, temp);
3885 reg = FDI_RX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 if (HAS_PCH_CPT(dev_priv)) {
3888 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3889 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3890 } else {
3891 temp &= ~FDI_LINK_TRAIN_NONE;
3892 temp |= FDI_LINK_TRAIN_NONE;
3893 }
3894 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3896 /* wait one idle pattern time */
3897 POSTING_READ(reg);
3898 udelay(1000);
3900 /* IVB wants error correction enabled */
3901 if (IS_IVYBRIDGE(dev_priv))
3902 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3903 FDI_FE_ERRC_ENABLE);
3904 }
3906 /* The FDI link training functions for ILK/Ibexpeak. */
3907 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3908 const struct intel_crtc_state *crtc_state)
3909 {
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = to_i915(dev);
3912 int pipe = crtc->pipe;
3913 i915_reg_t reg;
3914 u32 temp, tries;
3916 /* FDI needs bits from pipe first */
3917 assert_pipe_enabled(dev_priv, pipe);
3919 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3920 for train result */
3921 reg = FDI_RX_IMR(pipe);
3922 temp = I915_READ(reg);
3923 temp &= ~FDI_RX_SYMBOL_LOCK;
3924 temp &= ~FDI_RX_BIT_LOCK;
3925 I915_WRITE(reg, temp);
3926 I915_READ(reg);
3927 udelay(150);
3929 /* enable CPU FDI TX and PCH FDI RX */
3930 reg = FDI_TX_CTL(pipe);
3931 temp = I915_READ(reg);
3932 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3933 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3934 temp &= ~FDI_LINK_TRAIN_NONE;
3935 temp |= FDI_LINK_TRAIN_PATTERN_1;
3936 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3938 reg = FDI_RX_CTL(pipe);
3939 temp = I915_READ(reg);
3940 temp &= ~FDI_LINK_TRAIN_NONE;
3941 temp |= FDI_LINK_TRAIN_PATTERN_1;
3942 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3944 POSTING_READ(reg);
3945 udelay(150);
3947 /* Ironlake workaround, enable clock pointer after FDI enable*/
3948 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3949 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3950 FDI_RX_PHASE_SYNC_POINTER_EN);
3952 reg = FDI_RX_IIR(pipe);
3953 for (tries = 0; tries < 5; tries++) {
3954 temp = I915_READ(reg);
3955 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3957 if ((temp & FDI_RX_BIT_LOCK)) {
3958 DRM_DEBUG_KMS("FDI train 1 done.\n");
3959 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3960 break;
3961 }
3962 }
3963 if (tries == 5)
3964 DRM_ERROR("FDI train 1 fail!\n");
3966 /* Train 2 */
3967 reg = FDI_TX_CTL(pipe);
3968 temp = I915_READ(reg);
3969 temp &= ~FDI_LINK_TRAIN_NONE;
3970 temp |= FDI_LINK_TRAIN_PATTERN_2;
3971 I915_WRITE(reg, temp);
3973 reg = FDI_RX_CTL(pipe);
3974 temp = I915_READ(reg);
3975 temp &= ~FDI_LINK_TRAIN_NONE;
3976 temp |= FDI_LINK_TRAIN_PATTERN_2;
3977 I915_WRITE(reg, temp);
3979 POSTING_READ(reg);
3980 udelay(150);
3982 reg = FDI_RX_IIR(pipe);
3983 for (tries = 0; tries < 5; tries++) {
3984 temp = I915_READ(reg);
3985 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3987 if (temp & FDI_RX_SYMBOL_LOCK) {
3988 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3989 DRM_DEBUG_KMS("FDI train 2 done.\n");
3990 break;
3991 }
3992 }
3993 if (tries == 5)
3994 DRM_ERROR("FDI train 2 fail!\n");
3996 DRM_DEBUG_KMS("FDI train done\n");
3998 }
4000 static const int snb_b_fdi_train_param[] = {
4001 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4002 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4003 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4004 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4005 };
4007 /* The FDI link training functions for SNB/Cougarpoint. */
4008 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4009 const struct intel_crtc_state *crtc_state)
4010 {
4011 struct drm_device *dev = crtc->base.dev;
4012 struct drm_i915_private *dev_priv = to_i915(dev);
4013 int pipe = crtc->pipe;
4014 i915_reg_t reg;
4015 u32 temp, i, retry;
4017 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4018 for train result */
4019 reg = FDI_RX_IMR(pipe);
4020 temp = I915_READ(reg);
4021 temp &= ~FDI_RX_SYMBOL_LOCK;
4022 temp &= ~FDI_RX_BIT_LOCK;
4023 I915_WRITE(reg, temp);
4025 POSTING_READ(reg);
4026 udelay(150);
4028 /* enable CPU FDI TX and PCH FDI RX */
4029 reg = FDI_TX_CTL(pipe);
4030 temp = I915_READ(reg);
4031 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4032 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4033 temp &= ~FDI_LINK_TRAIN_NONE;
4034 temp |= FDI_LINK_TRAIN_PATTERN_1;
4035 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4036 /* SNB-B */
4037 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4038 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4040 I915_WRITE(FDI_RX_MISC(pipe),
4041 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4043 reg = FDI_RX_CTL(pipe);
4044 temp = I915_READ(reg);
4045 if (HAS_PCH_CPT(dev_priv)) {
4046 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4047 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4048 } else {
4049 temp &= ~FDI_LINK_TRAIN_NONE;
4050 temp |= FDI_LINK_TRAIN_PATTERN_1;
4051 }
4052 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4054 POSTING_READ(reg);
4055 udelay(150);
4057 for (i = 0; i < 4; i++) {
4058 reg = FDI_TX_CTL(pipe);
4059 temp = I915_READ(reg);
4060 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4061 temp |= snb_b_fdi_train_param[i];
4062 I915_WRITE(reg, temp);
4064 POSTING_READ(reg);
4065 udelay(500);
4067 for (retry = 0; retry < 5; retry++) {
4068 reg = FDI_RX_IIR(pipe);
4069 temp = I915_READ(reg);
4070 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4071 if (temp & FDI_RX_BIT_LOCK) {
4072 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4073 DRM_DEBUG_KMS("FDI train 1 done.\n");
4074 break;
4075 }
4076 udelay(50);
4077 }
4078 if (retry < 5)
4079 break;
4080 }
4081 if (i == 4)
4082 DRM_ERROR("FDI train 1 fail!\n");
4084 /* Train 2 */
4085 reg = FDI_TX_CTL(pipe);
4086 temp = I915_READ(reg);
4087 temp &= ~FDI_LINK_TRAIN_NONE;
4088 temp |= FDI_LINK_TRAIN_PATTERN_2;
4089 if (IS_GEN6(dev_priv)) {
4090 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4091 /* SNB-B */
4092 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4093 }
4094 I915_WRITE(reg, temp);
4096 reg = FDI_RX_CTL(pipe);
4097 temp = I915_READ(reg);
4098 if (HAS_PCH_CPT(dev_priv)) {
4099 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4100 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4101 } else {
4102 temp &= ~FDI_LINK_TRAIN_NONE;
4103 temp |= FDI_LINK_TRAIN_PATTERN_2;
4104 }
4105 I915_WRITE(reg, temp);
4107 POSTING_READ(reg);
4108 udelay(150);
4110 for (i = 0; i < 4; i++) {
4111 reg = FDI_TX_CTL(pipe);
4112 temp = I915_READ(reg);
4113 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4114 temp |= snb_b_fdi_train_param[i];
4115 I915_WRITE(reg, temp);
4117 POSTING_READ(reg);
4118 udelay(500);
4120 for (retry = 0; retry < 5; retry++) {
4121 reg = FDI_RX_IIR(pipe);
4122 temp = I915_READ(reg);
4123 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4124 if (temp & FDI_RX_SYMBOL_LOCK) {
4125 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4126 DRM_DEBUG_KMS("FDI train 2 done.\n");
4127 break;
4128 }
4129 udelay(50);
4130 }
4131 if (retry < 5)
4132 break;
4133 }
4134 if (i == 4)
4135 DRM_ERROR("FDI train 2 fail!\n");
4137 DRM_DEBUG_KMS("FDI train done.\n");
4138 }
4140 /* Manual link training for Ivy Bridge A0 parts */
4141 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4142 const struct intel_crtc_state *crtc_state)
4143 {
4144 struct drm_device *dev = crtc->base.dev;
4145 struct drm_i915_private *dev_priv = to_i915(dev);
4146 int pipe = crtc->pipe;
4147 i915_reg_t reg;
4148 u32 temp, i, j;
4150 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4151 for train result */
4152 reg = FDI_RX_IMR(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~FDI_RX_SYMBOL_LOCK;
4155 temp &= ~FDI_RX_BIT_LOCK;
4156 I915_WRITE(reg, temp);
4158 POSTING_READ(reg);
4159 udelay(150);
4161 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4162 I915_READ(FDI_RX_IIR(pipe)));
4164 /* Try each vswing and preemphasis setting twice before moving on */
4165 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4166 /* disable first in case we need to retry */
4167 reg = FDI_TX_CTL(pipe);
4168 temp = I915_READ(reg);
4169 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4170 temp &= ~FDI_TX_ENABLE;
4171 I915_WRITE(reg, temp);
4173 reg = FDI_RX_CTL(pipe);
4174 temp = I915_READ(reg);
4175 temp &= ~FDI_LINK_TRAIN_AUTO;
4176 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4177 temp &= ~FDI_RX_ENABLE;
4178 I915_WRITE(reg, temp);
4180 /* enable CPU FDI TX and PCH FDI RX */
4181 reg = FDI_TX_CTL(pipe);
4182 temp = I915_READ(reg);
4183 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4184 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4185 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4186 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4187 temp |= snb_b_fdi_train_param[j/2];
4188 temp |= FDI_COMPOSITE_SYNC;
4189 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4191 I915_WRITE(FDI_RX_MISC(pipe),
4192 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4194 reg = FDI_RX_CTL(pipe);
4195 temp = I915_READ(reg);
4196 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4197 temp |= FDI_COMPOSITE_SYNC;
4198 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4200 POSTING_READ(reg);
4201 udelay(1); /* should be 0.5us */
4203 for (i = 0; i < 4; i++) {
4204 reg = FDI_RX_IIR(pipe);
4205 temp = I915_READ(reg);
4206 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4208 if (temp & FDI_RX_BIT_LOCK ||
4209 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4210 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4211 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4212 i);
4213 break;
4214 }
4215 udelay(1); /* should be 0.5us */
4216 }
4217 if (i == 4) {
4218 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4219 continue;
4220 }
4222 /* Train 2 */
4223 reg = FDI_TX_CTL(pipe);
4224 temp = I915_READ(reg);
4225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4226 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4227 I915_WRITE(reg, temp);
4229 reg = FDI_RX_CTL(pipe);
4230 temp = I915_READ(reg);
4231 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4232 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4233 I915_WRITE(reg, temp);
4235 POSTING_READ(reg);
4236 udelay(2); /* should be 1.5us */
4238 for (i = 0; i < 4; i++) {
4239 reg = FDI_RX_IIR(pipe);
4240 temp = I915_READ(reg);
4241 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4243 if (temp & FDI_RX_SYMBOL_LOCK ||
4244 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4245 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4246 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4247 i);
4248 goto train_done;
4249 }
4250 udelay(2); /* should be 1.5us */
4251 }
4252 if (i == 4)
4253 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4254 }
4256 train_done:
4257 DRM_DEBUG_KMS("FDI train done.\n");
4258 }
4260 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4261 {
4262 struct drm_device *dev = intel_crtc->base.dev;
4263 struct drm_i915_private *dev_priv = to_i915(dev);
4264 int pipe = intel_crtc->pipe;
4265 i915_reg_t reg;
4266 u32 temp;
4268 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4269 reg = FDI_RX_CTL(pipe);
4270 temp = I915_READ(reg);
4271 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4272 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4273 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4274 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4276 POSTING_READ(reg);
4277 udelay(200);
4279 /* Switch from Rawclk to PCDclk */
4280 temp = I915_READ(reg);
4281 I915_WRITE(reg, temp | FDI_PCDCLK);
4283 POSTING_READ(reg);
4284 udelay(200);
4286 /* Enable CPU FDI TX PLL, always on for Ironlake */
4287 reg = FDI_TX_CTL(pipe);
4288 temp = I915_READ(reg);
4289 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4290 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4292 POSTING_READ(reg);
4293 udelay(100);
4294 }
4295 }
4297 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4298 {
4299 struct drm_device *dev = intel_crtc->base.dev;
4300 struct drm_i915_private *dev_priv = to_i915(dev);
4301 int pipe = intel_crtc->pipe;
4302 i915_reg_t reg;
4303 u32 temp;
4305 /* Switch from PCDclk to Rawclk */
4306 reg = FDI_RX_CTL(pipe);
4307 temp = I915_READ(reg);
4308 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4310 /* Disable CPU FDI TX PLL */
4311 reg = FDI_TX_CTL(pipe);
4312 temp = I915_READ(reg);
4313 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4315 POSTING_READ(reg);
4316 udelay(100);
4318 reg = FDI_RX_CTL(pipe);
4319 temp = I915_READ(reg);
4320 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4322 /* Wait for the clocks to turn off. */
4323 POSTING_READ(reg);
4324 udelay(100);
4325 }
4327 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4328 {
4329 struct drm_device *dev = crtc->dev;
4330 struct drm_i915_private *dev_priv = to_i915(dev);
4331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4332 int pipe = intel_crtc->pipe;
4333 i915_reg_t reg;
4334 u32 temp;
4336 /* disable CPU FDI tx and PCH FDI rx */
4337 reg = FDI_TX_CTL(pipe);
4338 temp = I915_READ(reg);
4339 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4340 POSTING_READ(reg);
4342 reg = FDI_RX_CTL(pipe);
4343 temp = I915_READ(reg);
4344 temp &= ~(0x7 << 16);
4345 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4346 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4348 POSTING_READ(reg);
4349 udelay(100);
4351 /* Ironlake workaround, disable clock pointer after downing FDI */
4352 if (HAS_PCH_IBX(dev_priv))
4353 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4355 /* still set train pattern 1 */
4356 reg = FDI_TX_CTL(pipe);
4357 temp = I915_READ(reg);
4358 temp &= ~FDI_LINK_TRAIN_NONE;
4359 temp |= FDI_LINK_TRAIN_PATTERN_1;
4360 I915_WRITE(reg, temp);
4362 reg = FDI_RX_CTL(pipe);
4363 temp = I915_READ(reg);
4364 if (HAS_PCH_CPT(dev_priv)) {
4365 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4366 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4367 } else {
4368 temp &= ~FDI_LINK_TRAIN_NONE;
4369 temp |= FDI_LINK_TRAIN_PATTERN_1;
4370 }
4371 /* BPC in FDI rx is consistent with that in PIPECONF */
4372 temp &= ~(0x07 << 16);
4373 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4374 I915_WRITE(reg, temp);
4376 POSTING_READ(reg);
4377 udelay(100);
4378 }
4380 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4381 {
4382 struct drm_crtc *crtc;
4383 bool cleanup_done;
4385 drm_for_each_crtc(crtc, &dev_priv->drm) {
4386 struct drm_crtc_commit *commit;
4387 spin_lock(&crtc->commit_lock);
4388 commit = list_first_entry_or_null(&crtc->commit_list,
4389 struct drm_crtc_commit, commit_entry);
4390 cleanup_done = commit ?
4391 try_wait_for_completion(&commit->cleanup_done) : true;
4392 spin_unlock(&crtc->commit_lock);
4394 if (cleanup_done)
4395 continue;
4397 drm_crtc_wait_one_vblank(crtc);
4399 return true;
4400 }
4402 return false;
4403 }
4405 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4406 {
4407 u32 temp;
4409 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4411 mutex_lock(&dev_priv->sb_lock);
4413 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4414 temp |= SBI_SSCCTL_DISABLE;
4415 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4417 mutex_unlock(&dev_priv->sb_lock);
4418 }
4420 /* Program iCLKIP clock to the desired frequency */
4421 static void lpt_program_iclkip(struct intel_crtc *crtc)
4422 {
4423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4424 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4425 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4426 u32 temp;
4428 lpt_disable_iclkip(dev_priv);
4430 /* The iCLK virtual clock root frequency is in MHz,
4431 * but the adjusted_mode->crtc_clock in in KHz. To get the
4432 * divisors, it is necessary to divide one by another, so we
4433 * convert the virtual clock precision to KHz here for higher
4434 * precision.
4435 */
4436 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4437 u32 iclk_virtual_root_freq = 172800 * 1000;
4438 u32 iclk_pi_range = 64;
4439 u32 desired_divisor;
4441 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4442 clock << auxdiv);
4443 divsel = (desired_divisor / iclk_pi_range) - 2;
4444 phaseinc = desired_divisor % iclk_pi_range;
4446 /*
4447 * Near 20MHz is a corner case which is
4448 * out of range for the 7-bit divisor
4449 */
4450 if (divsel <= 0x7f)
4451 break;
4452 }
4454 /* This should not happen with any sane values */
4455 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4456 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4457 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4458 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4460 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4461 clock,
4462 auxdiv,
4463 divsel,
4464 phasedir,
4465 phaseinc);
4467 mutex_lock(&dev_priv->sb_lock);
4469 /* Program SSCDIVINTPHASE6 */
4470 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4471 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4472 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4473 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4474 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4475 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4476 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4477 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4479 /* Program SSCAUXDIV */
4480 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4481 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4482 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4483 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4485 /* Enable modulator and associated divider */
4486 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4487 temp &= ~SBI_SSCCTL_DISABLE;
4488 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4490 mutex_unlock(&dev_priv->sb_lock);
4492 /* Wait for initialization time */
4493 udelay(24);
4495 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4496 }
4498 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4499 {
4500 u32 divsel, phaseinc, auxdiv;
4501 u32 iclk_virtual_root_freq = 172800 * 1000;
4502 u32 iclk_pi_range = 64;
4503 u32 desired_divisor;
4504 u32 temp;
4506 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4507 return 0;
4509 mutex_lock(&dev_priv->sb_lock);
4511 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4512 if (temp & SBI_SSCCTL_DISABLE) {
4513 mutex_unlock(&dev_priv->sb_lock);
4514 return 0;
4515 }
4517 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4518 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4519 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4520 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4521 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4523 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4524 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4525 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4527 mutex_unlock(&dev_priv->sb_lock);
4529 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4531 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4532 desired_divisor << auxdiv);
4533 }
4535 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4536 enum pipe pch_transcoder)
4537 {
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = to_i915(dev);
4540 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4542 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4543 I915_READ(HTOTAL(cpu_transcoder)));
4544 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4545 I915_READ(HBLANK(cpu_transcoder)));
4546 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4547 I915_READ(HSYNC(cpu_transcoder)));
4549 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4550 I915_READ(VTOTAL(cpu_transcoder)));
4551 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4552 I915_READ(VBLANK(cpu_transcoder)));
4553 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4554 I915_READ(VSYNC(cpu_transcoder)));
4555 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4556 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4557 }
4559 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4560 {
4561 struct drm_i915_private *dev_priv = to_i915(dev);
4562 uint32_t temp;
4564 temp = I915_READ(SOUTH_CHICKEN1);
4565 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4566 return;
4568 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4571 temp &= ~FDI_BC_BIFURCATION_SELECT;
4572 if (enable)
4573 temp |= FDI_BC_BIFURCATION_SELECT;
4575 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4576 I915_WRITE(SOUTH_CHICKEN1, temp);
4577 POSTING_READ(SOUTH_CHICKEN1);
4578 }
4580 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4581 {
4582 struct drm_device *dev = intel_crtc->base.dev;
4584 switch (intel_crtc->pipe) {
4585 case PIPE_A:
4586 break;
4587 case PIPE_B:
4588 if (intel_crtc->config->fdi_lanes > 2)
4589 cpt_set_fdi_bc_bifurcation(dev, false);
4590 else
4591 cpt_set_fdi_bc_bifurcation(dev, true);
4593 break;
4594 case PIPE_C:
4595 cpt_set_fdi_bc_bifurcation(dev, true);
4597 break;
4598 default:
4599 BUG();
4600 }
4601 }
4603 /*
4604 * Finds the encoder associated with the given CRTC. This can only be
4605 * used when we know that the CRTC isn't feeding multiple encoders!
4606 */
4607 static struct intel_encoder *
4608 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4609 const struct intel_crtc_state *crtc_state)
4610 {
4611 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4612 const struct drm_connector_state *connector_state;
4613 const struct drm_connector *connector;
4614 struct intel_encoder *encoder = NULL;
4615 int num_encoders = 0;
4616 int i;
4618 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4619 if (connector_state->crtc != &crtc->base)
4620 continue;
4622 encoder = to_intel_encoder(connector_state->best_encoder);
4623 num_encoders++;
4624 }
4626 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4627 num_encoders, pipe_name(crtc->pipe));
4629 return encoder;
4630 }
4632 /*
4633 * Enable PCH resources required for PCH ports:
4634 * - PCH PLLs
4635 * - FDI training & RX/TX
4636 * - update transcoder timings
4637 * - DP transcoding bits
4638 * - transcoder
4639 */
4640 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4641 const struct intel_crtc_state *crtc_state)
4642 {
4643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4644 struct drm_device *dev = crtc->base.dev;
4645 struct drm_i915_private *dev_priv = to_i915(dev);
4646 int pipe = crtc->pipe;
4647 u32 temp;
4649 assert_pch_transcoder_disabled(dev_priv, pipe);
4651 if (IS_IVYBRIDGE(dev_priv))
4652 ivybridge_update_fdi_bc_bifurcation(crtc);
4654 /* Write the TU size bits before fdi link training, so that error
4655 * detection works. */
4656 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4657 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4659 /* For PCH output, training FDI link */
4660 dev_priv->display.fdi_link_train(crtc, crtc_state);
4662 /* We need to program the right clock selection before writing the pixel
4663 * mutliplier into the DPLL. */
4664 if (HAS_PCH_CPT(dev_priv)) {
4665 u32 sel;
4667 temp = I915_READ(PCH_DPLL_SEL);
4668 temp |= TRANS_DPLL_ENABLE(pipe);
4669 sel = TRANS_DPLLB_SEL(pipe);
4670 if (crtc_state->shared_dpll ==
4671 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4672 temp |= sel;
4673 else
4674 temp &= ~sel;
4675 I915_WRITE(PCH_DPLL_SEL, temp);
4676 }
4678 /* XXX: pch pll's can be enabled any time before we enable the PCH
4679 * transcoder, and we actually should do this to not upset any PCH
4680 * transcoder that already use the clock when we share it.
4681 *
4682 * Note that enable_shared_dpll tries to do the right thing, but
4683 * get_shared_dpll unconditionally resets the pll - we need that to have
4684 * the right LVDS enable sequence. */
4685 intel_enable_shared_dpll(crtc);
4687 /* set transcoder timing, panel must allow it */
4688 assert_panel_unlocked(dev_priv, pipe);
4689 ironlake_pch_transcoder_set_timings(crtc, pipe);
4691 intel_fdi_normal_train(crtc);
4693 /* For PCH DP, enable TRANS_DP_CTL */
4694 if (HAS_PCH_CPT(dev_priv) &&
4695 intel_crtc_has_dp_encoder(crtc_state)) {
4696 const struct drm_display_mode *adjusted_mode =
4697 &crtc_state->base.adjusted_mode;
4698 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4699 i915_reg_t reg = TRANS_DP_CTL(pipe);
4700 enum port port;
4702 temp = I915_READ(reg);
4703 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4704 TRANS_DP_SYNC_MASK |
4705 TRANS_DP_BPC_MASK);
4706 temp |= TRANS_DP_OUTPUT_ENABLE;
4707 temp |= bpc << 9; /* same format but at 11:9 */
4709 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4710 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4711 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4712 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4714 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4715 WARN_ON(port < PORT_B || port > PORT_D);
4716 temp |= TRANS_DP_PORT_SEL(port);
4718 I915_WRITE(reg, temp);
4719 }
4721 ironlake_enable_pch_transcoder(dev_priv, pipe);
4722 }
4724 static void lpt_pch_enable(const struct intel_atomic_state *state,
4725 const struct intel_crtc_state *crtc_state)
4726 {
4727 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4728 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4729 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4731 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4733 lpt_program_iclkip(crtc);
4735 /* Set transcoder timing. */
4736 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4738 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4739 }
4741 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4742 {
4743 struct drm_i915_private *dev_priv = to_i915(dev);
4744 i915_reg_t dslreg = PIPEDSL(pipe);
4745 u32 temp;
4747 temp = I915_READ(dslreg);
4748 udelay(500);
4749 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4750 if (wait_for(I915_READ(dslreg) != temp, 5))
4751 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4752 }
4753 }
4755 /*
4756 * The hardware phase 0.0 refers to the center of the pixel.
4757 * We want to start from the top/left edge which is phase
4758 * -0.5. That matches how the hardware calculates the scaling
4759 * factors (from top-left of the first pixel to bottom-right
4760 * of the last pixel, as opposed to the pixel centers).
4761 *
4762 * For 4:2:0 subsampled chroma planes we obviously have to
4763 * adjust that so that the chroma sample position lands in
4764 * the right spot.
4765 *
4766 * Note that for packed YCbCr 4:2:2 formats there is no way to
4767 * control chroma siting. The hardware simply replicates the
4768 * chroma samples for both of the luma samples, and thus we don't
4769 * actually get the expected MPEG2 chroma siting convention :(
4770 * The same behaviour is observed on pre-SKL platforms as well.
4771 */
4772 u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
4773 {
4774 int phase = -0x8000;
4775 u16 trip = 0;
4777 if (chroma_cosited)
4778 phase += (sub - 1) * 0x8000 / sub;
4780 if (phase < 0)
4781 phase = 0x10000 + phase;
4782 else
4783 trip = PS_PHASE_TRIP;
4785 return ((phase >> 2) & PS_PHASE_MASK) | trip;
4786 }
4788 static int
4789 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4790 unsigned int scaler_user, int *scaler_id,
4791 int src_w, int src_h, int dst_w, int dst_h,
4792 bool plane_scaler_check,
4793 uint32_t pixel_format)
4794 {
4795 struct intel_crtc_scaler_state *scaler_state =
4796 &crtc_state->scaler_state;
4797 struct intel_crtc *intel_crtc =
4798 to_intel_crtc(crtc_state->base.crtc);
4799 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4800 const struct drm_display_mode *adjusted_mode =
4801 &crtc_state->base.adjusted_mode;
4802 int need_scaling;
4804 /*
4805 * Src coordinates are already rotated by 270 degrees for
4806 * the 90/270 degree plane rotation cases (to match the
4807 * GTT mapping), hence no need to account for rotation here.
4808 */
4809 need_scaling = src_w != dst_w || src_h != dst_h;
4811 if (plane_scaler_check)
4812 if (pixel_format == DRM_FORMAT_NV12)
4813 need_scaling = true;
4815 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4816 need_scaling = true;
4818 /*
4819 * Scaling/fitting not supported in IF-ID mode in GEN9+
4820 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4821 * Once NV12 is enabled, handle it here while allocating scaler
4822 * for NV12.
4823 */
4824 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4825 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4826 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4827 return -EINVAL;
4828 }
4830 /*
4831 * if plane is being disabled or scaler is no more required or force detach
4832 * - free scaler binded to this plane/crtc
4833 * - in order to do this, update crtc->scaler_usage
4834 *
4835 * Here scaler state in crtc_state is set free so that
4836 * scaler can be assigned to other user. Actual register
4837 * update to free the scaler is done in plane/panel-fit programming.
4838 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4839 */
4840 if (force_detach || !need_scaling) {
4841 if (*scaler_id >= 0) {
4842 scaler_state->scaler_users &= ~(1 << scaler_user);
4843 scaler_state->scalers[*scaler_id].in_use = 0;
4845 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4846 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4847 intel_crtc->pipe, scaler_user, *scaler_id,
4848 scaler_state->scaler_users);
4849 *scaler_id = -1;
4850 }
4851 return 0;
4852 }
4854 if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4855 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4856 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4857 return -EINVAL;
4858 }
4860 /* range checks */
4861 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4862 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4863 (IS_GEN11(dev_priv) &&
4864 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4865 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4866 (!IS_GEN11(dev_priv) &&
4867 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4868 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4869 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4870 "size is out of scaler range\n",
4871 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4872 return -EINVAL;
4873 }
4875 /* mark this plane as a scaler user in crtc_state */
4876 scaler_state->scaler_users |= (1 << scaler_user);
4877 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4878 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4879 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4880 scaler_state->scaler_users);
4882 return 0;
4883 }
4885 /**
4886 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4887 *
4888 * @state: crtc's scaler state
4889 *
4890 * Return
4891 * 0 - scaler_usage updated successfully
4892 * error - requested scaling cannot be supported or other error condition
4893 */
4894 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4895 {
4896 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4898 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4899 &state->scaler_state.scaler_id,
4900 state->pipe_src_w, state->pipe_src_h,
4901 adjusted_mode->crtc_hdisplay,
4902 adjusted_mode->crtc_vdisplay, false, 0);
4903 }
4905 /**
4906 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4907 * @crtc_state: crtc's scaler state
4908 * @plane_state: atomic plane state to update
4909 *
4910 * Return
4911 * 0 - scaler_usage updated successfully
4912 * error - requested scaling cannot be supported or other error condition
4913 */
4914 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4915 struct intel_plane_state *plane_state)
4916 {
4918 struct intel_plane *intel_plane =
4919 to_intel_plane(plane_state->base.plane);
4920 struct drm_framebuffer *fb = plane_state->base.fb;
4921 int ret;
4923 bool force_detach = !fb || !plane_state->base.visible;
4925 ret = skl_update_scaler(crtc_state, force_detach,
4926 drm_plane_index(&intel_plane->base),
4927 &plane_state->scaler_id,
4928 drm_rect_width(&plane_state->base.src) >> 16,
4929 drm_rect_height(&plane_state->base.src) >> 16,
4930 drm_rect_width(&plane_state->base.dst),
4931 drm_rect_height(&plane_state->base.dst),
4932 fb ? true : false, fb ? fb->format->format : 0);
4934 if (ret || plane_state->scaler_id < 0)
4935 return ret;
4937 /* check colorkey */
4938 if (plane_state->ckey.flags) {
4939 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4940 intel_plane->base.base.id,
4941 intel_plane->base.name);
4942 return -EINVAL;
4943 }
4945 /* Check src format */
4946 switch (fb->format->format) {
4947 case DRM_FORMAT_RGB565:
4948 case DRM_FORMAT_XBGR8888:
4949 case DRM_FORMAT_XRGB8888:
4950 case DRM_FORMAT_ABGR8888:
4951 case DRM_FORMAT_ARGB8888:
4952 case DRM_FORMAT_XRGB2101010:
4953 case DRM_FORMAT_XBGR2101010:
4954 case DRM_FORMAT_YUYV:
4955 case DRM_FORMAT_YVYU:
4956 case DRM_FORMAT_UYVY:
4957 case DRM_FORMAT_VYUY:
4958 case DRM_FORMAT_NV12:
4959 break;
4960 default:
4961 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4962 intel_plane->base.base.id, intel_plane->base.name,
4963 fb->base.id, fb->format->format);
4964 return -EINVAL;
4965 }
4967 return 0;
4968 }
4970 static void skylake_scaler_disable(struct intel_crtc *crtc)
4971 {
4972 int i;
4974 for (i = 0; i < crtc->num_scalers; i++)
4975 skl_detach_scaler(crtc, i);
4976 }
4978 static void skylake_pfit_enable(struct intel_crtc *crtc)
4979 {
4980 struct drm_device *dev = crtc->base.dev;
4981 struct drm_i915_private *dev_priv = to_i915(dev);
4982 int pipe = crtc->pipe;
4983 struct intel_crtc_scaler_state *scaler_state =
4984 &crtc->config->scaler_state;
4986 if (crtc->config->pch_pfit.enabled) {
4987 u16 uv_rgb_hphase, uv_rgb_vphase;
4988 int id;
4990 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4991 return;
4993 uv_rgb_hphase = skl_scaler_calc_phase(1, false);
4994 uv_rgb_vphase = skl_scaler_calc_phase(1, false);
4996 id = scaler_state->scaler_id;
4997 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4998 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4999 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5000 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5001 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5002 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5003 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
5004 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
5005 }
5006 }
5008 static void ironlake_pfit_enable(struct intel_crtc *crtc)
5009 {
5010 struct drm_device *dev = crtc->base.dev;
5011 struct drm_i915_private *dev_priv = to_i915(dev);
5012 int pipe = crtc->pipe;
5014 if (crtc->config->pch_pfit.enabled) {
5015 /* Force use of hard-coded filter coefficients
5016 * as some pre-programmed values are broken,
5017 * e.g. x201.
5018 */
5019 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5020 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5021 PF_PIPE_SEL_IVB(pipe));
5022 else
5023 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5024 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
5025 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
5026 }
5027 }
5029 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5030 {
5031 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5032 struct drm_device *dev = crtc->base.dev;
5033 struct drm_i915_private *dev_priv = to_i915(dev);
5035 if (!crtc_state->ips_enabled)
5036 return;
5038 /*
5039 * We can only enable IPS after we enable a plane and wait for a vblank
5040 * This function is called from post_plane_update, which is run after
5041 * a vblank wait.
5042 */
5043 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5045 if (IS_BROADWELL(dev_priv)) {
5046 mutex_lock(&dev_priv->pcu_lock);
5047 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5048 IPS_ENABLE | IPS_PCODE_CONTROL));
5049 mutex_unlock(&dev_priv->pcu_lock);
5050 /* Quoting Art Runyan: "its not safe to expect any particular
5051 * value in IPS_CTL bit 31 after enabling IPS through the
5052 * mailbox." Moreover, the mailbox may return a bogus state,
5053 * so we need to just enable it and continue on.
5054 */
5055 } else {
5056 I915_WRITE(IPS_CTL, IPS_ENABLE);
5057 /* The bit only becomes 1 in the next vblank, so this wait here
5058 * is essentially intel_wait_for_vblank. If we don't have this
5059 * and don't wait for vblanks until the end of crtc_enable, then
5060 * the HW state readout code will complain that the expected
5061 * IPS_CTL value is not the one we read. */
5062 if (intel_wait_for_register(dev_priv,
5063 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5064 50))
5065 DRM_ERROR("Timed out waiting for IPS enable\n");
5066 }
5067 }
5069 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5070 {
5071 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5072 struct drm_device *dev = crtc->base.dev;
5073 struct drm_i915_private *dev_priv = to_i915(dev);
5075 if (!crtc_state->ips_enabled)
5076 return;
5078 if (IS_BROADWELL(dev_priv)) {
5079 mutex_lock(&dev_priv->pcu_lock);
5080 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5081 mutex_unlock(&dev_priv->pcu_lock);
5082 /*
5083 * Wait for PCODE to finish disabling IPS. The BSpec specified
5084 * 42ms timeout value leads to occasional timeouts so use 100ms
5085 * instead.
5086 */
5087 if (intel_wait_for_register(dev_priv,
5088 IPS_CTL, IPS_ENABLE, 0,
5089 100))
5090 DRM_ERROR("Timed out waiting for IPS disable\n");
5091 } else {
5092 I915_WRITE(IPS_CTL, 0);
5093 POSTING_READ(IPS_CTL);
5094 }
5096 /* We need to wait for a vblank before we can disable the plane. */
5097 intel_wait_for_vblank(dev_priv, crtc->pipe);
5098 }
5100 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5101 {
5102 if (intel_crtc->overlay) {
5103 struct drm_device *dev = intel_crtc->base.dev;
5105 mutex_lock(&dev->struct_mutex);
5106 (void) intel_overlay_switch_off(intel_crtc->overlay);
5107 mutex_unlock(&dev->struct_mutex);
5108 }
5110 /* Let userspace switch the overlay on again. In most cases userspace
5111 * has to recompute where to put it anyway.
5112 */
5113 }
5115 /**
5116 * intel_post_enable_primary - Perform operations after enabling primary plane
5117 * @crtc: the CRTC whose primary plane was just enabled
5118 * @new_crtc_state: the enabling state
5119 *
5120 * Performs potentially sleeping operations that must be done after the primary
5121 * plane is enabled, such as updating FBC and IPS. Note that this may be
5122 * called due to an explicit primary plane update, or due to an implicit
5123 * re-enable that is caused when a sprite plane is updated to no longer
5124 * completely hide the primary plane.
5125 */
5126 static void
5127 intel_post_enable_primary(struct drm_crtc *crtc,
5128 const struct intel_crtc_state *new_crtc_state)
5129 {
5130 struct drm_device *dev = crtc->dev;
5131 struct drm_i915_private *dev_priv = to_i915(dev);
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133 int pipe = intel_crtc->pipe;
5135 /*
5136 * Gen2 reports pipe underruns whenever all planes are disabled.
5137 * So don't enable underrun reporting before at least some planes
5138 * are enabled.
5139 * FIXME: Need to fix the logic to work when we turn off all planes
5140 * but leave the pipe running.
5141 */
5142 if (IS_GEN2(dev_priv))
5143 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5145 /* Underruns don't always raise interrupts, so check manually. */
5146 intel_check_cpu_fifo_underruns(dev_priv);
5147 intel_check_pch_fifo_underruns(dev_priv);
5148 }
5150 /* FIXME get rid of this and use pre_plane_update */
5151 static void
5152 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5153 {
5154 struct drm_device *dev = crtc->dev;
5155 struct drm_i915_private *dev_priv = to_i915(dev);
5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5157 int pipe = intel_crtc->pipe;
5159 /*
5160 * Gen2 reports pipe underruns whenever all planes are disabled.
5161 * So disable underrun reporting before all the planes get disabled.
5162 */
5163 if (IS_GEN2(dev_priv))
5164 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5166 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5168 /*
5169 * Vblank time updates from the shadow to live plane control register
5170 * are blocked if the memory self-refresh mode is active at that
5171 * moment. So to make sure the plane gets truly disabled, disable
5172 * first the self-refresh mode. The self-refresh enable bit in turn
5173 * will be checked/applied by the HW only at the next frame start
5174 * event which is after the vblank start event, so we need to have a
5175 * wait-for-vblank between disabling the plane and the pipe.
5176 */
5177 if (HAS_GMCH_DISPLAY(dev_priv) &&
5178 intel_set_memory_cxsr(dev_priv, false))
5179 intel_wait_for_vblank(dev_priv, pipe);
5180 }
5182 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5183 const struct intel_crtc_state *new_crtc_state)
5184 {
5185 if (!old_crtc_state->ips_enabled)
5186 return false;
5188 if (needs_modeset(&new_crtc_state->base))
5189 return true;
5191 return !new_crtc_state->ips_enabled;
5192 }
5194 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5195 const struct intel_crtc_state *new_crtc_state)
5196 {
5197 if (!new_crtc_state->ips_enabled)
5198 return false;
5200 if (needs_modeset(&new_crtc_state->base))
5201 return true;
5203 /*
5204 * We can't read out IPS on broadwell, assume the worst and
5205 * forcibly enable IPS on the first fastset.
5206 */
5207 if (new_crtc_state->update_pipe &&
5208 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5209 return true;
5211 return !old_crtc_state->ips_enabled;
5212 }
5214 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5215 const struct intel_crtc_state *crtc_state)
5216 {
5217 if (!crtc_state->nv12_planes)
5218 return false;
5220 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
5221 return false;
5223 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5224 IS_CANNONLAKE(dev_priv))
5225 return true;
5227 return false;
5228 }
5230 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5231 {
5232 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5233 struct drm_device *dev = crtc->base.dev;
5234 struct drm_i915_private *dev_priv = to_i915(dev);
5235 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5236 struct intel_crtc_state *pipe_config =
5237 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5238 crtc);
5239 struct drm_plane *primary = crtc->base.primary;
5240 struct drm_plane_state *old_primary_state =
5241 drm_atomic_get_old_plane_state(old_state, primary);
5243 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5245 if (pipe_config->update_wm_post && pipe_config->base.active)
5246 intel_update_watermarks(crtc);
5248 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5249 hsw_enable_ips(pipe_config);
5251 if (old_primary_state) {
5252 struct drm_plane_state *new_primary_state =
5253 drm_atomic_get_new_plane_state(old_state, primary);
5255 intel_fbc_post_update(crtc);
5257 if (new_primary_state->visible &&
5258 (needs_modeset(&pipe_config->base) ||
5259 !old_primary_state->visible))
5260 intel_post_enable_primary(&crtc->base, pipe_config);
5261 }
5263 /* Display WA 827 */
5264 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5265 !needs_nv12_wa(dev_priv, pipe_config)) {
5266 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5267 skl_wa_528(dev_priv, crtc->pipe, false);
5268 }
5269 }
5271 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5272 struct intel_crtc_state *pipe_config)
5273 {
5274 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5275 struct drm_device *dev = crtc->base.dev;
5276 struct drm_i915_private *dev_priv = to_i915(dev);
5277 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5278 struct drm_plane *primary = crtc->base.primary;
5279 struct drm_plane_state *old_primary_state =
5280 drm_atomic_get_old_plane_state(old_state, primary);
5281 bool modeset = needs_modeset(&pipe_config->base);
5282 struct intel_atomic_state *old_intel_state =
5283 to_intel_atomic_state(old_state);
5285 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5286 hsw_disable_ips(old_crtc_state);
5288 if (old_primary_state) {
5289 struct intel_plane_state *new_primary_state =
5290 intel_atomic_get_new_plane_state(old_intel_state,
5291 to_intel_plane(primary));
5293 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5294 /*
5295 * Gen2 reports pipe underruns whenever all planes are disabled.
5296 * So disable underrun reporting before all the planes get disabled.
5297 */
5298 if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5299 (modeset || !new_primary_state->base.visible))
5300 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5301 }
5303 /* Display WA 827 */
5304 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5305 needs_nv12_wa(dev_priv, pipe_config)) {
5306 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5307 skl_wa_528(dev_priv, crtc->pipe, true);
5308 }
5310 /*
5311 * Vblank time updates from the shadow to live plane control register
5312 * are blocked if the memory self-refresh mode is active at that
5313 * moment. So to make sure the plane gets truly disabled, disable
5314 * first the self-refresh mode. The self-refresh enable bit in turn
5315 * will be checked/applied by the HW only at the next frame start
5316 * event which is after the vblank start event, so we need to have a
5317 * wait-for-vblank between disabling the plane and the pipe.
5318 */
5319 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5320 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5321 intel_wait_for_vblank(dev_priv, crtc->pipe);
5323 /*
5324 * IVB workaround: must disable low power watermarks for at least
5325 * one frame before enabling scaling. LP watermarks can be re-enabled
5326 * when scaling is disabled.
5327 *
5328 * WaCxSRDisabledForSpriteScaling:ivb
5329 */
5330 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5331 intel_wait_for_vblank(dev_priv, crtc->pipe);
5333 /*
5334 * If we're doing a modeset, we're done. No need to do any pre-vblank
5335 * watermark programming here.
5336 */
5337 if (needs_modeset(&pipe_config->base))
5338 return;
5340 /*
5341 * For platforms that support atomic watermarks, program the
5342 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5343 * will be the intermediate values that are safe for both pre- and
5344 * post- vblank; when vblank happens, the 'active' values will be set
5345 * to the final 'target' values and we'll do this again to get the
5346 * optimal watermarks. For gen9+ platforms, the values we program here
5347 * will be the final target values which will get automatically latched
5348 * at vblank time; no further programming will be necessary.
5349 *
5350 * If a platform hasn't been transitioned to atomic watermarks yet,
5351 * we'll continue to update watermarks the old way, if flags tell
5352 * us to.
5353 */
5354 if (dev_priv->display.initial_watermarks != NULL)
5355 dev_priv->display.initial_watermarks(old_intel_state,
5356 pipe_config);
5357 else if (pipe_config->update_wm_pre)
5358 intel_update_watermarks(crtc);
5359 }
5361 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5362 {
5363 struct drm_device *dev = crtc->dev;
5364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5365 struct drm_plane *p;
5366 int pipe = intel_crtc->pipe;
5368 intel_crtc_dpms_overlay_disable(intel_crtc);
5370 drm_for_each_plane_mask(p, dev, plane_mask)
5371 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5373 /*
5374 * FIXME: Once we grow proper nuclear flip support out of this we need
5375 * to compute the mask of flip planes precisely. For the time being
5376 * consider this a flip to a NULL plane.
5377 */
5378 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5379 }
5381 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5382 struct intel_crtc_state *crtc_state,
5383 struct drm_atomic_state *old_state)
5384 {
5385 struct drm_connector_state *conn_state;
5386 struct drm_connector *conn;
5387 int i;
5389 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5390 struct intel_encoder *encoder =
5391 to_intel_encoder(conn_state->best_encoder);
5393 if (conn_state->crtc != crtc)
5394 continue;
5396 if (encoder->pre_pll_enable)
5397 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5398 }
5399 }
5401 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5402 struct intel_crtc_state *crtc_state,
5403 struct drm_atomic_state *old_state)
5404 {
5405 struct drm_connector_state *conn_state;
5406 struct drm_connector *conn;
5407 int i;
5409 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5410 struct intel_encoder *encoder =
5411 to_intel_encoder(conn_state->best_encoder);
5413 if (conn_state->crtc != crtc)
5414 continue;
5416 if (encoder->pre_enable)
5417 encoder->pre_enable(encoder, crtc_state, conn_state);
5418 }
5419 }
5421 static void intel_encoders_enable(struct drm_crtc *crtc,
5422 struct intel_crtc_state *crtc_state,
5423 struct drm_atomic_state *old_state)
5424 {
5425 struct drm_connector_state *conn_state;
5426 struct drm_connector *conn;
5427 int i;
5429 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5430 struct intel_encoder *encoder =
5431 to_intel_encoder(conn_state->best_encoder);
5433 if (conn_state->crtc != crtc)
5434 continue;
5436 encoder->enable(encoder, crtc_state, conn_state);
5437 intel_opregion_notify_encoder(encoder, true);
5438 }
5439 }
5441 static void intel_encoders_disable(struct drm_crtc *crtc,
5442 struct intel_crtc_state *old_crtc_state,
5443 struct drm_atomic_state *old_state)
5444 {
5445 struct drm_connector_state *old_conn_state;
5446 struct drm_connector *conn;
5447 int i;
5449 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5450 struct intel_encoder *encoder =
5451 to_intel_encoder(old_conn_state->best_encoder);
5453 if (old_conn_state->crtc != crtc)
5454 continue;
5456 intel_opregion_notify_encoder(encoder, false);
5457 encoder->disable(encoder, old_crtc_state, old_conn_state);
5458 }
5459 }
5461 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5462 struct intel_crtc_state *old_crtc_state,
5463 struct drm_atomic_state *old_state)
5464 {
5465 struct drm_connector_state *old_conn_state;
5466 struct drm_connector *conn;
5467 int i;
5469 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5470 struct intel_encoder *encoder =
5471 to_intel_encoder(old_conn_state->best_encoder);
5473 if (old_conn_state->crtc != crtc)
5474 continue;
5476 if (encoder->post_disable)
5477 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5478 }
5479 }
5481 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5482 struct intel_crtc_state *old_crtc_state,
5483 struct drm_atomic_state *old_state)
5484 {
5485 struct drm_connector_state *old_conn_state;
5486 struct drm_connector *conn;
5487 int i;
5489 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5490 struct intel_encoder *encoder =
5491 to_intel_encoder(old_conn_state->best_encoder);
5493 if (old_conn_state->crtc != crtc)
5494 continue;
5496 if (encoder->post_pll_disable)
5497 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5498 }
5499 }
5501 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5502 struct drm_atomic_state *old_state)
5503 {
5504 struct drm_crtc *crtc = pipe_config->base.crtc;
5505 struct drm_device *dev = crtc->dev;
5506 struct drm_i915_private *dev_priv = to_i915(dev);
5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508 int pipe = intel_crtc->pipe;
5509 struct intel_atomic_state *old_intel_state =
5510 to_intel_atomic_state(old_state);
5512 if (WARN_ON(intel_crtc->active))
5513 return;
5515 /*
5516 * Sometimes spurious CPU pipe underruns happen during FDI
5517 * training, at least with VGA+HDMI cloning. Suppress them.
5518 *
5519 * On ILK we get an occasional spurious CPU pipe underruns
5520 * between eDP port A enable and vdd enable. Also PCH port
5521 * enable seems to result in the occasional CPU pipe underrun.
5522 *
5523 * Spurious PCH underruns also occur during PCH enabling.
5524 */
5525 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5526 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5528 if (intel_crtc->config->has_pch_encoder)
5529 intel_prepare_shared_dpll(intel_crtc);
5531 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5532 intel_dp_set_m_n(intel_crtc, M1_N1);
5534 intel_set_pipe_timings(intel_crtc);
5535 intel_set_pipe_src_size(intel_crtc);
5537 if (intel_crtc->config->has_pch_encoder) {
5538 intel_cpu_transcoder_set_m_n(intel_crtc,
5539 &intel_crtc->config->fdi_m_n, NULL);
5540 }
5542 ironlake_set_pipeconf(crtc);
5544 intel_crtc->active = true;
5546 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5548 if (intel_crtc->config->has_pch_encoder) {
5549 /* Note: FDI PLL enabling _must_ be done before we enable the
5550 * cpu pipes, hence this is separate from all the other fdi/pch
5551 * enabling. */
5552 ironlake_fdi_pll_enable(intel_crtc);
5553 } else {
5554 assert_fdi_tx_disabled(dev_priv, pipe);
5555 assert_fdi_rx_disabled(dev_priv, pipe);
5556 }
5558 ironlake_pfit_enable(intel_crtc);
5560 /*
5561 * On ILK+ LUT must be loaded before the pipe is running but with
5562 * clocks enabled
5563 */
5564 intel_color_load_luts(&pipe_config->base);
5566 if (dev_priv->display.initial_watermarks != NULL)
5567 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5568 intel_enable_pipe(pipe_config);
5570 if (intel_crtc->config->has_pch_encoder)
5571 ironlake_pch_enable(old_intel_state, pipe_config);
5573 assert_vblank_disabled(crtc);
5574 drm_crtc_vblank_on(crtc);
5576 intel_encoders_enable(crtc, pipe_config, old_state);
5578 if (HAS_PCH_CPT(dev_priv))
5579 cpt_verify_modeset(dev, intel_crtc->pipe);
5581 /*
5582 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5583 * And a second vblank wait is needed at least on ILK with
5584 * some interlaced HDMI modes. Let's do the double wait always
5585 * in case there are more corner cases we don't know about.
5586 */
5587 if (intel_crtc->config->has_pch_encoder) {
5588 intel_wait_for_vblank(dev_priv, pipe);
5589 intel_wait_for_vblank(dev_priv, pipe);
5590 }
5591 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5592 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5593 }
5595 /* IPS only exists on ULT machines and is tied to pipe A. */
5596 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5597 {
5598 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5599 }
5601 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5602 enum pipe pipe, bool apply)
5603 {
5604 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5605 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5607 if (apply)
5608 val |= mask;
5609 else
5610 val &= ~mask;
5612 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5613 }
5615 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5616 {
5617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5618 enum pipe pipe = crtc->pipe;
5619 uint32_t val;
5621 val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5623 /* Program B credit equally to all pipes */
5624 val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5626 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5627 }
5629 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5630 struct drm_atomic_state *old_state)
5631 {
5632 struct drm_crtc *crtc = pipe_config->base.crtc;
5633 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5635 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5636 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5637 struct intel_atomic_state *old_intel_state =
5638 to_intel_atomic_state(old_state);
5639 bool psl_clkgate_wa;
5640 u32 pipe_chicken;
5642 if (WARN_ON(intel_crtc->active))
5643 return;
5645 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5647 if (intel_crtc->config->shared_dpll)
5648 intel_enable_shared_dpll(intel_crtc);
5650 if (INTEL_GEN(dev_priv) >= 11)
5651 icl_map_plls_to_ports(crtc, pipe_config, old_state);
5653 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5655 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5656 intel_dp_set_m_n(intel_crtc, M1_N1);
5658 if (!transcoder_is_dsi(cpu_transcoder))
5659 intel_set_pipe_timings(intel_crtc);
5661 intel_set_pipe_src_size(intel_crtc);
5663 if (cpu_transcoder != TRANSCODER_EDP &&
5664 !transcoder_is_dsi(cpu_transcoder)) {
5665 I915_WRITE(PIPE_MULT(cpu_transcoder),
5666 intel_crtc->config->pixel_multiplier - 1);
5667 }
5669 if (intel_crtc->config->has_pch_encoder) {
5670 intel_cpu_transcoder_set_m_n(intel_crtc,
5671 &intel_crtc->config->fdi_m_n, NULL);
5672 }
5674 if (!transcoder_is_dsi(cpu_transcoder))
5675 haswell_set_pipeconf(crtc);
5677 haswell_set_pipemisc(crtc);
5679 intel_color_set_csc(&pipe_config->base);
5681 intel_crtc->active = true;
5683 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5684 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5685 intel_crtc->config->pch_pfit.enabled;
5686 if (psl_clkgate_wa)
5687 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5689 if (INTEL_GEN(dev_priv) >= 9)
5690 skylake_pfit_enable(intel_crtc);
5691 else
5692 ironlake_pfit_enable(intel_crtc);
5694 /*
5695 * On ILK+ LUT must be loaded before the pipe is running but with
5696 * clocks enabled
5697 */
5698 intel_color_load_luts(&pipe_config->base);
5700 /*
5701 * Display WA #1153: enable hardware to bypass the alpha math
5702 * and rounding for per-pixel values 00 and 0xff
5703 */
5704 if (INTEL_GEN(dev_priv) >= 11) {
5705 pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
5706 if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
5707 I915_WRITE_FW(PIPE_CHICKEN(pipe),
5708 pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
5709 }
5711 intel_ddi_set_pipe_settings(pipe_config);
5712 if (!transcoder_is_dsi(cpu_transcoder))
5713 intel_ddi_enable_transcoder_func(pipe_config);
5715 if (dev_priv->display.initial_watermarks != NULL)
5716 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5718 if (INTEL_GEN(dev_priv) >= 11)
5719 icl_pipe_mbus_enable(intel_crtc);
5721 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5722 if (!transcoder_is_dsi(cpu_transcoder))
5723 intel_enable_pipe(pipe_config);
5725 if (intel_crtc->config->has_pch_encoder)
5726 lpt_pch_enable(old_intel_state, pipe_config);
5728 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5729 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5731 assert_vblank_disabled(crtc);
5732 drm_crtc_vblank_on(crtc);
5734 intel_encoders_enable(crtc, pipe_config, old_state);
5736 if (psl_clkgate_wa) {
5737 intel_wait_for_vblank(dev_priv, pipe);
5738 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5739 }
5741 /* If we change the relative order between pipe/planes enabling, we need
5742 * to change the workaround. */
5743 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5744 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5745 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5746 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5747 }
5748 }
5750 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5751 {
5752 struct drm_device *dev = crtc->base.dev;
5753 struct drm_i915_private *dev_priv = to_i915(dev);
5754 int pipe = crtc->pipe;
5756 /* To avoid upsetting the power well on haswell only disable the pfit if
5757 * it's in use. The hw state code will make sure we get this right. */
5758 if (force || crtc->config->pch_pfit.enabled) {
5759 I915_WRITE(PF_CTL(pipe), 0);
5760 I915_WRITE(PF_WIN_POS(pipe), 0);
5761 I915_WRITE(PF_WIN_SZ(pipe), 0);
5762 }
5763 }
5765 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5766 struct drm_atomic_state *old_state)
5767 {
5768 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5769 struct drm_device *dev = crtc->dev;
5770 struct drm_i915_private *dev_priv = to_i915(dev);
5771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5772 int pipe = intel_crtc->pipe;
5774 /*
5775 * Sometimes spurious CPU pipe underruns happen when the
5776 * pipe is already disabled, but FDI RX/TX is still enabled.
5777 * Happens at least with VGA+HDMI cloning. Suppress them.
5778 */
5779 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5780 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5782 intel_encoders_disable(crtc, old_crtc_state, old_state);
5784 drm_crtc_vblank_off(crtc);
5785 assert_vblank_disabled(crtc);
5787 intel_disable_pipe(old_crtc_state);
5789 ironlake_pfit_disable(intel_crtc, false);
5791 if (intel_crtc->config->has_pch_encoder)
5792 ironlake_fdi_disable(crtc);
5794 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5796 if (intel_crtc->config->has_pch_encoder) {
5797 ironlake_disable_pch_transcoder(dev_priv, pipe);
5799 if (HAS_PCH_CPT(dev_priv)) {
5800 i915_reg_t reg;
5801 u32 temp;
5803 /* disable TRANS_DP_CTL */
5804 reg = TRANS_DP_CTL(pipe);
5805 temp = I915_READ(reg);
5806 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5807 TRANS_DP_PORT_SEL_MASK);
5808 temp |= TRANS_DP_PORT_SEL_NONE;
5809 I915_WRITE(reg, temp);
5811 /* disable DPLL_SEL */
5812 temp = I915_READ(PCH_DPLL_SEL);
5813 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5814 I915_WRITE(PCH_DPLL_SEL, temp);
5815 }
5817 ironlake_fdi_pll_disable(intel_crtc);
5818 }
5820 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5821 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5822 }
5824 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5825 struct drm_atomic_state *old_state)
5826 {
5827 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5828 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5830 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
5832 intel_encoders_disable(crtc, old_crtc_state, old_state);
5834 drm_crtc_vblank_off(crtc);
5835 assert_vblank_disabled(crtc);
5837 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5838 if (!transcoder_is_dsi(cpu_transcoder))
5839 intel_disable_pipe(old_crtc_state);
5841 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
5842 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
5844 if (!transcoder_is_dsi(cpu_transcoder))
5845 intel_ddi_disable_transcoder_func(old_crtc_state);
5847 if (INTEL_GEN(dev_priv) >= 9)
5848 skylake_scaler_disable(intel_crtc);
5849 else
5850 ironlake_pfit_disable(intel_crtc, false);
5852 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5854 if (INTEL_GEN(dev_priv) >= 11)
5855 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
5856 }
5858 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5859 {
5860 struct drm_device *dev = crtc->base.dev;
5861 struct drm_i915_private *dev_priv = to_i915(dev);
5862 struct intel_crtc_state *pipe_config = crtc->config;
5864 if (!pipe_config->gmch_pfit.control)
5865 return;
5867 /*
5868 * The panel fitter should only be adjusted whilst the pipe is disabled,
5869 * according to register description and PRM.
5870 */
5871 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5872 assert_pipe_disabled(dev_priv, crtc->pipe);
5874 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5875 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5877 /* Border color in case we don't scale up to the full screen. Black by
5878 * default, change to something else for debugging. */
5879 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5880 }
5882 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
5883 {
5884 if (IS_ICELAKE(dev_priv))
5885 return port >= PORT_C && port <= PORT_F;
5887 return false;
5888 }
5890 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
5891 {
5892 if (!intel_port_is_tc(dev_priv, port))
5893 return PORT_TC_NONE;
5895 return port - PORT_C;
5896 }
5898 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5899 {
5900 switch (port) {
5901 case PORT_A:
5902 return POWER_DOMAIN_PORT_DDI_A_LANES;
5903 case PORT_B:
5904 return POWER_DOMAIN_PORT_DDI_B_LANES;
5905 case PORT_C:
5906 return POWER_DOMAIN_PORT_DDI_C_LANES;
5907 case PORT_D:
5908 return POWER_DOMAIN_PORT_DDI_D_LANES;
5909 case PORT_E:
5910 return POWER_DOMAIN_PORT_DDI_E_LANES;
5911 case PORT_F:
5912 return POWER_DOMAIN_PORT_DDI_F_LANES;
5913 default:
5914 MISSING_CASE(port);
5915 return POWER_DOMAIN_PORT_OTHER;
5916 }
5917 }
5919 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5920 struct intel_crtc_state *crtc_state)
5921 {
5922 struct drm_device *dev = crtc->dev;
5923 struct drm_i915_private *dev_priv = to_i915(dev);
5924 struct drm_encoder *encoder;
5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5926 enum pipe pipe = intel_crtc->pipe;
5927 u64 mask;
5928 enum transcoder transcoder = crtc_state->cpu_transcoder;
5930 if (!crtc_state->base.active)
5931 return 0;
5933 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5934 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5935 if (crtc_state->pch_pfit.enabled ||
5936 crtc_state->pch_pfit.force_thru)
5937 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5939 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5940 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5942 mask |= BIT_ULL(intel_encoder->power_domain);
5943 }
5945 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5946 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5948 if (crtc_state->shared_dpll)
5949 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5951 return mask;
5952 }
5954 static u64
5955 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5956 struct intel_crtc_state *crtc_state)
5957 {
5958 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5960 enum intel_display_power_domain domain;
5961 u64 domains, new_domains, old_domains;
5963 old_domains = intel_crtc->enabled_power_domains;
5964 intel_crtc->enabled_power_domains = new_domains =
5965 get_crtc_power_domains(crtc, crtc_state);
5967 domains = new_domains & ~old_domains;
5969 for_each_power_domain(domain, domains)
5970 intel_display_power_get(dev_priv, domain);
5972 return old_domains & ~new_domains;
5973 }
5975 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5976 u64 domains)
5977 {
5978 enum intel_display_power_domain domain;
5980 for_each_power_domain(domain, domains)
5981 intel_display_power_put(dev_priv, domain);
5982 }
5984 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5985 struct drm_atomic_state *old_state)
5986 {
5987 struct intel_atomic_state *old_intel_state =
5988 to_intel_atomic_state(old_state);
5989 struct drm_crtc *crtc = pipe_config->base.crtc;
5990 struct drm_device *dev = crtc->dev;
5991 struct drm_i915_private *dev_priv = to_i915(dev);
5992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5993 int pipe = intel_crtc->pipe;
5995 if (WARN_ON(intel_crtc->active))
5996 return;
5998 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5999 intel_dp_set_m_n(intel_crtc, M1_N1);
6001 intel_set_pipe_timings(intel_crtc);
6002 intel_set_pipe_src_size(intel_crtc);
6004 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6005 struct drm_i915_private *dev_priv = to_i915(dev);
6007 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6008 I915_WRITE(CHV_CANVAS(pipe), 0);
6009 }
6011 i9xx_set_pipeconf(intel_crtc);
6013 intel_crtc->active = true;
6015 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6017 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6019 if (IS_CHERRYVIEW(dev_priv)) {
6020 chv_prepare_pll(intel_crtc, intel_crtc->config);
6021 chv_enable_pll(intel_crtc, intel_crtc->config);
6022 } else {
6023 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6024 vlv_enable_pll(intel_crtc, intel_crtc->config);
6025 }
6027 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6029 i9xx_pfit_enable(intel_crtc);
6031 intel_color_load_luts(&pipe_config->base);
6033 dev_priv->display.initial_watermarks(old_intel_state,
6034 pipe_config);
6035 intel_enable_pipe(pipe_config);
6037 assert_vblank_disabled(crtc);
6038 drm_crtc_vblank_on(crtc);
6040 intel_encoders_enable(crtc, pipe_config, old_state);
6041 }
6043 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6044 {
6045 struct drm_device *dev = crtc->base.dev;
6046 struct drm_i915_private *dev_priv = to_i915(dev);
6048 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6049 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6050 }
6052 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6053 struct drm_atomic_state *old_state)
6054 {
6055 struct intel_atomic_state *old_intel_state =
6056 to_intel_atomic_state(old_state);
6057 struct drm_crtc *crtc = pipe_config->base.crtc;
6058 struct drm_device *dev = crtc->dev;
6059 struct drm_i915_private *dev_priv = to_i915(dev);
6060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6061 enum pipe pipe = intel_crtc->pipe;
6063 if (WARN_ON(intel_crtc->active))
6064 return;
6066 i9xx_set_pll_dividers(intel_crtc);
6068 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6069 intel_dp_set_m_n(intel_crtc, M1_N1);
6071 intel_set_pipe_timings(intel_crtc);
6072 intel_set_pipe_src_size(intel_crtc);
6074 i9xx_set_pipeconf(intel_crtc);
6076 intel_crtc->active = true;
6078 if (!IS_GEN2(dev_priv))
6079 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6081 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6083 i9xx_enable_pll(intel_crtc, pipe_config);
6085 i9xx_pfit_enable(intel_crtc);
6087 intel_color_load_luts(&pipe_config->base);
6089 if (dev_priv->display.initial_watermarks != NULL)
6090 dev_priv->display.initial_watermarks(old_intel_state,
6091 intel_crtc->config);
6092 else
6093 intel_update_watermarks(intel_crtc);
6094 intel_enable_pipe(pipe_config);
6096 assert_vblank_disabled(crtc);
6097 drm_crtc_vblank_on(crtc);
6099 intel_encoders_enable(crtc, pipe_config, old_state);
6100 }
6102 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6103 {
6104 struct drm_device *dev = crtc->base.dev;
6105 struct drm_i915_private *dev_priv = to_i915(dev);
6107 if (!crtc->config->gmch_pfit.control)
6108 return;
6110 assert_pipe_disabled(dev_priv, crtc->pipe);
6112 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6113 I915_READ(PFIT_CONTROL));
6114 I915_WRITE(PFIT_CONTROL, 0);
6115 }
6117 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6118 struct drm_atomic_state *old_state)
6119 {
6120 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6121 struct drm_device *dev = crtc->dev;
6122 struct drm_i915_private *dev_priv = to_i915(dev);
6123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124 int pipe = intel_crtc->pipe;
6126 /*
6127 * On gen2 planes are double buffered but the pipe isn't, so we must
6128 * wait for planes to fully turn off before disabling the pipe.
6129 */
6130 if (IS_GEN2(dev_priv))
6131 intel_wait_for_vblank(dev_priv, pipe);
6133 intel_encoders_disable(crtc, old_crtc_state, old_state);
6135 drm_crtc_vblank_off(crtc);
6136 assert_vblank_disabled(crtc);
6138 intel_disable_pipe(old_crtc_state);
6140 i9xx_pfit_disable(intel_crtc);
6142 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6144 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6145 if (IS_CHERRYVIEW(dev_priv))
6146 chv_disable_pll(dev_priv, pipe);
6147 else if (IS_VALLEYVIEW(dev_priv))
6148 vlv_disable_pll(dev_priv, pipe);
6149 else
6150 i9xx_disable_pll(intel_crtc);
6151 }
6153 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6155 if (!IS_GEN2(dev_priv))
6156 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6158 if (!dev_priv->display.initial_watermarks)
6159 intel_update_watermarks(intel_crtc);
6161 /* clock the pipe down to 640x480@60 to potentially save power */
6162 if (IS_I830(dev_priv))
6163 i830_enable_pipe(dev_priv, pipe);
6164 }
6166 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6167 struct drm_modeset_acquire_ctx *ctx)
6168 {
6169 struct intel_encoder *encoder;
6170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6171 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6172 enum intel_display_power_domain domain;
6173 struct intel_plane *plane;
6174 u64 domains;
6175 struct drm_atomic_state *state;
6176 struct intel_crtc_state *crtc_state;
6177 int ret;
6179 if (!intel_crtc->active)
6180 return;
6182 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6183 const struct intel_plane_state *plane_state =
6184 to_intel_plane_state(plane->base.state);
6186 if (plane_state->base.visible)
6187 intel_plane_disable_noatomic(intel_crtc, plane);
6188 }
6190 state = drm_atomic_state_alloc(crtc->dev);
6191 if (!state) {
6192 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6193 crtc->base.id, crtc->name);
6194 return;
6195 }
6197 state->acquire_ctx = ctx;
6199 /* Everything's already locked, -EDEADLK can't happen. */
6200 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6201 ret = drm_atomic_add_affected_connectors(state, crtc);
6203 WARN_ON(IS_ERR(crtc_state) || ret);
6205 dev_priv->display.crtc_disable(crtc_state, state);
6207 drm_atomic_state_put(state);
6209 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6210 crtc->base.id, crtc->name);
6212 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6213 crtc->state->active = false;
6214 intel_crtc->active = false;
6215 crtc->enabled = false;
6216 crtc->state->connector_mask = 0;
6217 crtc->state->encoder_mask = 0;
6219 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6220 encoder->base.crtc = NULL;
6222 intel_fbc_disable(intel_crtc);
6223 intel_update_watermarks(intel_crtc);
6224 intel_disable_shared_dpll(intel_crtc);
6226 domains = intel_crtc->enabled_power_domains;
6227 for_each_power_domain(domain, domains)
6228 intel_display_power_put(dev_priv, domain);
6229 intel_crtc->enabled_power_domains = 0;
6231 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6232 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6233 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6234 }
6236 /*
6237 * turn all crtc's off, but do not adjust state
6238 * This has to be paired with a call to intel_modeset_setup_hw_state.
6239 */
6240 int intel_display_suspend(struct drm_device *dev)
6241 {
6242 struct drm_i915_private *dev_priv = to_i915(dev);
6243 struct drm_atomic_state *state;
6244 int ret;
6246 state = drm_atomic_helper_suspend(dev);
6247 ret = PTR_ERR_OR_ZERO(state);
6248 if (ret)
6249 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6250 else
6251 dev_priv->modeset_restore_state = state;
6252 return ret;
6253 }
6255 void intel_encoder_destroy(struct drm_encoder *encoder)
6256 {
6257 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6259 drm_encoder_cleanup(encoder);
6260 kfree(intel_encoder);
6261 }
6263 /* Cross check the actual hw state with our own modeset state tracking (and it's
6264 * internal consistency). */
6265 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6266 struct drm_connector_state *conn_state)
6267 {
6268 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6270 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6271 connector->base.base.id,
6272 connector->base.name);
6274 if (connector->get_hw_state(connector)) {
6275 struct intel_encoder *encoder = connector->encoder;
6277 I915_STATE_WARN(!crtc_state,
6278 "connector enabled without attached crtc\n");
6280 if (!crtc_state)
6281 return;
6283 I915_STATE_WARN(!crtc_state->active,
6284 "connector is active, but attached crtc isn't\n");
6286 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6287 return;
6289 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6290 "atomic encoder doesn't match attached encoder\n");
6292 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6293 "attached encoder crtc differs from connector crtc\n");
6294 } else {
6295 I915_STATE_WARN(crtc_state && crtc_state->active,
6296 "attached crtc is active, but connector isn't\n");
6297 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6298 "best encoder set without crtc!\n");
6299 }
6300 }
6302 int intel_connector_init(struct intel_connector *connector)
6303 {
6304 struct intel_digital_connector_state *conn_state;
6306 /*
6307 * Allocate enough memory to hold intel_digital_connector_state,
6308 * This might be a few bytes too many, but for connectors that don't
6309 * need it we'll free the state and allocate a smaller one on the first
6310 * succesful commit anyway.
6311 */
6312 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6313 if (!conn_state)
6314 return -ENOMEM;
6316 __drm_atomic_helper_connector_reset(&connector->base,
6317 &conn_state->base);
6319 return 0;
6320 }
6322 struct intel_connector *intel_connector_alloc(void)
6323 {
6324 struct intel_connector *connector;
6326 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6327 if (!connector)
6328 return NULL;
6330 if (intel_connector_init(connector) < 0) {
6331 kfree(connector);
6332 return NULL;
6333 }
6335 return connector;
6336 }
6338 /*
6339 * Free the bits allocated by intel_connector_alloc.
6340 * This should only be used after intel_connector_alloc has returned
6341 * successfully, and before drm_connector_init returns successfully.
6342 * Otherwise the destroy callbacks for the connector and the state should
6343 * take care of proper cleanup/free
6344 */
6345 void intel_connector_free(struct intel_connector *connector)
6346 {
6347 kfree(to_intel_digital_connector_state(connector->base.state));
6348 kfree(connector);
6349 }
6351 /* Simple connector->get_hw_state implementation for encoders that support only
6352 * one connector and no cloning and hence the encoder state determines the state
6353 * of the connector. */
6354 bool intel_connector_get_hw_state(struct intel_connector *connector)
6355 {
6356 enum pipe pipe = 0;
6357 struct intel_encoder *encoder = connector->encoder;
6359 return encoder->get_hw_state(encoder, &pipe);
6360 }
6362 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6363 {
6364 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6365 return crtc_state->fdi_lanes;
6367 return 0;
6368 }
6370 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6371 struct intel_crtc_state *pipe_config)
6372 {
6373 struct drm_i915_private *dev_priv = to_i915(dev);
6374 struct drm_atomic_state *state = pipe_config->base.state;
6375 struct intel_crtc *other_crtc;
6376 struct intel_crtc_state *other_crtc_state;
6378 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6379 pipe_name(pipe), pipe_config->fdi_lanes);
6380 if (pipe_config->fdi_lanes > 4) {
6381 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6382 pipe_name(pipe), pipe_config->fdi_lanes);
6383 return -EINVAL;
6384 }
6386 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6387 if (pipe_config->fdi_lanes > 2) {
6388 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6389 pipe_config->fdi_lanes);
6390 return -EINVAL;
6391 } else {
6392 return 0;
6393 }
6394 }
6396 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6397 return 0;
6399 /* Ivybridge 3 pipe is really complicated */
6400 switch (pipe) {
6401 case PIPE_A:
6402 return 0;
6403 case PIPE_B:
6404 if (pipe_config->fdi_lanes <= 2)
6405 return 0;
6407 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6408 other_crtc_state =
6409 intel_atomic_get_crtc_state(state, other_crtc);
6410 if (IS_ERR(other_crtc_state))
6411 return PTR_ERR(other_crtc_state);
6413 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6414 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6415 pipe_name(pipe), pipe_config->fdi_lanes);
6416 return -EINVAL;
6417 }
6418 return 0;
6419 case PIPE_C:
6420 if (pipe_config->fdi_lanes > 2) {
6421 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6422 pipe_name(pipe), pipe_config->fdi_lanes);
6423 return -EINVAL;
6424 }
6426 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6427 other_crtc_state =
6428 intel_atomic_get_crtc_state(state, other_crtc);
6429 if (IS_ERR(other_crtc_state))
6430 return PTR_ERR(other_crtc_state);
6432 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6433 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6434 return -EINVAL;
6435 }
6436 return 0;
6437 default:
6438 BUG();
6439 }
6440 }
6442 #define RETRY 1
6443 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6444 struct intel_crtc_state *pipe_config)
6445 {
6446 struct drm_device *dev = intel_crtc->base.dev;
6447 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6448 int lane, link_bw, fdi_dotclock, ret;
6449 bool needs_recompute = false;
6451 retry:
6452 /* FDI is a binary signal running at ~2.7GHz, encoding
6453 * each output octet as 10 bits. The actual frequency
6454 * is stored as a divider into a 100MHz clock, and the
6455 * mode pixel clock is stored in units of 1KHz.
6456 * Hence the bw of each lane in terms of the mode signal
6457 * is:
6458 */
6459 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6461 fdi_dotclock = adjusted_mode->crtc_clock;
6463 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6464 pipe_config->pipe_bpp);
6466 pipe_config->fdi_lanes = lane;
6468 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6469 link_bw, &pipe_config->fdi_m_n, false);
6471 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6472 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6473 pipe_config->pipe_bpp -= 2*3;
6474 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6475 pipe_config->pipe_bpp);
6476 needs_recompute = true;
6477 pipe_config->bw_constrained = true;
6479 goto retry;
6480 }
6482 if (needs_recompute)
6483 return RETRY;
6485 return ret;
6486 }
6488 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6489 {
6490 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6493 /* IPS only exists on ULT machines and is tied to pipe A. */
6494 if (!hsw_crtc_supports_ips(crtc))
6495 return false;
6497 if (!i915_modparams.enable_ips)
6498 return false;
6500 if (crtc_state->pipe_bpp > 24)
6501 return false;
6503 /*
6504 * We compare against max which means we must take
6505 * the increased cdclk requirement into account when
6506 * calculating the new cdclk.
6507 *
6508 * Should measure whether using a lower cdclk w/o IPS
6509 */
6510 if (IS_BROADWELL(dev_priv) &&
6511 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6512 return false;
6514 return true;
6515 }
6517 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6518 {
6519 struct drm_i915_private *dev_priv =
6520 to_i915(crtc_state->base.crtc->dev);
6521 struct intel_atomic_state *intel_state =
6522 to_intel_atomic_state(crtc_state->base.state);
6524 if (!hsw_crtc_state_ips_capable(crtc_state))
6525 return false;
6527 if (crtc_state->ips_force_disable)
6528 return false;
6530 /* IPS should be fine as long as at least one plane is enabled. */
6531 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6532 return false;
6534 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6535 if (IS_BROADWELL(dev_priv) &&
6536 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6537 return false;
6539 return true;
6540 }
6542 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6543 {
6544 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6546 /* GDG double wide on either pipe, otherwise pipe A only */
6547 return INTEL_GEN(dev_priv) < 4 &&
6548 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6549 }
6551 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6552 {
6553 uint32_t pixel_rate;
6555 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6557 /*
6558 * We only use IF-ID interlacing. If we ever use
6559 * PF-ID we'll need to adjust the pixel_rate here.
6560 */
6562 if (pipe_config->pch_pfit.enabled) {
6563 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6564 uint32_t pfit_size = pipe_config->pch_pfit.size;
6566 pipe_w = pipe_config->pipe_src_w;
6567 pipe_h = pipe_config->pipe_src_h;
6569 pfit_w = (pfit_size >> 16) & 0xFFFF;
6570 pfit_h = pfit_size & 0xFFFF;
6571 if (pipe_w < pfit_w)
6572 pipe_w = pfit_w;
6573 if (pipe_h < pfit_h)
6574 pipe_h = pfit_h;
6576 if (WARN_ON(!pfit_w || !pfit_h))
6577 return pixel_rate;
6579 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6580 pfit_w * pfit_h);
6581 }
6583 return pixel_rate;
6584 }
6586 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6587 {
6588 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6590 if (HAS_GMCH_DISPLAY(dev_priv))
6591 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6592 crtc_state->pixel_rate =
6593 crtc_state->base.adjusted_mode.crtc_clock;
6594 else
6595 crtc_state->pixel_rate =
6596 ilk_pipe_pixel_rate(crtc_state);
6597 }
6599 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6600 struct intel_crtc_state *pipe_config)
6601 {
6602 struct drm_device *dev = crtc->base.dev;
6603 struct drm_i915_private *dev_priv = to_i915(dev);
6604 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6605 int clock_limit = dev_priv->max_dotclk_freq;
6607 if (INTEL_GEN(dev_priv) < 4) {
6608 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6610 /*
6611 * Enable double wide mode when the dot clock
6612 * is > 90% of the (display) core speed.
6613 */
6614 if (intel_crtc_supports_double_wide(crtc) &&
6615 adjusted_mode->crtc_clock > clock_limit) {
6616 clock_limit = dev_priv->max_dotclk_freq;
6617 pipe_config->double_wide = true;
6618 }
6619 }
6621 if (adjusted_mode->crtc_clock > clock_limit) {
6622 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6623 adjusted_mode->crtc_clock, clock_limit,
6624 yesno(pipe_config->double_wide));
6625 return -EINVAL;
6626 }
6628 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6629 /*
6630 * There is only one pipe CSC unit per pipe, and we need that
6631 * for output conversion from RGB->YCBCR. So if CTM is already
6632 * applied we can't support YCBCR420 output.
6633 */
6634 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6635 return -EINVAL;
6636 }
6638 /*
6639 * Pipe horizontal size must be even in:
6640 * - DVO ganged mode
6641 * - LVDS dual channel mode
6642 * - Double wide pipe
6643 */
6644 if (pipe_config->pipe_src_w & 1) {
6645 if (pipe_config->double_wide) {
6646 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6647 return -EINVAL;
6648 }
6650 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6651 intel_is_dual_link_lvds(dev)) {
6652 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6653 return -EINVAL;
6654 }
6655 }
6657 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6658 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6659 */
6660 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6661 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6662 return -EINVAL;
6664 intel_crtc_compute_pixel_rate(pipe_config);
6666 if (pipe_config->has_pch_encoder)
6667 return ironlake_fdi_compute_config(crtc, pipe_config);
6669 return 0;
6670 }
6672 static void
6673 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6674 {
6675 while (*num > DATA_LINK_M_N_MASK ||
6676 *den > DATA_LINK_M_N_MASK) {
6677 *num >>= 1;
6678 *den >>= 1;
6679 }
6680 }
6682 static void compute_m_n(unsigned int m, unsigned int n,
6683 uint32_t *ret_m, uint32_t *ret_n,
6684 bool reduce_m_n)
6685 {
6686 /*
6687 * Reduce M/N as much as possible without loss in precision. Several DP
6688 * dongles in particular seem to be fussy about too large *link* M/N
6689 * values. The passed in values are more likely to have the least
6690 * significant bits zero than M after rounding below, so do this first.
6691 */
6692 if (reduce_m_n) {
6693 while ((m & 1) == 0 && (n & 1) == 0) {
6694 m >>= 1;
6695 n >>= 1;
6696 }
6697 }
6699 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6700 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6701 intel_reduce_m_n_ratio(ret_m, ret_n);
6702 }
6704 void
6705 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6706 int pixel_clock, int link_clock,
6707 struct intel_link_m_n *m_n,
6708 bool reduce_m_n)
6709 {
6710 m_n->tu = 64;
6712 compute_m_n(bits_per_pixel * pixel_clock,
6713 link_clock * nlanes * 8,
6714 &m_n->gmch_m, &m_n->gmch_n,
6715 reduce_m_n);
6717 compute_m_n(pixel_clock, link_clock,
6718 &m_n->link_m, &m_n->link_n,
6719 reduce_m_n);
6720 }
6722 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6723 {
6724 if (i915_modparams.panel_use_ssc >= 0)
6725 return i915_modparams.panel_use_ssc != 0;
6726 return dev_priv->vbt.lvds_use_ssc
6727 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6728 }
6730 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6731 {
6732 return (1 << dpll->n) << 16 | dpll->m2;
6733 }
6735 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6736 {
6737 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6738 }
6740 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6741 struct intel_crtc_state *crtc_state,
6742 struct dpll *reduced_clock)
6743 {
6744 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6745 u32 fp, fp2 = 0;
6747 if (IS_PINEVIEW(dev_priv)) {
6748 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6749 if (reduced_clock)
6750 fp2 = pnv_dpll_compute_fp(reduced_clock);
6751 } else {
6752 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6753 if (reduced_clock)
6754 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6755 }
6757 crtc_state->dpll_hw_state.fp0 = fp;
6759 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6760 reduced_clock) {
6761 crtc_state->dpll_hw_state.fp1 = fp2;
6762 } else {
6763 crtc_state->dpll_hw_state.fp1 = fp;
6764 }
6765 }
6767 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6768 pipe)
6769 {
6770 u32 reg_val;
6772 /*
6773 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6774 * and set it to a reasonable value instead.
6775 */
6776 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6777 reg_val &= 0xffffff00;
6778 reg_val |= 0x00000030;
6779 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6781 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6782 reg_val &= 0x00ffffff;
6783 reg_val |= 0x8c000000;
6784 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6786 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6787 reg_val &= 0xffffff00;
6788 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6790 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6791 reg_val &= 0x00ffffff;
6792 reg_val |= 0xb0000000;
6793 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6794 }
6796 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6797 struct intel_link_m_n *m_n)
6798 {
6799 struct drm_device *dev = crtc->base.dev;
6800 struct drm_i915_private *dev_priv = to_i915(dev);
6801 int pipe = crtc->pipe;
6803 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6804 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6805 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6806 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6807 }
6809 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6810 struct intel_link_m_n *m_n,
6811 struct intel_link_m_n *m2_n2)
6812 {
6813 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6814 int pipe = crtc->pipe;
6815 enum transcoder transcoder = crtc->config->cpu_transcoder;
6817 if (INTEL_GEN(dev_priv) >= 5) {
6818 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6819 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6820 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6821 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6822 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6823 * for gen < 8) and if DRRS is supported (to make sure the
6824 * registers are not unnecessarily accessed).
6825 */
6826 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6827 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6828 I915_WRITE(PIPE_DATA_M2(transcoder),
6829 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6830 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6831 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6832 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6833 }
6834 } else {
6835 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6836 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6837 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6838 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6839 }
6840 }
6842 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6843 {
6844 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6846 if (m_n == M1_N1) {
6847 dp_m_n = &crtc->config->dp_m_n;
6848 dp_m2_n2 = &crtc->config->dp_m2_n2;
6849 } else if (m_n == M2_N2) {
6851 /*
6852 * M2_N2 registers are not supported. Hence m2_n2 divider value
6853 * needs to be programmed into M1_N1.
6854 */
6855 dp_m_n = &crtc->config->dp_m2_n2;
6856 } else {
6857 DRM_ERROR("Unsupported divider value\n");
6858 return;
6859 }
6861 if (crtc->config->has_pch_encoder)
6862 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6863 else
6864 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6865 }
6867 static void vlv_compute_dpll(struct intel_crtc *crtc,
6868 struct intel_crtc_state *pipe_config)
6869 {
6870 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6871 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6872 if (crtc->pipe != PIPE_A)
6873 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6875 /* DPLL not used with DSI, but still need the rest set up */
6876 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6877 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6878 DPLL_EXT_BUFFER_ENABLE_VLV;
6880 pipe_config->dpll_hw_state.dpll_md =
6881 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6882 }
6884 static void chv_compute_dpll(struct intel_crtc *crtc,
6885 struct intel_crtc_state *pipe_config)
6886 {
6887 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6888 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6889 if (crtc->pipe != PIPE_A)
6890 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6892 /* DPLL not used with DSI, but still need the rest set up */
6893 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6894 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6896 pipe_config->dpll_hw_state.dpll_md =
6897 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6898 }
6900 static void vlv_prepare_pll(struct intel_crtc *crtc,
6901 const struct intel_crtc_state *pipe_config)
6902 {
6903 struct drm_device *dev = crtc->base.dev;
6904 struct drm_i915_private *dev_priv = to_i915(dev);
6905 enum pipe pipe = crtc->pipe;
6906 u32 mdiv;
6907 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6908 u32 coreclk, reg_val;
6910 /* Enable Refclk */
6911 I915_WRITE(DPLL(pipe),
6912 pipe_config->dpll_hw_state.dpll &
6913 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6915 /* No need to actually set up the DPLL with DSI */
6916 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6917 return;
6919 mutex_lock(&dev_priv->sb_lock);
6921 bestn = pipe_config->dpll.n;
6922 bestm1 = pipe_config->dpll.m1;
6923 bestm2 = pipe_config->dpll.m2;
6924 bestp1 = pipe_config->dpll.p1;
6925 bestp2 = pipe_config->dpll.p2;
6927 /* See eDP HDMI DPIO driver vbios notes doc */
6929 /* PLL B needs special handling */
6930 if (pipe == PIPE_B)
6931 vlv_pllb_recal_opamp(dev_priv, pipe);
6933 /* Set up Tx target for periodic Rcomp update */
6934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6936 /* Disable target IRef on PLL */
6937 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6938 reg_val &= 0x00ffffff;
6939 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6941 /* Disable fast lock */
6942 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6944 /* Set idtafcrecal before PLL is enabled */
6945 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6946 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6947 mdiv |= ((bestn << DPIO_N_SHIFT));
6948 mdiv |= (1 << DPIO_K_SHIFT);
6950 /*
6951 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6952 * but we don't support that).
6953 * Note: don't use the DAC post divider as it seems unstable.
6954 */
6955 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6958 mdiv |= DPIO_ENABLE_CALIBRATION;
6959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6961 /* Set HBR and RBR LPF coefficients */
6962 if (pipe_config->port_clock == 162000 ||
6963 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6964 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6966 0x009f0003);
6967 else
6968 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6969 0x00d0000f);
6971 if (intel_crtc_has_dp_encoder(pipe_config)) {
6972 /* Use SSC source */
6973 if (pipe == PIPE_A)
6974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6975 0x0df40000);
6976 else
6977 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6978 0x0df70000);
6979 } else { /* HDMI or VGA */
6980 /* Use bend source */
6981 if (pipe == PIPE_A)
6982 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6983 0x0df70000);
6984 else
6985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6986 0x0df40000);
6987 }
6989 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6990 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6991 if (intel_crtc_has_dp_encoder(crtc->config))
6992 coreclk |= 0x01000000;
6993 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6995 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6996 mutex_unlock(&dev_priv->sb_lock);
6997 }
6999 static void chv_prepare_pll(struct intel_crtc *crtc,
7000 const struct intel_crtc_state *pipe_config)
7001 {
7002 struct drm_device *dev = crtc->base.dev;
7003 struct drm_i915_private *dev_priv = to_i915(dev);
7004 enum pipe pipe = crtc->pipe;
7005 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7006 u32 loopfilter, tribuf_calcntr;
7007 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7008 u32 dpio_val;
7009 int vco;
7011 /* Enable Refclk and SSC */
7012 I915_WRITE(DPLL(pipe),
7013 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7015 /* No need to actually set up the DPLL with DSI */
7016 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7017 return;
7019 bestn = pipe_config->dpll.n;
7020 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7021 bestm1 = pipe_config->dpll.m1;
7022 bestm2 = pipe_config->dpll.m2 >> 22;
7023 bestp1 = pipe_config->dpll.p1;
7024 bestp2 = pipe_config->dpll.p2;
7025 vco = pipe_config->dpll.vco;
7026 dpio_val = 0;
7027 loopfilter = 0;
7029 mutex_lock(&dev_priv->sb_lock);
7031 /* p1 and p2 divider */
7032 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7033 5 << DPIO_CHV_S1_DIV_SHIFT |
7034 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7035 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7036 1 << DPIO_CHV_K_DIV_SHIFT);
7038 /* Feedback post-divider - m2 */
7039 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7041 /* Feedback refclk divider - n and m1 */
7042 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7043 DPIO_CHV_M1_DIV_BY_2 |
7044 1 << DPIO_CHV_N_DIV_SHIFT);
7046 /* M2 fraction division */
7047 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7049 /* M2 fraction division enable */
7050 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7051 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7052 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7053 if (bestm2_frac)
7054 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7055 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7057 /* Program digital lock detect threshold */
7058 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7059 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7060 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7061 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7062 if (!bestm2_frac)
7063 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7064 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7066 /* Loop filter */
7067 if (vco == 5400000) {
7068 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7069 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7070 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7071 tribuf_calcntr = 0x9;
7072 } else if (vco <= 6200000) {
7073 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7074 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7075 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7076 tribuf_calcntr = 0x9;
7077 } else if (vco <= 6480000) {
7078 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7079 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7080 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7081 tribuf_calcntr = 0x8;
7082 } else {
7083 /* Not supported. Apply the same limits as in the max case */
7084 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7085 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7086 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7087 tribuf_calcntr = 0;
7088 }
7089 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7091 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7092 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7093 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7094 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7096 /* AFC Recal */
7097 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7098 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7099 DPIO_AFC_RECAL);
7101 mutex_unlock(&dev_priv->sb_lock);
7102 }
7104 /**
7105 * vlv_force_pll_on - forcibly enable just the PLL
7106 * @dev_priv: i915 private structure
7107 * @pipe: pipe PLL to enable
7108 * @dpll: PLL configuration
7109 *
7110 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7111 * in cases where we need the PLL enabled even when @pipe is not going to
7112 * be enabled.
7113 */
7114 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7115 const struct dpll *dpll)
7116 {
7117 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7118 struct intel_crtc_state *pipe_config;
7120 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7121 if (!pipe_config)
7122 return -ENOMEM;
7124 pipe_config->base.crtc = &crtc->base;
7125 pipe_config->pixel_multiplier = 1;
7126 pipe_config->dpll = *dpll;
7128 if (IS_CHERRYVIEW(dev_priv)) {
7129 chv_compute_dpll(crtc, pipe_config);
7130 chv_prepare_pll(crtc, pipe_config);
7131 chv_enable_pll(crtc, pipe_config);
7132 } else {
7133 vlv_compute_dpll(crtc, pipe_config);
7134 vlv_prepare_pll(crtc, pipe_config);
7135 vlv_enable_pll(crtc, pipe_config);
7136 }
7138 kfree(pipe_config);
7140 return 0;
7141 }
7143 /**
7144 * vlv_force_pll_off - forcibly disable just the PLL
7145 * @dev_priv: i915 private structure
7146 * @pipe: pipe PLL to disable
7147 *
7148 * Disable the PLL for @pipe. To be used in cases where we need
7149 * the PLL enabled even when @pipe is not going to be enabled.
7150 */
7151 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7152 {
7153 if (IS_CHERRYVIEW(dev_priv))
7154 chv_disable_pll(dev_priv, pipe);
7155 else
7156 vlv_disable_pll(dev_priv, pipe);
7157 }
7159 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7160 struct intel_crtc_state *crtc_state,
7161 struct dpll *reduced_clock)
7162 {
7163 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7164 u32 dpll;
7165 struct dpll *clock = &crtc_state->dpll;
7167 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7169 dpll = DPLL_VGA_MODE_DIS;
7171 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7172 dpll |= DPLLB_MODE_LVDS;
7173 else
7174 dpll |= DPLLB_MODE_DAC_SERIAL;
7176 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7177 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7178 dpll |= (crtc_state->pixel_multiplier - 1)
7179 << SDVO_MULTIPLIER_SHIFT_HIRES;
7180 }
7182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7183 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7184 dpll |= DPLL_SDVO_HIGH_SPEED;
7186 if (intel_crtc_has_dp_encoder(crtc_state))
7187 dpll |= DPLL_SDVO_HIGH_SPEED;
7189 /* compute bitmask from p1 value */
7190 if (IS_PINEVIEW(dev_priv))
7191 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7192 else {
7193 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7194 if (IS_G4X(dev_priv) && reduced_clock)
7195 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7196 }
7197 switch (clock->p2) {
7198 case 5:
7199 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7200 break;
7201 case 7:
7202 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7203 break;
7204 case 10:
7205 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7206 break;
7207 case 14:
7208 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7209 break;
7210 }
7211 if (INTEL_GEN(dev_priv) >= 4)
7212 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7214 if (crtc_state->sdvo_tv_clock)
7215 dpll |= PLL_REF_INPUT_TVCLKINBC;
7216 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7217 intel_panel_use_ssc(dev_priv))
7218 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7219 else
7220 dpll |= PLL_REF_INPUT_DREFCLK;
7222 dpll |= DPLL_VCO_ENABLE;
7223 crtc_state->dpll_hw_state.dpll = dpll;
7225 if (INTEL_GEN(dev_priv) >= 4) {
7226 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7227 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7228 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7229 }
7230 }
7232 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7233 struct intel_crtc_state *crtc_state,
7234 struct dpll *reduced_clock)
7235 {
7236 struct drm_device *dev = crtc->base.dev;
7237 struct drm_i915_private *dev_priv = to_i915(dev);
7238 u32 dpll;
7239 struct dpll *clock = &crtc_state->dpll;
7241 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7243 dpll = DPLL_VGA_MODE_DIS;
7245 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7246 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7247 } else {
7248 if (clock->p1 == 2)
7249 dpll |= PLL_P1_DIVIDE_BY_TWO;
7250 else
7251 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7252 if (clock->p2 == 4)
7253 dpll |= PLL_P2_DIVIDE_BY_4;
7254 }
7256 if (!IS_I830(dev_priv) &&
7257 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7258 dpll |= DPLL_DVO_2X_MODE;
7260 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7261 intel_panel_use_ssc(dev_priv))
7262 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7263 else
7264 dpll |= PLL_REF_INPUT_DREFCLK;
7266 dpll |= DPLL_VCO_ENABLE;
7267 crtc_state->dpll_hw_state.dpll = dpll;
7268 }
7270 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7271 {
7272 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7273 enum pipe pipe = intel_crtc->pipe;
7274 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7275 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7276 uint32_t crtc_vtotal, crtc_vblank_end;
7277 int vsyncshift = 0;
7279 /* We need to be careful not to changed the adjusted mode, for otherwise
7280 * the hw state checker will get angry at the mismatch. */
7281 crtc_vtotal = adjusted_mode->crtc_vtotal;
7282 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7284 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7285 /* the chip adds 2 halflines automatically */
7286 crtc_vtotal -= 1;
7287 crtc_vblank_end -= 1;
7289 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7290 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7291 else
7292 vsyncshift = adjusted_mode->crtc_hsync_start -
7293 adjusted_mode->crtc_htotal / 2;
7294 if (vsyncshift < 0)
7295 vsyncshift += adjusted_mode->crtc_htotal;
7296 }
7298 if (INTEL_GEN(dev_priv) > 3)
7299 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7301 I915_WRITE(HTOTAL(cpu_transcoder),
7302 (adjusted_mode->crtc_hdisplay - 1) |
7303 ((adjusted_mode->crtc_htotal - 1) << 16));
7304 I915_WRITE(HBLANK(cpu_transcoder),
7305 (adjusted_mode->crtc_hblank_start - 1) |
7306 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7307 I915_WRITE(HSYNC(cpu_transcoder),
7308 (adjusted_mode->crtc_hsync_start - 1) |
7309 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7311 I915_WRITE(VTOTAL(cpu_transcoder),
7312 (adjusted_mode->crtc_vdisplay - 1) |
7313 ((crtc_vtotal - 1) << 16));
7314 I915_WRITE(VBLANK(cpu_transcoder),
7315 (adjusted_mode->crtc_vblank_start - 1) |
7316 ((crtc_vblank_end - 1) << 16));
7317 I915_WRITE(VSYNC(cpu_transcoder),
7318 (adjusted_mode->crtc_vsync_start - 1) |
7319 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7321 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7322 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7323 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7324 * bits. */
7325 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7326 (pipe == PIPE_B || pipe == PIPE_C))
7327 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7329 }
7331 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7332 {
7333 struct drm_device *dev = intel_crtc->base.dev;
7334 struct drm_i915_private *dev_priv = to_i915(dev);
7335 enum pipe pipe = intel_crtc->pipe;
7337 /* pipesrc controls the size that is scaled from, which should
7338 * always be the user's requested size.
7339 */
7340 I915_WRITE(PIPESRC(pipe),
7341 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7342 (intel_crtc->config->pipe_src_h - 1));
7343 }
7345 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7346 struct intel_crtc_state *pipe_config)
7347 {
7348 struct drm_device *dev = crtc->base.dev;
7349 struct drm_i915_private *dev_priv = to_i915(dev);
7350 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7351 uint32_t tmp;
7353 tmp = I915_READ(HTOTAL(cpu_transcoder));
7354 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7355 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7356 tmp = I915_READ(HBLANK(cpu_transcoder));
7357 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7358 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7359 tmp = I915_READ(HSYNC(cpu_transcoder));
7360 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7361 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7363 tmp = I915_READ(VTOTAL(cpu_transcoder));
7364 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7365 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7366 tmp = I915_READ(VBLANK(cpu_transcoder));
7367 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7368 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7369 tmp = I915_READ(VSYNC(cpu_transcoder));
7370 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7371 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7373 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7374 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7375 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7376 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7377 }
7378 }
7380 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7381 struct intel_crtc_state *pipe_config)
7382 {
7383 struct drm_device *dev = crtc->base.dev;
7384 struct drm_i915_private *dev_priv = to_i915(dev);
7385 u32 tmp;
7387 tmp = I915_READ(PIPESRC(crtc->pipe));
7388 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7389 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7391 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7392 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7393 }
7395 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7396 struct intel_crtc_state *pipe_config)
7397 {
7398 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7399 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7400 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7401 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7403 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7404 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7405 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7406 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7408 mode->flags = pipe_config->base.adjusted_mode.flags;
7409 mode->type = DRM_MODE_TYPE_DRIVER;
7411 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7413 mode->hsync = drm_mode_hsync(mode);
7414 mode->vrefresh = drm_mode_vrefresh(mode);
7415 drm_mode_set_name(mode);
7416 }
7418 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7419 {
7420 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7421 uint32_t pipeconf;
7423 pipeconf = 0;
7425 /* we keep both pipes enabled on 830 */
7426 if (IS_I830(dev_priv))
7427 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7429 if (intel_crtc->config->double_wide)
7430 pipeconf |= PIPECONF_DOUBLE_WIDE;
7432 /* only g4x and later have fancy bpc/dither controls */
7433 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7434 IS_CHERRYVIEW(dev_priv)) {
7435 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7436 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7437 pipeconf |= PIPECONF_DITHER_EN |
7438 PIPECONF_DITHER_TYPE_SP;
7440 switch (intel_crtc->config->pipe_bpp) {
7441 case 18:
7442 pipeconf |= PIPECONF_6BPC;
7443 break;
7444 case 24:
7445 pipeconf |= PIPECONF_8BPC;
7446 break;
7447 case 30:
7448 pipeconf |= PIPECONF_10BPC;
7449 break;
7450 default:
7451 /* Case prevented by intel_choose_pipe_bpp_dither. */
7452 BUG();
7453 }
7454 }
7456 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7457 if (INTEL_GEN(dev_priv) < 4 ||
7458 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7459 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7460 else
7461 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7462 } else
7463 pipeconf |= PIPECONF_PROGRESSIVE;
7465 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7466 intel_crtc->config->limited_color_range)
7467 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7469 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7470 POSTING_READ(PIPECONF(intel_crtc->pipe));
7471 }
7473 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7474 struct intel_crtc_state *crtc_state)
7475 {
7476 struct drm_device *dev = crtc->base.dev;
7477 struct drm_i915_private *dev_priv = to_i915(dev);
7478 const struct intel_limit *limit;
7479 int refclk = 48000;
7481 memset(&crtc_state->dpll_hw_state, 0,
7482 sizeof(crtc_state->dpll_hw_state));
7484 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7485 if (intel_panel_use_ssc(dev_priv)) {
7486 refclk = dev_priv->vbt.lvds_ssc_freq;
7487 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7488 }
7490 limit = &intel_limits_i8xx_lvds;
7491 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7492 limit = &intel_limits_i8xx_dvo;
7493 } else {
7494 limit = &intel_limits_i8xx_dac;
7495 }
7497 if (!crtc_state->clock_set &&
7498 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7499 refclk, NULL, &crtc_state->dpll)) {
7500 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7501 return -EINVAL;
7502 }
7504 i8xx_compute_dpll(crtc, crtc_state, NULL);
7506 return 0;
7507 }
7509 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7510 struct intel_crtc_state *crtc_state)
7511 {
7512 struct drm_device *dev = crtc->base.dev;
7513 struct drm_i915_private *dev_priv = to_i915(dev);
7514 const struct intel_limit *limit;
7515 int refclk = 96000;
7517 memset(&crtc_state->dpll_hw_state, 0,
7518 sizeof(crtc_state->dpll_hw_state));
7520 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7521 if (intel_panel_use_ssc(dev_priv)) {
7522 refclk = dev_priv->vbt.lvds_ssc_freq;
7523 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7524 }
7526 if (intel_is_dual_link_lvds(dev))
7527 limit = &intel_limits_g4x_dual_channel_lvds;
7528 else
7529 limit = &intel_limits_g4x_single_channel_lvds;
7530 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7531 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7532 limit = &intel_limits_g4x_hdmi;
7533 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7534 limit = &intel_limits_g4x_sdvo;
7535 } else {
7536 /* The option is for other outputs */
7537 limit = &intel_limits_i9xx_sdvo;
7538 }
7540 if (!crtc_state->clock_set &&
7541 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7542 refclk, NULL, &crtc_state->dpll)) {
7543 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7544 return -EINVAL;
7545 }
7547 i9xx_compute_dpll(crtc, crtc_state, NULL);
7549 return 0;
7550 }
7552 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7553 struct intel_crtc_state *crtc_state)
7554 {
7555 struct drm_device *dev = crtc->base.dev;
7556 struct drm_i915_private *dev_priv = to_i915(dev);
7557 const struct intel_limit *limit;
7558 int refclk = 96000;
7560 memset(&crtc_state->dpll_hw_state, 0,
7561 sizeof(crtc_state->dpll_hw_state));
7563 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7564 if (intel_panel_use_ssc(dev_priv)) {
7565 refclk = dev_priv->vbt.lvds_ssc_freq;
7566 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7567 }
7569 limit = &intel_limits_pineview_lvds;
7570 } else {
7571 limit = &intel_limits_pineview_sdvo;
7572 }
7574 if (!crtc_state->clock_set &&
7575 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7576 refclk, NULL, &crtc_state->dpll)) {
7577 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7578 return -EINVAL;
7579 }
7581 i9xx_compute_dpll(crtc, crtc_state, NULL);
7583 return 0;
7584 }
7586 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7587 struct intel_crtc_state *crtc_state)
7588 {
7589 struct drm_device *dev = crtc->base.dev;
7590 struct drm_i915_private *dev_priv = to_i915(dev);
7591 const struct intel_limit *limit;
7592 int refclk = 96000;
7594 memset(&crtc_state->dpll_hw_state, 0,
7595 sizeof(crtc_state->dpll_hw_state));
7597 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7598 if (intel_panel_use_ssc(dev_priv)) {
7599 refclk = dev_priv->vbt.lvds_ssc_freq;
7600 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7601 }
7603 limit = &intel_limits_i9xx_lvds;
7604 } else {
7605 limit = &intel_limits_i9xx_sdvo;
7606 }
7608 if (!crtc_state->clock_set &&
7609 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7610 refclk, NULL, &crtc_state->dpll)) {
7611 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7612 return -EINVAL;
7613 }
7615 i9xx_compute_dpll(crtc, crtc_state, NULL);
7617 return 0;
7618 }
7620 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7621 struct intel_crtc_state *crtc_state)
7622 {
7623 int refclk = 100000;
7624 const struct intel_limit *limit = &intel_limits_chv;
7626 memset(&crtc_state->dpll_hw_state, 0,
7627 sizeof(crtc_state->dpll_hw_state));
7629 if (!crtc_state->clock_set &&
7630 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7631 refclk, NULL, &crtc_state->dpll)) {
7632 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7633 return -EINVAL;
7634 }
7636 chv_compute_dpll(crtc, crtc_state);
7638 return 0;
7639 }
7641 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7642 struct intel_crtc_state *crtc_state)
7643 {
7644 int refclk = 100000;
7645 const struct intel_limit *limit = &intel_limits_vlv;
7647 memset(&crtc_state->dpll_hw_state, 0,
7648 sizeof(crtc_state->dpll_hw_state));
7650 if (!crtc_state->clock_set &&
7651 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7652 refclk, NULL, &crtc_state->dpll)) {
7653 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7654 return -EINVAL;
7655 }
7657 vlv_compute_dpll(crtc, crtc_state);
7659 return 0;
7660 }
7662 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7663 struct intel_crtc_state *pipe_config)
7664 {
7665 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7666 uint32_t tmp;
7668 if (INTEL_GEN(dev_priv) <= 3 &&
7669 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7670 return;
7672 tmp = I915_READ(PFIT_CONTROL);
7673 if (!(tmp & PFIT_ENABLE))
7674 return;
7676 /* Check whether the pfit is attached to our pipe. */
7677 if (INTEL_GEN(dev_priv) < 4) {
7678 if (crtc->pipe != PIPE_B)
7679 return;
7680 } else {
7681 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7682 return;
7683 }
7685 pipe_config->gmch_pfit.control = tmp;
7686 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7687 }
7689 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7690 struct intel_crtc_state *pipe_config)
7691 {
7692 struct drm_device *dev = crtc->base.dev;
7693 struct drm_i915_private *dev_priv = to_i915(dev);
7694 int pipe = pipe_config->cpu_transcoder;
7695 struct dpll clock;
7696 u32 mdiv;
7697 int refclk = 100000;
7699 /* In case of DSI, DPLL will not be used */
7700 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7701 return;
7703 mutex_lock(&dev_priv->sb_lock);
7704 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7705 mutex_unlock(&dev_priv->sb_lock);
7707 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7708 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7709 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7710 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7711 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7713 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7714 }
7716 static void
7717 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7718 struct intel_initial_plane_config *plane_config)
7719 {
7720 struct drm_device *dev = crtc->base.dev;
7721 struct drm_i915_private *dev_priv = to_i915(dev);
7722 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7723 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7724 enum pipe pipe;
7725 u32 val, base, offset;
7726 int fourcc, pixel_format;
7727 unsigned int aligned_height;
7728 struct drm_framebuffer *fb;
7729 struct intel_framebuffer *intel_fb;
7731 if (!plane->get_hw_state(plane, &pipe))
7732 return;
7734 WARN_ON(pipe != crtc->pipe);
7736 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7737 if (!intel_fb) {
7738 DRM_DEBUG_KMS("failed to alloc fb\n");
7739 return;
7740 }
7742 fb = &intel_fb->base;
7744 fb->dev = dev;
7746 val = I915_READ(DSPCNTR(i9xx_plane));
7748 if (INTEL_GEN(dev_priv) >= 4) {
7749 if (val & DISPPLANE_TILED) {
7750 plane_config->tiling = I915_TILING_X;
7751 fb->modifier = I915_FORMAT_MOD_X_TILED;
7752 }
7753 }
7755 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7756 fourcc = i9xx_format_to_fourcc(pixel_format);
7757 fb->format = drm_format_info(fourcc);
7759 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7760 offset = I915_READ(DSPOFFSET(i9xx_plane));
7761 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7762 } else if (INTEL_GEN(dev_priv) >= 4) {
7763 if (plane_config->tiling)
7764 offset = I915_READ(DSPTILEOFF(i9xx_plane));
7765 else
7766 offset = I915_READ(DSPLINOFF(i9xx_plane));
7767 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7768 } else {
7769 base = I915_READ(DSPADDR(i9xx_plane));
7770 }
7771 plane_config->base = base;
7773 val = I915_READ(PIPESRC(pipe));
7774 fb->width = ((val >> 16) & 0xfff) + 1;
7775 fb->height = ((val >> 0) & 0xfff) + 1;
7777 val = I915_READ(DSPSTRIDE(i9xx_plane));
7778 fb->pitches[0] = val & 0xffffffc0;
7780 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7782 plane_config->size = fb->pitches[0] * aligned_height;
7784 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7785 crtc->base.name, plane->base.name, fb->width, fb->height,
7786 fb->format->cpp[0] * 8, base, fb->pitches[0],
7787 plane_config->size);
7789 plane_config->fb = intel_fb;
7790 }
7792 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7793 struct intel_crtc_state *pipe_config)
7794 {
7795 struct drm_device *dev = crtc->base.dev;
7796 struct drm_i915_private *dev_priv = to_i915(dev);
7797 int pipe = pipe_config->cpu_transcoder;
7798 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7799 struct dpll clock;
7800 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7801 int refclk = 100000;
7803 /* In case of DSI, DPLL will not be used */
7804 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7805 return;
7807 mutex_lock(&dev_priv->sb_lock);
7808 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7809 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7810 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7811 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7812 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7813 mutex_unlock(&dev_priv->sb_lock);
7815 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7816 clock.m2 = (pll_dw0 & 0xff) << 22;
7817 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7818 clock.m2 |= pll_dw2 & 0x3fffff;
7819 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7820 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7821 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7823 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7824 }
7826 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7827 struct intel_crtc_state *pipe_config)
7828 {
7829 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7830 enum intel_display_power_domain power_domain;
7831 uint32_t tmp;
7832 bool ret;
7834 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7835 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7836 return false;
7838 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7839 pipe_config->shared_dpll = NULL;
7841 ret = false;
7843 tmp = I915_READ(PIPECONF(crtc->pipe));
7844 if (!(tmp & PIPECONF_ENABLE))
7845 goto out;
7847 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7848 IS_CHERRYVIEW(dev_priv)) {
7849 switch (tmp & PIPECONF_BPC_MASK) {
7850 case PIPECONF_6BPC:
7851 pipe_config->pipe_bpp = 18;
7852 break;
7853 case PIPECONF_8BPC:
7854 pipe_config->pipe_bpp = 24;
7855 break;
7856 case PIPECONF_10BPC:
7857 pipe_config->pipe_bpp = 30;
7858 break;
7859 default:
7860 break;
7861 }
7862 }
7864 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7865 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7866 pipe_config->limited_color_range = true;
7868 if (INTEL_GEN(dev_priv) < 4)
7869 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7871 intel_get_pipe_timings(crtc, pipe_config);
7872 intel_get_pipe_src_size(crtc, pipe_config);
7874 i9xx_get_pfit_config(crtc, pipe_config);
7876 if (INTEL_GEN(dev_priv) >= 4) {
7877 /* No way to read it out on pipes B and C */
7878 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7879 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7880 else
7881 tmp = I915_READ(DPLL_MD(crtc->pipe));
7882 pipe_config->pixel_multiplier =
7883 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7884 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7885 pipe_config->dpll_hw_state.dpll_md = tmp;
7886 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7887 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7888 tmp = I915_READ(DPLL(crtc->pipe));
7889 pipe_config->pixel_multiplier =
7890 ((tmp & SDVO_MULTIPLIER_MASK)
7891 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7892 } else {
7893 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7894 * port and will be fixed up in the encoder->get_config
7895 * function. */
7896 pipe_config->pixel_multiplier = 1;
7897 }
7898 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7899 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7900 /*
7901 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7902 * on 830. Filter it out here so that we don't
7903 * report errors due to that.
7904 */
7905 if (IS_I830(dev_priv))
7906 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7908 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7909 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7910 } else {
7911 /* Mask out read-only status bits. */
7912 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7913 DPLL_PORTC_READY_MASK |
7914 DPLL_PORTB_READY_MASK);
7915 }
7917 if (IS_CHERRYVIEW(dev_priv))
7918 chv_crtc_clock_get(crtc, pipe_config);
7919 else if (IS_VALLEYVIEW(dev_priv))
7920 vlv_crtc_clock_get(crtc, pipe_config);
7921 else
7922 i9xx_crtc_clock_get(crtc, pipe_config);
7924 /*
7925 * Normally the dotclock is filled in by the encoder .get_config()
7926 * but in case the pipe is enabled w/o any ports we need a sane
7927 * default.
7928 */
7929 pipe_config->base.adjusted_mode.crtc_clock =
7930 pipe_config->port_clock / pipe_config->pixel_multiplier;
7932 ret = true;
7934 out:
7935 intel_display_power_put(dev_priv, power_domain);
7937 return ret;
7938 }
7940 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7941 {
7942 struct intel_encoder *encoder;
7943 int i;
7944 u32 val, final;
7945 bool has_lvds = false;
7946 bool has_cpu_edp = false;
7947 bool has_panel = false;
7948 bool has_ck505 = false;
7949 bool can_ssc = false;
7950 bool using_ssc_source = false;
7952 /* We need to take the global config into account */
7953 for_each_intel_encoder(&dev_priv->drm, encoder) {
7954 switch (encoder->type) {
7955 case INTEL_OUTPUT_LVDS:
7956 has_panel = true;
7957 has_lvds = true;
7958 break;
7959 case INTEL_OUTPUT_EDP:
7960 has_panel = true;
7961 if (encoder->port == PORT_A)
7962 has_cpu_edp = true;
7963 break;
7964 default:
7965 break;
7966 }
7967 }
7969 if (HAS_PCH_IBX(dev_priv)) {
7970 has_ck505 = dev_priv->vbt.display_clock_mode;
7971 can_ssc = has_ck505;
7972 } else {
7973 has_ck505 = false;
7974 can_ssc = true;
7975 }
7977 /* Check if any DPLLs are using the SSC source */
7978 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7979 u32 temp = I915_READ(PCH_DPLL(i));
7981 if (!(temp & DPLL_VCO_ENABLE))
7982 continue;
7984 if ((temp & PLL_REF_INPUT_MASK) ==
7985 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7986 using_ssc_source = true;
7987 break;
7988 }
7989 }
7991 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7992 has_panel, has_lvds, has_ck505, using_ssc_source);
7994 /* Ironlake: try to setup display ref clock before DPLL
7995 * enabling. This is only under driver's control after
7996 * PCH B stepping, previous chipset stepping should be
7997 * ignoring this setting.
7998 */
7999 val = I915_READ(PCH_DREF_CONTROL);
8001 /* As we must carefully and slowly disable/enable each source in turn,
8002 * compute the final state we want first and check if we need to
8003 * make any changes at all.
8004 */
8005 final = val;
8006 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8007 if (has_ck505)
8008 final |= DREF_NONSPREAD_CK505_ENABLE;
8009 else
8010 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8012 final &= ~DREF_SSC_SOURCE_MASK;
8013 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8014 final &= ~DREF_SSC1_ENABLE;
8016 if (has_panel) {
8017 final |= DREF_SSC_SOURCE_ENABLE;
8019 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8020 final |= DREF_SSC1_ENABLE;
8022 if (has_cpu_edp) {
8023 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8024 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8025 else
8026 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8027 } else
8028 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8029 } else if (using_ssc_source) {
8030 final |= DREF_SSC_SOURCE_ENABLE;
8031 final |= DREF_SSC1_ENABLE;
8032 }
8034 if (final == val)
8035 return;
8037 /* Always enable nonspread source */
8038 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8040 if (has_ck505)
8041 val |= DREF_NONSPREAD_CK505_ENABLE;
8042 else
8043 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8045 if (has_panel) {
8046 val &= ~DREF_SSC_SOURCE_MASK;
8047 val |= DREF_SSC_SOURCE_ENABLE;
8049 /* SSC must be turned on before enabling the CPU output */
8050 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8051 DRM_DEBUG_KMS("Using SSC on panel\n");
8052 val |= DREF_SSC1_ENABLE;
8053 } else
8054 val &= ~DREF_SSC1_ENABLE;
8056 /* Get SSC going before enabling the outputs */
8057 I915_WRITE(PCH_DREF_CONTROL, val);
8058 POSTING_READ(PCH_DREF_CONTROL);
8059 udelay(200);
8061 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8063 /* Enable CPU source on CPU attached eDP */
8064 if (has_cpu_edp) {
8065 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8066 DRM_DEBUG_KMS("Using SSC on eDP\n");
8067 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8068 } else
8069 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8070 } else
8071 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8073 I915_WRITE(PCH_DREF_CONTROL, val);
8074 POSTING_READ(PCH_DREF_CONTROL);
8075 udelay(200);
8076 } else {
8077 DRM_DEBUG_KMS("Disabling CPU source output\n");
8079 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8081 /* Turn off CPU output */
8082 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8084 I915_WRITE(PCH_DREF_CONTROL, val);
8085 POSTING_READ(PCH_DREF_CONTROL);
8086 udelay(200);
8088 if (!using_ssc_source) {
8089 DRM_DEBUG_KMS("Disabling SSC source\n");
8091 /* Turn off the SSC source */
8092 val &= ~DREF_SSC_SOURCE_MASK;
8093 val |= DREF_SSC_SOURCE_DISABLE;
8095 /* Turn off SSC1 */
8096 val &= ~DREF_SSC1_ENABLE;
8098 I915_WRITE(PCH_DREF_CONTROL, val);
8099 POSTING_READ(PCH_DREF_CONTROL);
8100 udelay(200);
8101 }
8102 }
8104 BUG_ON(val != final);
8105 }
8107 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8108 {
8109 uint32_t tmp;
8111 tmp = I915_READ(SOUTH_CHICKEN2);
8112 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8113 I915_WRITE(SOUTH_CHICKEN2, tmp);
8115 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8116 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8117 DRM_ERROR("FDI mPHY reset assert timeout\n");
8119 tmp = I915_READ(SOUTH_CHICKEN2);
8120 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8121 I915_WRITE(SOUTH_CHICKEN2, tmp);
8123 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8124 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8125 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8126 }
8128 /* WaMPhyProgramming:hsw */
8129 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8130 {
8131 uint32_t tmp;
8133 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8134 tmp &= ~(0xFF << 24);
8135 tmp |= (0x12 << 24);
8136 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8138 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8139 tmp |= (1 << 11);
8140 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8142 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8143 tmp |= (1 << 11);
8144 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8146 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8147 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8148 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8150 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8151 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8152 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8154 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8155 tmp &= ~(7 << 13);
8156 tmp |= (5 << 13);
8157 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8159 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8160 tmp &= ~(7 << 13);
8161 tmp |= (5 << 13);
8162 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8164 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8165 tmp &= ~0xFF;
8166 tmp |= 0x1C;
8167 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8169 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8170 tmp &= ~0xFF;
8171 tmp |= 0x1C;
8172 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8174 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8175 tmp &= ~(0xFF << 16);
8176 tmp |= (0x1C << 16);
8177 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8179 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8180 tmp &= ~(0xFF << 16);
8181 tmp |= (0x1C << 16);
8182 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8184 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8185 tmp |= (1 << 27);
8186 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8188 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8189 tmp |= (1 << 27);
8190 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8192 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8193 tmp &= ~(0xF << 28);
8194 tmp |= (4 << 28);
8195 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8197 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8198 tmp &= ~(0xF << 28);
8199 tmp |= (4 << 28);
8200 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8201 }
8203 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8204 * Programming" based on the parameters passed:
8205 * - Sequence to enable CLKOUT_DP
8206 * - Sequence to enable CLKOUT_DP without spread
8207 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8208 */
8209 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8210 bool with_spread, bool with_fdi)
8211 {
8212 uint32_t reg, tmp;
8214 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8215 with_spread = true;
8216 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8217 with_fdi, "LP PCH doesn't have FDI\n"))
8218 with_fdi = false;
8220 mutex_lock(&dev_priv->sb_lock);
8222 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8223 tmp &= ~SBI_SSCCTL_DISABLE;
8224 tmp |= SBI_SSCCTL_PATHALT;
8225 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8227 udelay(24);
8229 if (with_spread) {
8230 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8231 tmp &= ~SBI_SSCCTL_PATHALT;
8232 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8234 if (with_fdi) {
8235 lpt_reset_fdi_mphy(dev_priv);
8236 lpt_program_fdi_mphy(dev_priv);
8237 }
8238 }
8240 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8241 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8242 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8243 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8245 mutex_unlock(&dev_priv->sb_lock);
8246 }
8248 /* Sequence to disable CLKOUT_DP */
8249 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8250 {
8251 uint32_t reg, tmp;
8253 mutex_lock(&dev_priv->sb_lock);
8255 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8256 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8257 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8258 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8260 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8261 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8262 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8263 tmp |= SBI_SSCCTL_PATHALT;
8264 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8265 udelay(32);
8266 }
8267 tmp |= SBI_SSCCTL_DISABLE;
8268 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8269 }
8271 mutex_unlock(&dev_priv->sb_lock);
8272 }
8274 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8276 static const uint16_t sscdivintphase[] = {
8277 [BEND_IDX( 50)] = 0x3B23,
8278 [BEND_IDX( 45)] = 0x3B23,
8279 [BEND_IDX( 40)] = 0x3C23,
8280 [BEND_IDX( 35)] = 0x3C23,
8281 [BEND_IDX( 30)] = 0x3D23,
8282 [BEND_IDX( 25)] = 0x3D23,
8283 [BEND_IDX( 20)] = 0x3E23,
8284 [BEND_IDX( 15)] = 0x3E23,
8285 [BEND_IDX( 10)] = 0x3F23,
8286 [BEND_IDX( 5)] = 0x3F23,
8287 [BEND_IDX( 0)] = 0x0025,
8288 [BEND_IDX( -5)] = 0x0025,
8289 [BEND_IDX(-10)] = 0x0125,
8290 [BEND_IDX(-15)] = 0x0125,
8291 [BEND_IDX(-20)] = 0x0225,
8292 [BEND_IDX(-25)] = 0x0225,
8293 [BEND_IDX(-30)] = 0x0325,
8294 [BEND_IDX(-35)] = 0x0325,
8295 [BEND_IDX(-40)] = 0x0425,
8296 [BEND_IDX(-45)] = 0x0425,
8297 [BEND_IDX(-50)] = 0x0525,
8298 };
8300 /*
8301 * Bend CLKOUT_DP
8302 * steps -50 to 50 inclusive, in steps of 5
8303 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8304 * change in clock period = -(steps / 10) * 5.787 ps
8305 */
8306 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8307 {
8308 uint32_t tmp;
8309 int idx = BEND_IDX(steps);
8311 if (WARN_ON(steps % 5 != 0))
8312 return;
8314 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8315 return;
8317 mutex_lock(&dev_priv->sb_lock);
8319 if (steps % 10 != 0)
8320 tmp = 0xAAAAAAAB;
8321 else
8322 tmp = 0x00000000;
8323 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8325 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8326 tmp &= 0xffff0000;
8327 tmp |= sscdivintphase[idx];
8328 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8330 mutex_unlock(&dev_priv->sb_lock);
8331 }
8333 #undef BEND_IDX
8335 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8336 {
8337 struct intel_encoder *encoder;
8338 bool has_vga = false;
8340 for_each_intel_encoder(&dev_priv->drm, encoder) {
8341 switch (encoder->type) {
8342 case INTEL_OUTPUT_ANALOG:
8343 has_vga = true;
8344 break;
8345 default:
8346 break;
8347 }
8348 }
8350 if (has_vga) {
8351 lpt_bend_clkout_dp(dev_priv, 0);
8352 lpt_enable_clkout_dp(dev_priv, true, true);
8353 } else {
8354 lpt_disable_clkout_dp(dev_priv);
8355 }
8356 }
8358 /*
8359 * Initialize reference clocks when the driver loads
8360 */
8361 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8362 {
8363 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8364 ironlake_init_pch_refclk(dev_priv);
8365 else if (HAS_PCH_LPT(dev_priv))
8366 lpt_init_pch_refclk(dev_priv);
8367 }
8369 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8370 {
8371 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8373 int pipe = intel_crtc->pipe;
8374 uint32_t val;
8376 val = 0;
8378 switch (intel_crtc->config->pipe_bpp) {
8379 case 18:
8380 val |= PIPECONF_6BPC;
8381 break;
8382 case 24:
8383 val |= PIPECONF_8BPC;
8384 break;
8385 case 30:
8386 val |= PIPECONF_10BPC;
8387 break;
8388 case 36:
8389 val |= PIPECONF_12BPC;
8390 break;
8391 default:
8392 /* Case prevented by intel_choose_pipe_bpp_dither. */
8393 BUG();
8394 }
8396 if (intel_crtc->config->dither)
8397 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8399 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8400 val |= PIPECONF_INTERLACED_ILK;
8401 else
8402 val |= PIPECONF_PROGRESSIVE;
8404 if (intel_crtc->config->limited_color_range)
8405 val |= PIPECONF_COLOR_RANGE_SELECT;
8407 I915_WRITE(PIPECONF(pipe), val);
8408 POSTING_READ(PIPECONF(pipe));
8409 }
8411 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8412 {
8413 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8415 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8416 u32 val = 0;
8418 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8419 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8421 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8422 val |= PIPECONF_INTERLACED_ILK;
8423 else
8424 val |= PIPECONF_PROGRESSIVE;
8426 I915_WRITE(PIPECONF(cpu_transcoder), val);
8427 POSTING_READ(PIPECONF(cpu_transcoder));
8428 }
8430 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8431 {
8432 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8434 struct intel_crtc_state *config = intel_crtc->config;
8436 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8437 u32 val = 0;
8439 switch (intel_crtc->config->pipe_bpp) {
8440 case 18:
8441 val |= PIPEMISC_DITHER_6_BPC;
8442 break;
8443 case 24:
8444 val |= PIPEMISC_DITHER_8_BPC;
8445 break;
8446 case 30:
8447 val |= PIPEMISC_DITHER_10_BPC;
8448 break;
8449 case 36:
8450 val |= PIPEMISC_DITHER_12_BPC;
8451 break;
8452 default:
8453 /* Case prevented by pipe_config_set_bpp. */
8454 BUG();
8455 }
8457 if (intel_crtc->config->dither)
8458 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8460 if (config->ycbcr420) {
8461 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8462 PIPEMISC_YUV420_ENABLE |
8463 PIPEMISC_YUV420_MODE_FULL_BLEND;
8464 }
8466 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8467 }
8468 }
8470 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8471 {
8472 /*
8473 * Account for spread spectrum to avoid
8474 * oversubscribing the link. Max center spread
8475 * is 2.5%; use 5% for safety's sake.
8476 */
8477 u32 bps = target_clock * bpp * 21 / 20;
8478 return DIV_ROUND_UP(bps, link_bw * 8);
8479 }
8481 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8482 {
8483 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8484 }
8486 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8487 struct intel_crtc_state *crtc_state,
8488 struct dpll *reduced_clock)
8489 {
8490 struct drm_crtc *crtc = &intel_crtc->base;
8491 struct drm_device *dev = crtc->dev;
8492 struct drm_i915_private *dev_priv = to_i915(dev);
8493 u32 dpll, fp, fp2;
8494 int factor;
8496 /* Enable autotuning of the PLL clock (if permissible) */
8497 factor = 21;
8498 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8499 if ((intel_panel_use_ssc(dev_priv) &&
8500 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8501 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8502 factor = 25;
8503 } else if (crtc_state->sdvo_tv_clock)
8504 factor = 20;
8506 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8508 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8509 fp |= FP_CB_TUNE;
8511 if (reduced_clock) {
8512 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8514 if (reduced_clock->m < factor * reduced_clock->n)
8515 fp2 |= FP_CB_TUNE;
8516 } else {
8517 fp2 = fp;
8518 }
8520 dpll = 0;
8522 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8523 dpll |= DPLLB_MODE_LVDS;
8524 else
8525 dpll |= DPLLB_MODE_DAC_SERIAL;
8527 dpll |= (crtc_state->pixel_multiplier - 1)
8528 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8530 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8531 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8532 dpll |= DPLL_SDVO_HIGH_SPEED;
8534 if (intel_crtc_has_dp_encoder(crtc_state))
8535 dpll |= DPLL_SDVO_HIGH_SPEED;
8537 /*
8538 * The high speed IO clock is only really required for
8539 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8540 * possible to share the DPLL between CRT and HDMI. Enabling
8541 * the clock needlessly does no real harm, except use up a
8542 * bit of power potentially.
8543 *
8544 * We'll limit this to IVB with 3 pipes, since it has only two
8545 * DPLLs and so DPLL sharing is the only way to get three pipes
8546 * driving PCH ports at the same time. On SNB we could do this,
8547 * and potentially avoid enabling the second DPLL, but it's not
8548 * clear if it''s a win or loss power wise. No point in doing
8549 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8550 */
8551 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8552 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8553 dpll |= DPLL_SDVO_HIGH_SPEED;
8555 /* compute bitmask from p1 value */
8556 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8557 /* also FPA1 */
8558 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8560 switch (crtc_state->dpll.p2) {
8561 case 5:
8562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8563 break;
8564 case 7:
8565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8566 break;
8567 case 10:
8568 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8569 break;
8570 case 14:
8571 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8572 break;
8573 }
8575 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8576 intel_panel_use_ssc(dev_priv))
8577 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8578 else
8579 dpll |= PLL_REF_INPUT_DREFCLK;
8581 dpll |= DPLL_VCO_ENABLE;
8583 crtc_state->dpll_hw_state.dpll = dpll;
8584 crtc_state->dpll_hw_state.fp0 = fp;
8585 crtc_state->dpll_hw_state.fp1 = fp2;
8586 }
8588 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8589 struct intel_crtc_state *crtc_state)
8590 {
8591 struct drm_device *dev = crtc->base.dev;
8592 struct drm_i915_private *dev_priv = to_i915(dev);
8593 const struct intel_limit *limit;
8594 int refclk = 120000;
8596 memset(&crtc_state->dpll_hw_state, 0,
8597 sizeof(crtc_state->dpll_hw_state));
8599 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8600 if (!crtc_state->has_pch_encoder)
8601 return 0;
8603 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8604 if (intel_panel_use_ssc(dev_priv)) {
8605 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8606 dev_priv->vbt.lvds_ssc_freq);
8607 refclk = dev_priv->vbt.lvds_ssc_freq;
8608 }
8610 if (intel_is_dual_link_lvds(dev)) {
8611 if (refclk == 100000)
8612 limit = &intel_limits_ironlake_dual_lvds_100m;
8613 else
8614 limit = &intel_limits_ironlake_dual_lvds;
8615 } else {
8616 if (refclk == 100000)
8617 limit = &intel_limits_ironlake_single_lvds_100m;
8618 else
8619 limit = &intel_limits_ironlake_single_lvds;
8620 }
8621 } else {
8622 limit = &intel_limits_ironlake_dac;
8623 }
8625 if (!crtc_state->clock_set &&
8626 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8627 refclk, NULL, &crtc_state->dpll)) {
8628 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8629 return -EINVAL;
8630 }
8632 ironlake_compute_dpll(crtc, crtc_state, NULL);
8634 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8635 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8636 pipe_name(crtc->pipe));
8637 return -EINVAL;
8638 }
8640 return 0;
8641 }
8643 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8644 struct intel_link_m_n *m_n)
8645 {
8646 struct drm_device *dev = crtc->base.dev;
8647 struct drm_i915_private *dev_priv = to_i915(dev);
8648 enum pipe pipe = crtc->pipe;
8650 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8651 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8652 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8653 & ~TU_SIZE_MASK;
8654 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8655 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8656 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8657 }
8659 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8660 enum transcoder transcoder,
8661 struct intel_link_m_n *m_n,
8662 struct intel_link_m_n *m2_n2)
8663 {
8664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8665 enum pipe pipe = crtc->pipe;
8667 if (INTEL_GEN(dev_priv) >= 5) {
8668 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8669 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8670 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8671 & ~TU_SIZE_MASK;
8672 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8673 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8674 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8675 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8676 * gen < 8) and if DRRS is supported (to make sure the
8677 * registers are not unnecessarily read).
8678 */
8679 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8680 crtc->config->has_drrs) {
8681 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8682 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8683 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8684 & ~TU_SIZE_MASK;
8685 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8686 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8687 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8688 }
8689 } else {
8690 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8691 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8692 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8693 & ~TU_SIZE_MASK;
8694 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8695 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8696 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8697 }
8698 }
8700 void intel_dp_get_m_n(struct intel_crtc *crtc,
8701 struct intel_crtc_state *pipe_config)
8702 {
8703 if (pipe_config->has_pch_encoder)
8704 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8705 else
8706 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8707 &pipe_config->dp_m_n,
8708 &pipe_config->dp_m2_n2);
8709 }
8711 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8712 struct intel_crtc_state *pipe_config)
8713 {
8714 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8715 &pipe_config->fdi_m_n, NULL);
8716 }
8718 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8719 struct intel_crtc_state *pipe_config)
8720 {
8721 struct drm_device *dev = crtc->base.dev;
8722 struct drm_i915_private *dev_priv = to_i915(dev);
8723 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8724 uint32_t ps_ctrl = 0;
8725 int id = -1;
8726 int i;
8728 /* find scaler attached to this pipe */
8729 for (i = 0; i < crtc->num_scalers; i++) {
8730 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8731 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8732 id = i;
8733 pipe_config->pch_pfit.enabled = true;
8734 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8735 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8736 break;
8737 }
8738 }
8740 scaler_state->scaler_id = id;
8741 if (id >= 0) {
8742 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8743 } else {
8744 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8745 }
8746 }
8748 static void
8749 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8750 struct intel_initial_plane_config *plane_config)
8751 {
8752 struct drm_device *dev = crtc->base.dev;
8753 struct drm_i915_private *dev_priv = to_i915(dev);
8754 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8755 enum plane_id plane_id = plane->id;
8756 enum pipe pipe;
8757 u32 val, base, offset, stride_mult, tiling, alpha;
8758 int fourcc, pixel_format;
8759 unsigned int aligned_height;
8760 struct drm_framebuffer *fb;
8761 struct intel_framebuffer *intel_fb;
8763 if (!plane->get_hw_state(plane, &pipe))
8764 return;
8766 WARN_ON(pipe != crtc->pipe);
8768 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8769 if (!intel_fb) {
8770 DRM_DEBUG_KMS("failed to alloc fb\n");
8771 return;
8772 }
8774 fb = &intel_fb->base;
8776 fb->dev = dev;
8778 val = I915_READ(PLANE_CTL(pipe, plane_id));
8780 if (INTEL_GEN(dev_priv) >= 11)
8781 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8782 else
8783 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8785 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8786 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8787 alpha &= PLANE_COLOR_ALPHA_MASK;
8788 } else {
8789 alpha = val & PLANE_CTL_ALPHA_MASK;
8790 }
8792 fourcc = skl_format_to_fourcc(pixel_format,
8793 val & PLANE_CTL_ORDER_RGBX, alpha);
8794 fb->format = drm_format_info(fourcc);
8796 tiling = val & PLANE_CTL_TILED_MASK;
8797 switch (tiling) {
8798 case PLANE_CTL_TILED_LINEAR:
8799 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8800 break;
8801 case PLANE_CTL_TILED_X:
8802 plane_config->tiling = I915_TILING_X;
8803 fb->modifier = I915_FORMAT_MOD_X_TILED;
8804 break;
8805 case PLANE_CTL_TILED_Y:
8806 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8807 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8808 else
8809 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8810 break;
8811 case PLANE_CTL_TILED_YF:
8812 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8813 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8814 else
8815 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8816 break;
8817 default:
8818 MISSING_CASE(tiling);
8819 goto error;
8820 }
8822 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8823 plane_config->base = base;
8825 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8827 val = I915_READ(PLANE_SIZE(pipe, plane_id));
8828 fb->height = ((val >> 16) & 0xfff) + 1;
8829 fb->width = ((val >> 0) & 0x1fff) + 1;
8831 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8832 stride_mult = intel_fb_stride_alignment(fb, 0);
8833 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8835 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8837 plane_config->size = fb->pitches[0] * aligned_height;
8839 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8840 crtc->base.name, plane->base.name, fb->width, fb->height,
8841 fb->format->cpp[0] * 8, base, fb->pitches[0],
8842 plane_config->size);
8844 plane_config->fb = intel_fb;
8845 return;
8847 error:
8848 kfree(intel_fb);
8849 }
8851 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8852 struct intel_crtc_state *pipe_config)
8853 {
8854 struct drm_device *dev = crtc->base.dev;
8855 struct drm_i915_private *dev_priv = to_i915(dev);
8856 uint32_t tmp;
8858 tmp = I915_READ(PF_CTL(crtc->pipe));
8860 if (tmp & PF_ENABLE) {
8861 pipe_config->pch_pfit.enabled = true;
8862 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8863 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8865 /* We currently do not free assignements of panel fitters on
8866 * ivb/hsw (since we don't use the higher upscaling modes which
8867 * differentiates them) so just WARN about this case for now. */
8868 if (IS_GEN7(dev_priv)) {
8869 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8870 PF_PIPE_SEL_IVB(crtc->pipe));
8871 }
8872 }
8873 }
8875 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8876 struct intel_crtc_state *pipe_config)
8877 {
8878 struct drm_device *dev = crtc->base.dev;
8879 struct drm_i915_private *dev_priv = to_i915(dev);
8880 enum intel_display_power_domain power_domain;
8881 uint32_t tmp;
8882 bool ret;
8884 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8885 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8886 return false;
8888 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8889 pipe_config->shared_dpll = NULL;
8891 ret = false;
8892 tmp = I915_READ(PIPECONF(crtc->pipe));
8893 if (!(tmp & PIPECONF_ENABLE))
8894 goto out;
8896 switch (tmp & PIPECONF_BPC_MASK) {
8897 case PIPECONF_6BPC:
8898 pipe_config->pipe_bpp = 18;
8899 break;
8900 case PIPECONF_8BPC:
8901 pipe_config->pipe_bpp = 24;
8902 break;
8903 case PIPECONF_10BPC:
8904 pipe_config->pipe_bpp = 30;
8905 break;
8906 case PIPECONF_12BPC:
8907 pipe_config->pipe_bpp = 36;
8908 break;
8909 default:
8910 break;
8911 }
8913 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8914 pipe_config->limited_color_range = true;
8916 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8917 struct intel_shared_dpll *pll;
8918 enum intel_dpll_id pll_id;
8920 pipe_config->has_pch_encoder = true;
8922 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8923 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8924 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8926 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8928 if (HAS_PCH_IBX(dev_priv)) {
8929 /*
8930 * The pipe->pch transcoder and pch transcoder->pll
8931 * mapping is fixed.
8932 */
8933 pll_id = (enum intel_dpll_id) crtc->pipe;
8934 } else {
8935 tmp = I915_READ(PCH_DPLL_SEL);
8936 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8937 pll_id = DPLL_ID_PCH_PLL_B;
8938 else
8939 pll_id= DPLL_ID_PCH_PLL_A;
8940 }
8942 pipe_config->shared_dpll =
8943 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8944 pll = pipe_config->shared_dpll;
8946 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
8947 &pipe_config->dpll_hw_state));
8949 tmp = pipe_config->dpll_hw_state.dpll;
8950 pipe_config->pixel_multiplier =
8951 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8952 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8954 ironlake_pch_clock_get(crtc, pipe_config);
8955 } else {
8956 pipe_config->pixel_multiplier = 1;
8957 }
8959 intel_get_pipe_timings(crtc, pipe_config);
8960 intel_get_pipe_src_size(crtc, pipe_config);
8962 ironlake_get_pfit_config(crtc, pipe_config);
8964 ret = true;
8966 out:
8967 intel_display_power_put(dev_priv, power_domain);
8969 return ret;
8970 }
8972 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8973 {
8974 struct drm_device *dev = &dev_priv->drm;
8975 struct intel_crtc *crtc;
8977 for_each_intel_crtc(dev, crtc)
8978 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8979 pipe_name(crtc->pipe));
8981 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8982 "Display power well on\n");
8983 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8984 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8985 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8986 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8987 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8988 "CPU PWM1 enabled\n");
8989 if (IS_HASWELL(dev_priv))
8990 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8991 "CPU PWM2 enabled\n");
8992 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8993 "PCH PWM1 enabled\n");
8994 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8995 "Utility pin enabled\n");
8996 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8998 /*
8999 * In theory we can still leave IRQs enabled, as long as only the HPD
9000 * interrupts remain enabled. We used to check for that, but since it's
9001 * gen-specific and since we only disable LCPLL after we fully disable
9002 * the interrupts, the check below should be enough.
9003 */
9004 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9005 }
9007 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9008 {
9009 if (IS_HASWELL(dev_priv))
9010 return I915_READ(D_COMP_HSW);
9011 else
9012 return I915_READ(D_COMP_BDW);
9013 }
9015 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9016 {
9017 if (IS_HASWELL(dev_priv)) {
9018 mutex_lock(&dev_priv->pcu_lock);
9019 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9020 val))
9021 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9022 mutex_unlock(&dev_priv->pcu_lock);
9023 } else {
9024 I915_WRITE(D_COMP_BDW, val);
9025 POSTING_READ(D_COMP_BDW);
9026 }
9027 }
9029 /*
9030 * This function implements pieces of two sequences from BSpec:
9031 * - Sequence for display software to disable LCPLL
9032 * - Sequence for display software to allow package C8+
9033 * The steps implemented here are just the steps that actually touch the LCPLL
9034 * register. Callers should take care of disabling all the display engine
9035 * functions, doing the mode unset, fixing interrupts, etc.
9036 */
9037 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9038 bool switch_to_fclk, bool allow_power_down)
9039 {
9040 uint32_t val;
9042 assert_can_disable_lcpll(dev_priv);
9044 val = I915_READ(LCPLL_CTL);
9046 if (switch_to_fclk) {
9047 val |= LCPLL_CD_SOURCE_FCLK;
9048 I915_WRITE(LCPLL_CTL, val);
9050 if (wait_for_us(I915_READ(LCPLL_CTL) &
9051 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9052 DRM_ERROR("Switching to FCLK failed\n");
9054 val = I915_READ(LCPLL_CTL);
9055 }
9057 val |= LCPLL_PLL_DISABLE;
9058 I915_WRITE(LCPLL_CTL, val);
9059 POSTING_READ(LCPLL_CTL);
9061 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9062 DRM_ERROR("LCPLL still locked\n");
9064 val = hsw_read_dcomp(dev_priv);
9065 val |= D_COMP_COMP_DISABLE;
9066 hsw_write_dcomp(dev_priv, val);
9067 ndelay(100);
9069 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9070 1))
9071 DRM_ERROR("D_COMP RCOMP still in progress\n");
9073 if (allow_power_down) {
9074 val = I915_READ(LCPLL_CTL);
9075 val |= LCPLL_POWER_DOWN_ALLOW;
9076 I915_WRITE(LCPLL_CTL, val);
9077 POSTING_READ(LCPLL_CTL);
9078 }
9079 }
9081 /*
9082 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9083 * source.
9084 */
9085 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9086 {
9087 uint32_t val;
9089 val = I915_READ(LCPLL_CTL);
9091 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9092 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9093 return;
9095 /*
9096 * Make sure we're not on PC8 state before disabling PC8, otherwise
9097 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9098 */
9099 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9101 if (val & LCPLL_POWER_DOWN_ALLOW) {
9102 val &= ~LCPLL_POWER_DOWN_ALLOW;
9103 I915_WRITE(LCPLL_CTL, val);
9104 POSTING_READ(LCPLL_CTL);
9105 }
9107 val = hsw_read_dcomp(dev_priv);
9108 val |= D_COMP_COMP_FORCE;
9109 val &= ~D_COMP_COMP_DISABLE;
9110 hsw_write_dcomp(dev_priv, val);
9112 val = I915_READ(LCPLL_CTL);
9113 val &= ~LCPLL_PLL_DISABLE;
9114 I915_WRITE(LCPLL_CTL, val);
9116 if (intel_wait_for_register(dev_priv,
9117 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9118 5))
9119 DRM_ERROR("LCPLL not locked yet\n");
9121 if (val & LCPLL_CD_SOURCE_FCLK) {
9122 val = I915_READ(LCPLL_CTL);
9123 val &= ~LCPLL_CD_SOURCE_FCLK;
9124 I915_WRITE(LCPLL_CTL, val);
9126 if (wait_for_us((I915_READ(LCPLL_CTL) &
9127 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9128 DRM_ERROR("Switching back to LCPLL failed\n");
9129 }
9131 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9133 intel_update_cdclk(dev_priv);
9134 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9135 }
9137 /*
9138 * Package states C8 and deeper are really deep PC states that can only be
9139 * reached when all the devices on the system allow it, so even if the graphics
9140 * device allows PC8+, it doesn't mean the system will actually get to these
9141 * states. Our driver only allows PC8+ when going into runtime PM.
9142 *
9143 * The requirements for PC8+ are that all the outputs are disabled, the power
9144 * well is disabled and most interrupts are disabled, and these are also
9145 * requirements for runtime PM. When these conditions are met, we manually do
9146 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9147 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9148 * hang the machine.
9149 *
9150 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9151 * the state of some registers, so when we come back from PC8+ we need to
9152 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9153 * need to take care of the registers kept by RC6. Notice that this happens even
9154 * if we don't put the device in PCI D3 state (which is what currently happens
9155 * because of the runtime PM support).
9156 *
9157 * For more, read "Display Sequences for Package C8" on the hardware
9158 * documentation.
9159 */
9160 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9161 {
9162 uint32_t val;
9164 DRM_DEBUG_KMS("Enabling package C8+\n");
9166 if (HAS_PCH_LPT_LP(dev_priv)) {
9167 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9168 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9169 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9170 }
9172 lpt_disable_clkout_dp(dev_priv);
9173 hsw_disable_lcpll(dev_priv, true, true);
9174 }
9176 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9177 {
9178 uint32_t val;
9180 DRM_DEBUG_KMS("Disabling package C8+\n");
9182 hsw_restore_lcpll(dev_priv);
9183 lpt_init_pch_refclk(dev_priv);
9185 if (HAS_PCH_LPT_LP(dev_priv)) {
9186 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9187 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9188 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9189 }
9190 }
9192 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9193 struct intel_crtc_state *crtc_state)
9194 {
9195 struct intel_atomic_state *state =
9196 to_intel_atomic_state(crtc_state->base.state);
9198 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9199 struct intel_encoder *encoder =
9200 intel_get_crtc_new_encoder(state, crtc_state);
9202 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9203 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9204 pipe_name(crtc->pipe));
9205 return -EINVAL;
9206 }
9207 }
9209 return 0;
9210 }
9212 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9213 enum port port,
9214 struct intel_crtc_state *pipe_config)
9215 {
9216 enum intel_dpll_id id;
9217 u32 temp;
9219 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9220 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9222 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9223 return;
9225 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9226 }
9228 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9229 enum port port,
9230 struct intel_crtc_state *pipe_config)
9231 {
9232 enum intel_dpll_id id;
9233 u32 temp;
9235 /* TODO: TBT pll not implemented. */
9236 switch (port) {
9237 case PORT_A:
9238 case PORT_B:
9239 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9240 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9241 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9243 if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
9244 return;
9245 break;
9246 case PORT_C:
9247 id = DPLL_ID_ICL_MGPLL1;
9248 break;
9249 case PORT_D:
9250 id = DPLL_ID_ICL_MGPLL2;
9251 break;
9252 case PORT_E:
9253 id = DPLL_ID_ICL_MGPLL3;
9254 break;
9255 case PORT_F:
9256 id = DPLL_ID_ICL_MGPLL4;
9257 break;
9258 default:
9259 MISSING_CASE(port);
9260 return;
9261 }
9263 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9264 }
9266 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9267 enum port port,
9268 struct intel_crtc_state *pipe_config)
9269 {
9270 enum intel_dpll_id id;
9272 switch (port) {
9273 case PORT_A:
9274 id = DPLL_ID_SKL_DPLL0;
9275 break;
9276 case PORT_B:
9277 id = DPLL_ID_SKL_DPLL1;
9278 break;
9279 case PORT_C:
9280 id = DPLL_ID_SKL_DPLL2;
9281 break;
9282 default:
9283 DRM_ERROR("Incorrect port type\n");
9284 return;
9285 }
9287 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9288 }
9290 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9291 enum port port,
9292 struct intel_crtc_state *pipe_config)
9293 {
9294 enum intel_dpll_id id;
9295 u32 temp;
9297 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9298 id = temp >> (port * 3 + 1);
9300 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9301 return;
9303 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9304 }
9306 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9307 enum port port,
9308 struct intel_crtc_state *pipe_config)
9309 {
9310 enum intel_dpll_id id;
9311 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9313 switch (ddi_pll_sel) {
9314 case PORT_CLK_SEL_WRPLL1:
9315 id = DPLL_ID_WRPLL1;
9316 break;
9317 case PORT_CLK_SEL_WRPLL2:
9318 id = DPLL_ID_WRPLL2;
9319 break;
9320 case PORT_CLK_SEL_SPLL:
9321 id = DPLL_ID_SPLL;
9322 break;
9323 case PORT_CLK_SEL_LCPLL_810:
9324 id = DPLL_ID_LCPLL_810;
9325 break;
9326 case PORT_CLK_SEL_LCPLL_1350:
9327 id = DPLL_ID_LCPLL_1350;
9328 break;
9329 case PORT_CLK_SEL_LCPLL_2700:
9330 id = DPLL_ID_LCPLL_2700;
9331 break;
9332 default:
9333 MISSING_CASE(ddi_pll_sel);
9334 /* fall through */
9335 case PORT_CLK_SEL_NONE:
9336 return;
9337 }
9339 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9340 }
9342 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9343 struct intel_crtc_state *pipe_config,
9344 u64 *power_domain_mask)
9345 {
9346 struct drm_device *dev = crtc->base.dev;
9347 struct drm_i915_private *dev_priv = to_i915(dev);
9348 enum intel_display_power_domain power_domain;
9349 u32 tmp;
9351 /*
9352 * The pipe->transcoder mapping is fixed with the exception of the eDP
9353 * transcoder handled below.
9354 */
9355 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9357 /*
9358 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9359 * consistency and less surprising code; it's in always on power).
9360 */
9361 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9362 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9363 enum pipe trans_edp_pipe;
9364 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9365 default:
9366 WARN(1, "unknown pipe linked to edp transcoder\n");
9367 /* fall through */
9368 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9369 case TRANS_DDI_EDP_INPUT_A_ON:
9370 trans_edp_pipe = PIPE_A;
9371 break;
9372 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9373 trans_edp_pipe = PIPE_B;
9374 break;
9375 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9376 trans_edp_pipe = PIPE_C;
9377 break;
9378 }
9380 if (trans_edp_pipe == crtc->pipe)
9381 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9382 }
9384 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9385 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9386 return false;
9387 *power_domain_mask |= BIT_ULL(power_domain);
9389 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9391 return tmp & PIPECONF_ENABLE;
9392 }
9394 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9395 struct intel_crtc_state *pipe_config,
9396 u64 *power_domain_mask)
9397 {
9398 struct drm_device *dev = crtc->base.dev;
9399 struct drm_i915_private *dev_priv = to_i915(dev);
9400 enum intel_display_power_domain power_domain;
9401 enum port port;
9402 enum transcoder cpu_transcoder;
9403 u32 tmp;
9405 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9406 if (port == PORT_A)
9407 cpu_transcoder = TRANSCODER_DSI_A;
9408 else
9409 cpu_transcoder = TRANSCODER_DSI_C;
9411 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9412 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9413 continue;
9414 *power_domain_mask |= BIT_ULL(power_domain);
9416 /*
9417 * The PLL needs to be enabled with a valid divider
9418 * configuration, otherwise accessing DSI registers will hang
9419 * the machine. See BSpec North Display Engine
9420 * registers/MIPI[BXT]. We can break out here early, since we
9421 * need the same DSI PLL to be enabled for both DSI ports.
9422 */
9423 if (!bxt_dsi_pll_is_enabled(dev_priv))
9424 break;
9426 /* XXX: this works for video mode only */
9427 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9428 if (!(tmp & DPI_ENABLE))
9429 continue;
9431 tmp = I915_READ(MIPI_CTRL(port));
9432 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9433 continue;
9435 pipe_config->cpu_transcoder = cpu_transcoder;
9436 break;
9437 }
9439 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9440 }
9442 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9443 struct intel_crtc_state *pipe_config)
9444 {
9445 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9446 struct intel_shared_dpll *pll;
9447 enum port port;
9448 uint32_t tmp;
9450 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9452 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9454 if (IS_ICELAKE(dev_priv))
9455 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9456 else if (IS_CANNONLAKE(dev_priv))
9457 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9458 else if (IS_GEN9_BC(dev_priv))
9459 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9460 else if (IS_GEN9_LP(dev_priv))
9461 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9462 else
9463 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9465 pll = pipe_config->shared_dpll;
9466 if (pll) {
9467 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9468 &pipe_config->dpll_hw_state));
9469 }
9471 /*
9472 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9473 * DDI E. So just check whether this pipe is wired to DDI E and whether
9474 * the PCH transcoder is on.
9475 */
9476 if (INTEL_GEN(dev_priv) < 9 &&
9477 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9478 pipe_config->has_pch_encoder = true;
9480 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9481 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9482 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9484 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9485 }
9486 }
9488 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9489 struct intel_crtc_state *pipe_config)
9490 {
9491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9492 enum intel_display_power_domain power_domain;
9493 u64 power_domain_mask;
9494 bool active;
9496 intel_crtc_init_scalers(crtc, pipe_config);
9498 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9499 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9500 return false;
9501 power_domain_mask = BIT_ULL(power_domain);
9503 pipe_config->shared_dpll = NULL;
9505 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9507 if (IS_GEN9_LP(dev_priv) &&
9508 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9509 WARN_ON(active);
9510 active = true;
9511 }
9513 if (!active)
9514 goto out;
9516 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9517 haswell_get_ddi_port_state(crtc, pipe_config);
9518 intel_get_pipe_timings(crtc, pipe_config);
9519 }
9521 intel_get_pipe_src_size(crtc, pipe_config);
9523 pipe_config->gamma_mode =
9524 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9526 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9527 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9528 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9530 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9531 bool blend_mode_420 = tmp &
9532 PIPEMISC_YUV420_MODE_FULL_BLEND;
9534 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9535 if (pipe_config->ycbcr420 != clrspace_yuv ||
9536 pipe_config->ycbcr420 != blend_mode_420)
9537 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9538 } else if (clrspace_yuv) {
9539 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9540 }
9541 }
9543 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9544 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9545 power_domain_mask |= BIT_ULL(power_domain);
9546 if (INTEL_GEN(dev_priv) >= 9)
9547 skylake_get_pfit_config(crtc, pipe_config);
9548 else
9549 ironlake_get_pfit_config(crtc, pipe_config);
9550 }
9552 if (hsw_crtc_supports_ips(crtc)) {
9553 if (IS_HASWELL(dev_priv))
9554 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9555 else {
9556 /*
9557 * We cannot readout IPS state on broadwell, set to
9558 * true so we can set it to a defined state on first
9559 * commit.
9560 */
9561 pipe_config->ips_enabled = true;
9562 }
9563 }
9565 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9566 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9567 pipe_config->pixel_multiplier =
9568 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9569 } else {
9570 pipe_config->pixel_multiplier = 1;
9571 }
9573 out:
9574 for_each_power_domain(power_domain, power_domain_mask)
9575 intel_display_power_put(dev_priv, power_domain);
9577 return active;
9578 }
9580 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9581 {
9582 struct drm_i915_private *dev_priv =
9583 to_i915(plane_state->base.plane->dev);
9584 const struct drm_framebuffer *fb = plane_state->base.fb;
9585 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9586 u32 base;
9588 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9589 base = obj->phys_handle->busaddr;
9590 else
9591 base = intel_plane_ggtt_offset(plane_state);
9593 base += plane_state->main.offset;
9595 /* ILK+ do this automagically */
9596 if (HAS_GMCH_DISPLAY(dev_priv) &&
9597 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9598 base += (plane_state->base.crtc_h *
9599 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9601 return base;
9602 }
9604 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9605 {
9606 int x = plane_state->base.crtc_x;
9607 int y = plane_state->base.crtc_y;
9608 u32 pos = 0;
9610 if (x < 0) {
9611 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9612 x = -x;
9613 }
9614 pos |= x << CURSOR_X_SHIFT;
9616 if (y < 0) {
9617 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9618 y = -y;
9619 }
9620 pos |= y << CURSOR_Y_SHIFT;
9622 return pos;
9623 }
9625 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9626 {
9627 const struct drm_mode_config *config =
9628 &plane_state->base.plane->dev->mode_config;
9629 int width = plane_state->base.crtc_w;
9630 int height = plane_state->base.crtc_h;
9632 return width > 0 && width <= config->cursor_width &&
9633 height > 0 && height <= config->cursor_height;
9634 }
9636 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9637 struct intel_plane_state *plane_state)
9638 {
9639 const struct drm_framebuffer *fb = plane_state->base.fb;
9640 int src_x, src_y;
9641 u32 offset;
9642 int ret;
9644 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9645 &crtc_state->base,
9646 DRM_PLANE_HELPER_NO_SCALING,
9647 DRM_PLANE_HELPER_NO_SCALING,
9648 true, true);
9649 if (ret)
9650 return ret;
9652 if (!fb)
9653 return 0;
9655 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9656 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9657 return -EINVAL;
9658 }
9660 src_x = plane_state->base.src_x >> 16;
9661 src_y = plane_state->base.src_y >> 16;
9663 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9664 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9666 if (src_x != 0 || src_y != 0) {
9667 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9668 return -EINVAL;
9669 }
9671 plane_state->main.offset = offset;
9673 return 0;
9674 }
9676 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9677 const struct intel_plane_state *plane_state)
9678 {
9679 const struct drm_framebuffer *fb = plane_state->base.fb;
9681 return CURSOR_ENABLE |
9682 CURSOR_GAMMA_ENABLE |
9683 CURSOR_FORMAT_ARGB |
9684 CURSOR_STRIDE(fb->pitches[0]);
9685 }
9687 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9688 {
9689 int width = plane_state->base.crtc_w;
9691 /*
9692 * 845g/865g are only limited by the width of their cursors,
9693 * the height is arbitrary up to the precision of the register.
9694 */
9695 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9696 }
9698 static int i845_check_cursor(struct intel_plane *plane,
9699 struct intel_crtc_state *crtc_state,
9700 struct intel_plane_state *plane_state)
9701 {
9702 const struct drm_framebuffer *fb = plane_state->base.fb;
9703 int ret;
9705 ret = intel_check_cursor(crtc_state, plane_state);
9706 if (ret)
9707 return ret;
9709 /* if we want to turn off the cursor ignore width and height */
9710 if (!fb)
9711 return 0;
9713 /* Check for which cursor types we support */
9714 if (!i845_cursor_size_ok(plane_state)) {
9715 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9716 plane_state->base.crtc_w,
9717 plane_state->base.crtc_h);
9718 return -EINVAL;
9719 }
9721 switch (fb->pitches[0]) {
9722 case 256:
9723 case 512:
9724 case 1024:
9725 case 2048:
9726 break;
9727 default:
9728 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9729 fb->pitches[0]);
9730 return -EINVAL;
9731 }
9733 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9735 return 0;
9736 }
9738 static void i845_update_cursor(struct intel_plane *plane,
9739 const struct intel_crtc_state *crtc_state,
9740 const struct intel_plane_state *plane_state)
9741 {
9742 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9743 u32 cntl = 0, base = 0, pos = 0, size = 0;
9744 unsigned long irqflags;
9746 if (plane_state && plane_state->base.visible) {
9747 unsigned int width = plane_state->base.crtc_w;
9748 unsigned int height = plane_state->base.crtc_h;
9750 cntl = plane_state->ctl;
9751 size = (height << 12) | width;
9753 base = intel_cursor_base(plane_state);
9754 pos = intel_cursor_position(plane_state);
9755 }
9757 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9759 /* On these chipsets we can only modify the base/size/stride
9760 * whilst the cursor is disabled.
9761 */
9762 if (plane->cursor.base != base ||
9763 plane->cursor.size != size ||
9764 plane->cursor.cntl != cntl) {
9765 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9766 I915_WRITE_FW(CURBASE(PIPE_A), base);
9767 I915_WRITE_FW(CURSIZE, size);
9768 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9769 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9771 plane->cursor.base = base;
9772 plane->cursor.size = size;
9773 plane->cursor.cntl = cntl;
9774 } else {
9775 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9776 }
9778 POSTING_READ_FW(CURCNTR(PIPE_A));
9780 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9781 }
9783 static void i845_disable_cursor(struct intel_plane *plane,
9784 struct intel_crtc *crtc)
9785 {
9786 i845_update_cursor(plane, NULL, NULL);
9787 }
9789 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
9790 enum pipe *pipe)
9791 {
9792 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9793 enum intel_display_power_domain power_domain;
9794 bool ret;
9796 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9797 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9798 return false;
9800 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9802 *pipe = PIPE_A;
9804 intel_display_power_put(dev_priv, power_domain);
9806 return ret;
9807 }
9809 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9810 const struct intel_plane_state *plane_state)
9811 {
9812 struct drm_i915_private *dev_priv =
9813 to_i915(plane_state->base.plane->dev);
9814 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9815 u32 cntl = 0;
9817 if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
9818 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
9820 if (INTEL_GEN(dev_priv) <= 10) {
9821 cntl |= MCURSOR_GAMMA_ENABLE;
9823 if (HAS_DDI(dev_priv))
9824 cntl |= MCURSOR_PIPE_CSC_ENABLE;
9825 }
9827 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9828 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9830 switch (plane_state->base.crtc_w) {
9831 case 64:
9832 cntl |= MCURSOR_MODE_64_ARGB_AX;
9833 break;
9834 case 128:
9835 cntl |= MCURSOR_MODE_128_ARGB_AX;
9836 break;
9837 case 256:
9838 cntl |= MCURSOR_MODE_256_ARGB_AX;
9839 break;
9840 default:
9841 MISSING_CASE(plane_state->base.crtc_w);
9842 return 0;
9843 }
9845 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9846 cntl |= MCURSOR_ROTATE_180;
9848 return cntl;
9849 }
9851 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9852 {
9853 struct drm_i915_private *dev_priv =
9854 to_i915(plane_state->base.plane->dev);
9855 int width = plane_state->base.crtc_w;
9856 int height = plane_state->base.crtc_h;
9858 if (!intel_cursor_size_ok(plane_state))
9859 return false;
9861 /* Cursor width is limited to a few power-of-two sizes */
9862 switch (width) {
9863 case 256:
9864 case 128:
9865 case 64:
9866 break;
9867 default:
9868 return false;
9869 }
9871 /*
9872 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9873 * height from 8 lines up to the cursor width, when the
9874 * cursor is not rotated. Everything else requires square
9875 * cursors.
9876 */
9877 if (HAS_CUR_FBC(dev_priv) &&
9878 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9879 if (height < 8 || height > width)
9880 return false;
9881 } else {
9882 if (height != width)
9883 return false;
9884 }
9886 return true;
9887 }
9889 static int i9xx_check_cursor(struct intel_plane *plane,
9890 struct intel_crtc_state *crtc_state,
9891 struct intel_plane_state *plane_state)
9892 {
9893 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9894 const struct drm_framebuffer *fb = plane_state->base.fb;
9895 enum pipe pipe = plane->pipe;
9896 int ret;
9898 ret = intel_check_cursor(crtc_state, plane_state);
9899 if (ret)
9900 return ret;
9902 /* if we want to turn off the cursor ignore width and height */
9903 if (!fb)
9904 return 0;
9906 /* Check for which cursor types we support */
9907 if (!i9xx_cursor_size_ok(plane_state)) {
9908 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9909 plane_state->base.crtc_w,
9910 plane_state->base.crtc_h);
9911 return -EINVAL;
9912 }
9914 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9915 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9916 fb->pitches[0], plane_state->base.crtc_w);
9917 return -EINVAL;
9918 }
9920 /*
9921 * There's something wrong with the cursor on CHV pipe C.
9922 * If it straddles the left edge of the screen then
9923 * moving it away from the edge or disabling it often
9924 * results in a pipe underrun, and often that can lead to
9925 * dead pipe (constant underrun reported, and it scans
9926 * out just a solid color). To recover from that, the
9927 * display power well must be turned off and on again.
9928 * Refuse the put the cursor into that compromised position.
9929 */
9930 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9931 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9932 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9933 return -EINVAL;
9934 }
9936 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9938 return 0;
9939 }
9941 static void i9xx_update_cursor(struct intel_plane *plane,
9942 const struct intel_crtc_state *crtc_state,
9943 const struct intel_plane_state *plane_state)
9944 {
9945 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9946 enum pipe pipe = plane->pipe;
9947 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9948 unsigned long irqflags;
9950 if (plane_state && plane_state->base.visible) {
9951 cntl = plane_state->ctl;
9953 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9954 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9956 base = intel_cursor_base(plane_state);
9957 pos = intel_cursor_position(plane_state);
9958 }
9960 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9962 /*
9963 * On some platforms writing CURCNTR first will also
9964 * cause CURPOS to be armed by the CURBASE write.
9965 * Without the CURCNTR write the CURPOS write would
9966 * arm itself. Thus we always start the full update
9967 * with a CURCNTR write.
9968 *
9969 * On other platforms CURPOS always requires the
9970 * CURBASE write to arm the update. Additonally
9971 * a write to any of the cursor register will cancel
9972 * an already armed cursor update. Thus leaving out
9973 * the CURBASE write after CURPOS could lead to a
9974 * cursor that doesn't appear to move, or even change
9975 * shape. Thus we always write CURBASE.
9976 *
9977 * CURCNTR and CUR_FBC_CTL are always
9978 * armed by the CURBASE write only.
9979 */
9980 if (plane->cursor.base != base ||
9981 plane->cursor.size != fbc_ctl ||
9982 plane->cursor.cntl != cntl) {
9983 I915_WRITE_FW(CURCNTR(pipe), cntl);
9984 if (HAS_CUR_FBC(dev_priv))
9985 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9986 I915_WRITE_FW(CURPOS(pipe), pos);
9987 I915_WRITE_FW(CURBASE(pipe), base);
9989 plane->cursor.base = base;
9990 plane->cursor.size = fbc_ctl;
9991 plane->cursor.cntl = cntl;
9992 } else {
9993 I915_WRITE_FW(CURPOS(pipe), pos);
9994 I915_WRITE_FW(CURBASE(pipe), base);
9995 }
9997 POSTING_READ_FW(CURBASE(pipe));
9999 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10000 }
10002 static void i9xx_disable_cursor(struct intel_plane *plane,
10003 struct intel_crtc *crtc)
10004 {
10005 i9xx_update_cursor(plane, NULL, NULL);
10006 }
10008 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10009 enum pipe *pipe)
10010 {
10011 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10012 enum intel_display_power_domain power_domain;
10013 bool ret;
10014 u32 val;
10016 /*
10017 * Not 100% correct for planes that can move between pipes,
10018 * but that's only the case for gen2-3 which don't have any
10019 * display power wells.
10020 */
10021 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10022 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10023 return false;
10025 val = I915_READ(CURCNTR(plane->pipe));
10027 ret = val & MCURSOR_MODE;
10029 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10030 *pipe = plane->pipe;
10031 else
10032 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10033 MCURSOR_PIPE_SELECT_SHIFT;
10035 intel_display_power_put(dev_priv, power_domain);
10037 return ret;
10038 }
10040 /* VESA 640x480x72Hz mode to set on the pipe */
10041 static const struct drm_display_mode load_detect_mode = {
10042 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10043 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10044 };
10046 struct drm_framebuffer *
10047 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10048 struct drm_mode_fb_cmd2 *mode_cmd)
10049 {
10050 struct intel_framebuffer *intel_fb;
10051 int ret;
10053 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10054 if (!intel_fb)
10055 return ERR_PTR(-ENOMEM);
10057 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10058 if (ret)
10059 goto err;
10061 return &intel_fb->base;
10063 err:
10064 kfree(intel_fb);
10065 return ERR_PTR(ret);
10066 }
10068 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10069 struct drm_crtc *crtc)
10070 {
10071 struct drm_plane *plane;
10072 struct drm_plane_state *plane_state;
10073 int ret, i;
10075 ret = drm_atomic_add_affected_planes(state, crtc);
10076 if (ret)
10077 return ret;
10079 for_each_new_plane_in_state(state, plane, plane_state, i) {
10080 if (plane_state->crtc != crtc)
10081 continue;
10083 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10084 if (ret)
10085 return ret;
10087 drm_atomic_set_fb_for_plane(plane_state, NULL);
10088 }
10090 return 0;
10091 }
10093 int intel_get_load_detect_pipe(struct drm_connector *connector,
10094 const struct drm_display_mode *mode,
10095 struct intel_load_detect_pipe *old,
10096 struct drm_modeset_acquire_ctx *ctx)
10097 {
10098 struct intel_crtc *intel_crtc;
10099 struct intel_encoder *intel_encoder =
10100 intel_attached_encoder(connector);
10101 struct drm_crtc *possible_crtc;
10102 struct drm_encoder *encoder = &intel_encoder->base;
10103 struct drm_crtc *crtc = NULL;
10104 struct drm_device *dev = encoder->dev;
10105 struct drm_i915_private *dev_priv = to_i915(dev);
10106 struct drm_mode_config *config = &dev->mode_config;
10107 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10108 struct drm_connector_state *connector_state;
10109 struct intel_crtc_state *crtc_state;
10110 int ret, i = -1;
10112 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10113 connector->base.id, connector->name,
10114 encoder->base.id, encoder->name);
10116 old->restore_state = NULL;
10118 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10120 /*
10121 * Algorithm gets a little messy:
10122 *
10123 * - if the connector already has an assigned crtc, use it (but make
10124 * sure it's on first)
10125 *
10126 * - try to find the first unused crtc that can drive this connector,
10127 * and use that if we find one
10128 */
10130 /* See if we already have a CRTC for this connector */
10131 if (connector->state->crtc) {
10132 crtc = connector->state->crtc;
10134 ret = drm_modeset_lock(&crtc->mutex, ctx);
10135 if (ret)
10136 goto fail;
10138 /* Make sure the crtc and connector are running */
10139 goto found;
10140 }
10142 /* Find an unused one (if possible) */
10143 for_each_crtc(dev, possible_crtc) {
10144 i++;
10145 if (!(encoder->possible_crtcs & (1 << i)))
10146 continue;
10148 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10149 if (ret)
10150 goto fail;
10152 if (possible_crtc->state->enable) {
10153 drm_modeset_unlock(&possible_crtc->mutex);
10154 continue;
10155 }
10157 crtc = possible_crtc;
10158 break;
10159 }
10161 /*
10162 * If we didn't find an unused CRTC, don't use any.
10163 */
10164 if (!crtc) {
10165 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10166 ret = -ENODEV;
10167 goto fail;
10168 }
10170 found:
10171 intel_crtc = to_intel_crtc(crtc);
10173 state = drm_atomic_state_alloc(dev);
10174 restore_state = drm_atomic_state_alloc(dev);
10175 if (!state || !restore_state) {
10176 ret = -ENOMEM;
10177 goto fail;
10178 }
10180 state->acquire_ctx = ctx;
10181 restore_state->acquire_ctx = ctx;
10183 connector_state = drm_atomic_get_connector_state(state, connector);
10184 if (IS_ERR(connector_state)) {
10185 ret = PTR_ERR(connector_state);
10186 goto fail;
10187 }
10189 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10190 if (ret)
10191 goto fail;
10193 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10194 if (IS_ERR(crtc_state)) {
10195 ret = PTR_ERR(crtc_state);
10196 goto fail;
10197 }
10199 crtc_state->base.active = crtc_state->base.enable = true;
10201 if (!mode)
10202 mode = &load_detect_mode;
10204 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10205 if (ret)
10206 goto fail;
10208 ret = intel_modeset_disable_planes(state, crtc);
10209 if (ret)
10210 goto fail;
10212 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10213 if (!ret)
10214 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10215 if (!ret)
10216 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10217 if (ret) {
10218 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10219 goto fail;
10220 }
10222 ret = drm_atomic_commit(state);
10223 if (ret) {
10224 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10225 goto fail;
10226 }
10228 old->restore_state = restore_state;
10229 drm_atomic_state_put(state);
10231 /* let the connector get through one full cycle before testing */
10232 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10233 return true;
10235 fail:
10236 if (state) {
10237 drm_atomic_state_put(state);
10238 state = NULL;
10239 }
10240 if (restore_state) {
10241 drm_atomic_state_put(restore_state);
10242 restore_state = NULL;
10243 }
10245 if (ret == -EDEADLK)
10246 return ret;
10248 return false;
10249 }
10251 void intel_release_load_detect_pipe(struct drm_connector *connector,
10252 struct intel_load_detect_pipe *old,
10253 struct drm_modeset_acquire_ctx *ctx)
10254 {
10255 struct intel_encoder *intel_encoder =
10256 intel_attached_encoder(connector);
10257 struct drm_encoder *encoder = &intel_encoder->base;
10258 struct drm_atomic_state *state = old->restore_state;
10259 int ret;
10261 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10262 connector->base.id, connector->name,
10263 encoder->base.id, encoder->name);
10265 if (!state)
10266 return;
10268 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10269 if (ret)
10270 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10271 drm_atomic_state_put(state);
10272 }
10274 static int i9xx_pll_refclk(struct drm_device *dev,
10275 const struct intel_crtc_state *pipe_config)
10276 {
10277 struct drm_i915_private *dev_priv = to_i915(dev);
10278 u32 dpll = pipe_config->dpll_hw_state.dpll;
10280 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10281 return dev_priv->vbt.lvds_ssc_freq;
10282 else if (HAS_PCH_SPLIT(dev_priv))
10283 return 120000;
10284 else if (!IS_GEN2(dev_priv))
10285 return 96000;
10286 else
10287 return 48000;
10288 }
10290 /* Returns the clock of the currently programmed mode of the given pipe. */
10291 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10292 struct intel_crtc_state *pipe_config)
10293 {
10294 struct drm_device *dev = crtc->base.dev;
10295 struct drm_i915_private *dev_priv = to_i915(dev);
10296 int pipe = pipe_config->cpu_transcoder;
10297 u32 dpll = pipe_config->dpll_hw_state.dpll;
10298 u32 fp;
10299 struct dpll clock;
10300 int port_clock;
10301 int refclk = i9xx_pll_refclk(dev, pipe_config);
10303 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10304 fp = pipe_config->dpll_hw_state.fp0;
10305 else
10306 fp = pipe_config->dpll_hw_state.fp1;
10308 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10309 if (IS_PINEVIEW(dev_priv)) {
10310 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10311 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10312 } else {
10313 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10314 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10315 }
10317 if (!IS_GEN2(dev_priv)) {
10318 if (IS_PINEVIEW(dev_priv))
10319 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10320 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10321 else
10322 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10323 DPLL_FPA01_P1_POST_DIV_SHIFT);
10325 switch (dpll & DPLL_MODE_MASK) {
10326 case DPLLB_MODE_DAC_SERIAL:
10327 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10328 5 : 10;
10329 break;
10330 case DPLLB_MODE_LVDS:
10331 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10332 7 : 14;
10333 break;
10334 default:
10335 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10336 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10337 return;
10338 }
10340 if (IS_PINEVIEW(dev_priv))
10341 port_clock = pnv_calc_dpll_params(refclk, &clock);
10342 else
10343 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10344 } else {
10345 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10346 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10348 if (is_lvds) {
10349 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10350 DPLL_FPA01_P1_POST_DIV_SHIFT);
10352 if (lvds & LVDS_CLKB_POWER_UP)
10353 clock.p2 = 7;
10354 else
10355 clock.p2 = 14;
10356 } else {
10357 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10358 clock.p1 = 2;
10359 else {
10360 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10361 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10362 }
10363 if (dpll & PLL_P2_DIVIDE_BY_4)
10364 clock.p2 = 4;
10365 else
10366 clock.p2 = 2;
10367 }
10369 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10370 }
10372 /*
10373 * This value includes pixel_multiplier. We will use
10374 * port_clock to compute adjusted_mode.crtc_clock in the
10375 * encoder's get_config() function.
10376 */
10377 pipe_config->port_clock = port_clock;
10378 }
10380 int intel_dotclock_calculate(int link_freq,
10381 const struct intel_link_m_n *m_n)
10382 {
10383 /*
10384 * The calculation for the data clock is:
10385 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10386 * But we want to avoid losing precison if possible, so:
10387 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10388 *
10389 * and the link clock is simpler:
10390 * link_clock = (m * link_clock) / n
10391 */
10393 if (!m_n->link_n)
10394 return 0;
10396 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10397 }
10399 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10400 struct intel_crtc_state *pipe_config)
10401 {
10402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10404 /* read out port_clock from the DPLL */
10405 i9xx_crtc_clock_get(crtc, pipe_config);
10407 /*
10408 * In case there is an active pipe without active ports,
10409 * we may need some idea for the dotclock anyway.
10410 * Calculate one based on the FDI configuration.
10411 */
10412 pipe_config->base.adjusted_mode.crtc_clock =
10413 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10414 &pipe_config->fdi_m_n);
10415 }
10417 /* Returns the currently programmed mode of the given encoder. */
10418 struct drm_display_mode *
10419 intel_encoder_current_mode(struct intel_encoder *encoder)
10420 {
10421 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10422 struct intel_crtc_state *crtc_state;
10423 struct drm_display_mode *mode;
10424 struct intel_crtc *crtc;
10425 enum pipe pipe;
10427 if (!encoder->get_hw_state(encoder, &pipe))
10428 return NULL;
10430 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10432 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10433 if (!mode)
10434 return NULL;
10436 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10437 if (!crtc_state) {
10438 kfree(mode);
10439 return NULL;
10440 }
10442 crtc_state->base.crtc = &crtc->base;
10444 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10445 kfree(crtc_state);
10446 kfree(mode);
10447 return NULL;
10448 }
10450 encoder->get_config(encoder, crtc_state);
10452 intel_mode_from_pipe_config(mode, crtc_state);
10454 kfree(crtc_state);
10456 return mode;
10457 }
10459 static void intel_crtc_destroy(struct drm_crtc *crtc)
10460 {
10461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10463 drm_crtc_cleanup(crtc);
10464 kfree(intel_crtc);
10465 }
10467 /**
10468 * intel_wm_need_update - Check whether watermarks need updating
10469 * @plane: drm plane
10470 * @state: new plane state
10471 *
10472 * Check current plane state versus the new one to determine whether
10473 * watermarks need to be recalculated.
10474 *
10475 * Returns true or false.
10476 */
10477 static bool intel_wm_need_update(struct drm_plane *plane,
10478 struct drm_plane_state *state)
10479 {
10480 struct intel_plane_state *new = to_intel_plane_state(state);
10481 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10483 /* Update watermarks on tiling or size changes. */
10484 if (new->base.visible != cur->base.visible)
10485 return true;
10487 if (!cur->base.fb || !new->base.fb)
10488 return false;
10490 if (cur->base.fb->modifier != new->base.fb->modifier ||
10491 cur->base.rotation != new->base.rotation ||
10492 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10493 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10494 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10495 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10496 return true;
10498 return false;
10499 }
10501 static bool needs_scaling(const struct intel_plane_state *state)
10502 {
10503 int src_w = drm_rect_width(&state->base.src) >> 16;
10504 int src_h = drm_rect_height(&state->base.src) >> 16;
10505 int dst_w = drm_rect_width(&state->base.dst);
10506 int dst_h = drm_rect_height(&state->base.dst);
10508 return (src_w != dst_w || src_h != dst_h);
10509 }
10511 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10512 struct drm_crtc_state *crtc_state,
10513 const struct intel_plane_state *old_plane_state,
10514 struct drm_plane_state *plane_state)
10515 {
10516 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10517 struct drm_crtc *crtc = crtc_state->crtc;
10518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10519 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10520 struct drm_device *dev = crtc->dev;
10521 struct drm_i915_private *dev_priv = to_i915(dev);
10522 bool mode_changed = needs_modeset(crtc_state);
10523 bool was_crtc_enabled = old_crtc_state->base.active;
10524 bool is_crtc_enabled = crtc_state->active;
10525 bool turn_off, turn_on, visible, was_visible;
10526 struct drm_framebuffer *fb = plane_state->fb;
10527 int ret;
10529 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10530 ret = skl_update_scaler_plane(
10531 to_intel_crtc_state(crtc_state),
10532 to_intel_plane_state(plane_state));
10533 if (ret)
10534 return ret;
10535 }
10537 was_visible = old_plane_state->base.visible;
10538 visible = plane_state->visible;
10540 if (!was_crtc_enabled && WARN_ON(was_visible))
10541 was_visible = false;
10543 /*
10544 * Visibility is calculated as if the crtc was on, but
10545 * after scaler setup everything depends on it being off
10546 * when the crtc isn't active.
10547 *
10548 * FIXME this is wrong for watermarks. Watermarks should also
10549 * be computed as if the pipe would be active. Perhaps move
10550 * per-plane wm computation to the .check_plane() hook, and
10551 * only combine the results from all planes in the current place?
10552 */
10553 if (!is_crtc_enabled) {
10554 plane_state->visible = visible = false;
10555 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10556 }
10558 if (!was_visible && !visible)
10559 return 0;
10561 if (fb != old_plane_state->base.fb)
10562 pipe_config->fb_changed = true;
10564 turn_off = was_visible && (!visible || mode_changed);
10565 turn_on = visible && (!was_visible || mode_changed);
10567 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10568 intel_crtc->base.base.id, intel_crtc->base.name,
10569 plane->base.base.id, plane->base.name,
10570 fb ? fb->base.id : -1);
10572 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10573 plane->base.base.id, plane->base.name,
10574 was_visible, visible,
10575 turn_off, turn_on, mode_changed);
10577 if (turn_on) {
10578 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10579 pipe_config->update_wm_pre = true;
10581 /* must disable cxsr around plane enable/disable */
10582 if (plane->id != PLANE_CURSOR)
10583 pipe_config->disable_cxsr = true;
10584 } else if (turn_off) {
10585 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10586 pipe_config->update_wm_post = true;
10588 /* must disable cxsr around plane enable/disable */
10589 if (plane->id != PLANE_CURSOR)
10590 pipe_config->disable_cxsr = true;
10591 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10592 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10593 /* FIXME bollocks */
10594 pipe_config->update_wm_pre = true;
10595 pipe_config->update_wm_post = true;
10596 }
10597 }
10599 if (visible || was_visible)
10600 pipe_config->fb_bits |= plane->frontbuffer_bit;
10602 /*
10603 * WaCxSRDisabledForSpriteScaling:ivb
10604 *
10605 * cstate->update_wm was already set above, so this flag will
10606 * take effect when we commit and program watermarks.
10607 */
10608 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10609 needs_scaling(to_intel_plane_state(plane_state)) &&
10610 !needs_scaling(old_plane_state))
10611 pipe_config->disable_lp_wm = true;
10613 return 0;
10614 }
10616 static bool encoders_cloneable(const struct intel_encoder *a,
10617 const struct intel_encoder *b)
10618 {
10619 /* masks could be asymmetric, so check both ways */
10620 return a == b || (a->cloneable & (1 << b->type) &&
10621 b->cloneable & (1 << a->type));
10622 }
10624 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10625 struct intel_crtc *crtc,
10626 struct intel_encoder *encoder)
10627 {
10628 struct intel_encoder *source_encoder;
10629 struct drm_connector *connector;
10630 struct drm_connector_state *connector_state;
10631 int i;
10633 for_each_new_connector_in_state(state, connector, connector_state, i) {
10634 if (connector_state->crtc != &crtc->base)
10635 continue;
10637 source_encoder =
10638 to_intel_encoder(connector_state->best_encoder);
10639 if (!encoders_cloneable(encoder, source_encoder))
10640 return false;
10641 }
10643 return true;
10644 }
10646 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10647 struct drm_crtc_state *crtc_state)
10648 {
10649 struct drm_device *dev = crtc->dev;
10650 struct drm_i915_private *dev_priv = to_i915(dev);
10651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10652 struct intel_crtc_state *pipe_config =
10653 to_intel_crtc_state(crtc_state);
10654 struct drm_atomic_state *state = crtc_state->state;
10655 int ret;
10656 bool mode_changed = needs_modeset(crtc_state);
10658 if (mode_changed && !crtc_state->active)
10659 pipe_config->update_wm_post = true;
10661 if (mode_changed && crtc_state->enable &&
10662 dev_priv->display.crtc_compute_clock &&
10663 !WARN_ON(pipe_config->shared_dpll)) {
10664 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10665 pipe_config);
10666 if (ret)
10667 return ret;
10668 }
10670 if (crtc_state->color_mgmt_changed) {
10671 ret = intel_color_check(crtc, crtc_state);
10672 if (ret)
10673 return ret;
10675 /*
10676 * Changing color management on Intel hardware is
10677 * handled as part of planes update.
10678 */
10679 crtc_state->planes_changed = true;
10680 }
10682 ret = 0;
10683 if (dev_priv->display.compute_pipe_wm) {
10684 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10685 if (ret) {
10686 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10687 return ret;
10688 }
10689 }
10691 if (dev_priv->display.compute_intermediate_wm &&
10692 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10693 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10694 return 0;
10696 /*
10697 * Calculate 'intermediate' watermarks that satisfy both the
10698 * old state and the new state. We can program these
10699 * immediately.
10700 */
10701 ret = dev_priv->display.compute_intermediate_wm(dev,
10702 intel_crtc,
10703 pipe_config);
10704 if (ret) {
10705 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10706 return ret;
10707 }
10708 } else if (dev_priv->display.compute_intermediate_wm) {
10709 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10710 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10711 }
10713 if (INTEL_GEN(dev_priv) >= 9) {
10714 if (mode_changed)
10715 ret = skl_update_scaler_crtc(pipe_config);
10717 if (!ret)
10718 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10719 pipe_config);
10720 if (!ret)
10721 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10722 pipe_config);
10723 }
10725 if (HAS_IPS(dev_priv))
10726 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10728 return ret;
10729 }
10731 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10732 .atomic_begin = intel_begin_crtc_commit,
10733 .atomic_flush = intel_finish_crtc_commit,
10734 .atomic_check = intel_crtc_atomic_check,
10735 };
10737 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10738 {
10739 struct intel_connector *connector;
10740 struct drm_connector_list_iter conn_iter;
10742 drm_connector_list_iter_begin(dev, &conn_iter);
10743 for_each_intel_connector_iter(connector, &conn_iter) {
10744 if (connector->base.state->crtc)
10745 drm_connector_put(&connector->base);
10747 if (connector->base.encoder) {
10748 connector->base.state->best_encoder =
10749 connector->base.encoder;
10750 connector->base.state->crtc =
10751 connector->base.encoder->crtc;
10753 drm_connector_get(&connector->base);
10754 } else {
10755 connector->base.state->best_encoder = NULL;
10756 connector->base.state->crtc = NULL;
10757 }
10758 }
10759 drm_connector_list_iter_end(&conn_iter);
10760 }
10762 static void
10763 connected_sink_compute_bpp(struct intel_connector *connector,
10764 struct intel_crtc_state *pipe_config)
10765 {
10766 const struct drm_display_info *info = &connector->base.display_info;
10767 int bpp = pipe_config->pipe_bpp;
10769 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10770 connector->base.base.id,
10771 connector->base.name);
10773 /* Don't use an invalid EDID bpc value */
10774 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10775 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10776 bpp, info->bpc * 3);
10777 pipe_config->pipe_bpp = info->bpc * 3;
10778 }
10780 /* Clamp bpp to 8 on screens without EDID 1.4 */
10781 if (info->bpc == 0 && bpp > 24) {
10782 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10783 bpp);
10784 pipe_config->pipe_bpp = 24;
10785 }
10786 }
10788 static int
10789 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10790 struct intel_crtc_state *pipe_config)
10791 {
10792 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10793 struct drm_atomic_state *state;
10794 struct drm_connector *connector;
10795 struct drm_connector_state *connector_state;
10796 int bpp, i;
10798 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10799 IS_CHERRYVIEW(dev_priv)))
10800 bpp = 10*3;
10801 else if (INTEL_GEN(dev_priv) >= 5)
10802 bpp = 12*3;
10803 else
10804 bpp = 8*3;
10807 pipe_config->pipe_bpp = bpp;
10809 state = pipe_config->base.state;
10811 /* Clamp display bpp to EDID value */
10812 for_each_new_connector_in_state(state, connector, connector_state, i) {
10813 if (connector_state->crtc != &crtc->base)
10814 continue;
10816 connected_sink_compute_bpp(to_intel_connector(connector),
10817 pipe_config);
10818 }
10820 return bpp;
10821 }
10823 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10824 {
10825 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10826 "type: 0x%x flags: 0x%x\n",
10827 mode->crtc_clock,
10828 mode->crtc_hdisplay, mode->crtc_hsync_start,
10829 mode->crtc_hsync_end, mode->crtc_htotal,
10830 mode->crtc_vdisplay, mode->crtc_vsync_start,
10831 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10832 }
10834 static inline void
10835 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10836 unsigned int lane_count, struct intel_link_m_n *m_n)
10837 {
10838 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10839 id, lane_count,
10840 m_n->gmch_m, m_n->gmch_n,
10841 m_n->link_m, m_n->link_n, m_n->tu);
10842 }
10844 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10846 static const char * const output_type_str[] = {
10847 OUTPUT_TYPE(UNUSED),
10848 OUTPUT_TYPE(ANALOG),
10849 OUTPUT_TYPE(DVO),
10850 OUTPUT_TYPE(SDVO),
10851 OUTPUT_TYPE(LVDS),
10852 OUTPUT_TYPE(TVOUT),
10853 OUTPUT_TYPE(HDMI),
10854 OUTPUT_TYPE(DP),
10855 OUTPUT_TYPE(EDP),
10856 OUTPUT_TYPE(DSI),
10857 OUTPUT_TYPE(DDI),
10858 OUTPUT_TYPE(DP_MST),
10859 };
10861 #undef OUTPUT_TYPE
10863 static void snprintf_output_types(char *buf, size_t len,
10864 unsigned int output_types)
10865 {
10866 char *str = buf;
10867 int i;
10869 str[0] = '\0';
10871 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10872 int r;
10874 if ((output_types & BIT(i)) == 0)
10875 continue;
10877 r = snprintf(str, len, "%s%s",
10878 str != buf ? "," : "", output_type_str[i]);
10879 if (r >= len)
10880 break;
10881 str += r;
10882 len -= r;
10884 output_types &= ~BIT(i);
10885 }
10887 WARN_ON_ONCE(output_types != 0);
10888 }
10890 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10891 struct intel_crtc_state *pipe_config,
10892 const char *context)
10893 {
10894 struct drm_device *dev = crtc->base.dev;
10895 struct drm_i915_private *dev_priv = to_i915(dev);
10896 struct drm_plane *plane;
10897 struct intel_plane *intel_plane;
10898 struct intel_plane_state *state;
10899 struct drm_framebuffer *fb;
10900 char buf[64];
10902 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10903 crtc->base.base.id, crtc->base.name, context);
10905 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10906 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10907 buf, pipe_config->output_types);
10909 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10910 transcoder_name(pipe_config->cpu_transcoder),
10911 pipe_config->pipe_bpp, pipe_config->dither);
10913 if (pipe_config->has_pch_encoder)
10914 intel_dump_m_n_config(pipe_config, "fdi",
10915 pipe_config->fdi_lanes,
10916 &pipe_config->fdi_m_n);
10918 if (pipe_config->ycbcr420)
10919 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10921 if (intel_crtc_has_dp_encoder(pipe_config)) {
10922 intel_dump_m_n_config(pipe_config, "dp m_n",
10923 pipe_config->lane_count, &pipe_config->dp_m_n);
10924 if (pipe_config->has_drrs)
10925 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10926 pipe_config->lane_count,
10927 &pipe_config->dp_m2_n2);
10928 }
10930 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10931 pipe_config->has_audio, pipe_config->has_infoframe);
10933 DRM_DEBUG_KMS("requested mode:\n");
10934 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10935 DRM_DEBUG_KMS("adjusted mode:\n");
10936 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10937 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10938 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10939 pipe_config->port_clock,
10940 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10941 pipe_config->pixel_rate);
10943 if (INTEL_GEN(dev_priv) >= 9)
10944 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10945 crtc->num_scalers,
10946 pipe_config->scaler_state.scaler_users,
10947 pipe_config->scaler_state.scaler_id);
10949 if (HAS_GMCH_DISPLAY(dev_priv))
10950 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10951 pipe_config->gmch_pfit.control,
10952 pipe_config->gmch_pfit.pgm_ratios,
10953 pipe_config->gmch_pfit.lvds_border_bits);
10954 else
10955 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10956 pipe_config->pch_pfit.pos,
10957 pipe_config->pch_pfit.size,
10958 enableddisabled(pipe_config->pch_pfit.enabled));
10960 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10961 pipe_config->ips_enabled, pipe_config->double_wide);
10963 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10965 DRM_DEBUG_KMS("planes on this crtc\n");
10966 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10967 struct drm_format_name_buf format_name;
10968 intel_plane = to_intel_plane(plane);
10969 if (intel_plane->pipe != crtc->pipe)
10970 continue;
10972 state = to_intel_plane_state(plane->state);
10973 fb = state->base.fb;
10974 if (!fb) {
10975 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10976 plane->base.id, plane->name, state->scaler_id);
10977 continue;
10978 }
10980 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10981 plane->base.id, plane->name,
10982 fb->base.id, fb->width, fb->height,
10983 drm_get_format_name(fb->format->format, &format_name));
10984 if (INTEL_GEN(dev_priv) >= 9)
10985 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10986 state->scaler_id,
10987 state->base.src.x1 >> 16,
10988 state->base.src.y1 >> 16,
10989 drm_rect_width(&state->base.src) >> 16,
10990 drm_rect_height(&state->base.src) >> 16,
10991 state->base.dst.x1, state->base.dst.y1,
10992 drm_rect_width(&state->base.dst),
10993 drm_rect_height(&state->base.dst));
10994 }
10995 }
10997 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10998 {
10999 struct drm_device *dev = state->dev;
11000 struct drm_connector *connector;
11001 struct drm_connector_list_iter conn_iter;
11002 unsigned int used_ports = 0;
11003 unsigned int used_mst_ports = 0;
11004 bool ret = true;
11006 /*
11007 * Walk the connector list instead of the encoder
11008 * list to detect the problem on ddi platforms
11009 * where there's just one encoder per digital port.
11010 */
11011 drm_connector_list_iter_begin(dev, &conn_iter);
11012 drm_for_each_connector_iter(connector, &conn_iter) {
11013 struct drm_connector_state *connector_state;
11014 struct intel_encoder *encoder;
11016 connector_state = drm_atomic_get_new_connector_state(state, connector);
11017 if (!connector_state)
11018 connector_state = connector->state;
11020 if (!connector_state->best_encoder)
11021 continue;
11023 encoder = to_intel_encoder(connector_state->best_encoder);
11025 WARN_ON(!connector_state->crtc);
11027 switch (encoder->type) {
11028 unsigned int port_mask;
11029 case INTEL_OUTPUT_DDI:
11030 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11031 break;
11032 /* else: fall through */
11033 case INTEL_OUTPUT_DP:
11034 case INTEL_OUTPUT_HDMI:
11035 case INTEL_OUTPUT_EDP:
11036 port_mask = 1 << encoder->port;
11038 /* the same port mustn't appear more than once */
11039 if (used_ports & port_mask)
11040 ret = false;
11042 used_ports |= port_mask;
11043 break;
11044 case INTEL_OUTPUT_DP_MST:
11045 used_mst_ports |=
11046 1 << encoder->port;
11047 break;
11048 default:
11049 break;
11050 }
11051 }
11052 drm_connector_list_iter_end(&conn_iter);
11054 /* can't mix MST and SST/HDMI on the same port */
11055 if (used_ports & used_mst_ports)
11056 return false;
11058 return ret;
11059 }
11061 static void
11062 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11063 {
11064 struct drm_i915_private *dev_priv =
11065 to_i915(crtc_state->base.crtc->dev);
11066 struct intel_crtc_scaler_state scaler_state;
11067 struct intel_dpll_hw_state dpll_hw_state;
11068 struct intel_shared_dpll *shared_dpll;
11069 struct intel_crtc_wm_state wm_state;
11070 bool force_thru, ips_force_disable;
11072 /* FIXME: before the switch to atomic started, a new pipe_config was
11073 * kzalloc'd. Code that depends on any field being zero should be
11074 * fixed, so that the crtc_state can be safely duplicated. For now,
11075 * only fields that are know to not cause problems are preserved. */
11077 scaler_state = crtc_state->scaler_state;
11078 shared_dpll = crtc_state->shared_dpll;
11079 dpll_hw_state = crtc_state->dpll_hw_state;
11080 force_thru = crtc_state->pch_pfit.force_thru;
11081 ips_force_disable = crtc_state->ips_force_disable;
11082 if (IS_G4X(dev_priv) ||
11083 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11084 wm_state = crtc_state->wm;
11086 /* Keep base drm_crtc_state intact, only clear our extended struct */
11087 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11088 memset(&crtc_state->base + 1, 0,
11089 sizeof(*crtc_state) - sizeof(crtc_state->base));
11091 crtc_state->scaler_state = scaler_state;
11092 crtc_state->shared_dpll = shared_dpll;
11093 crtc_state->dpll_hw_state = dpll_hw_state;
11094 crtc_state->pch_pfit.force_thru = force_thru;
11095 crtc_state->ips_force_disable = ips_force_disable;
11096 if (IS_G4X(dev_priv) ||
11097 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11098 crtc_state->wm = wm_state;
11099 }
11101 static int
11102 intel_modeset_pipe_config(struct drm_crtc *crtc,
11103 struct intel_crtc_state *pipe_config)
11104 {
11105 struct drm_atomic_state *state = pipe_config->base.state;
11106 struct intel_encoder *encoder;
11107 struct drm_connector *connector;
11108 struct drm_connector_state *connector_state;
11109 int base_bpp, ret = -EINVAL;
11110 int i;
11111 bool retry = true;
11113 clear_intel_crtc_state(pipe_config);
11115 pipe_config->cpu_transcoder =
11116 (enum transcoder) to_intel_crtc(crtc)->pipe;
11118 /*
11119 * Sanitize sync polarity flags based on requested ones. If neither
11120 * positive or negative polarity is requested, treat this as meaning
11121 * negative polarity.
11122 */
11123 if (!(pipe_config->base.adjusted_mode.flags &
11124 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11125 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11127 if (!(pipe_config->base.adjusted_mode.flags &
11128 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11129 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11131 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11132 pipe_config);
11133 if (base_bpp < 0)
11134 goto fail;
11136 /*
11137 * Determine the real pipe dimensions. Note that stereo modes can
11138 * increase the actual pipe size due to the frame doubling and
11139 * insertion of additional space for blanks between the frame. This
11140 * is stored in the crtc timings. We use the requested mode to do this
11141 * computation to clearly distinguish it from the adjusted mode, which
11142 * can be changed by the connectors in the below retry loop.
11143 */
11144 drm_mode_get_hv_timing(&pipe_config->base.mode,
11145 &pipe_config->pipe_src_w,
11146 &pipe_config->pipe_src_h);
11148 for_each_new_connector_in_state(state, connector, connector_state, i) {
11149 if (connector_state->crtc != crtc)
11150 continue;
11152 encoder = to_intel_encoder(connector_state->best_encoder);
11154 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11155 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11156 goto fail;
11157 }
11159 /*
11160 * Determine output_types before calling the .compute_config()
11161 * hooks so that the hooks can use this information safely.
11162 */
11163 if (encoder->compute_output_type)
11164 pipe_config->output_types |=
11165 BIT(encoder->compute_output_type(encoder, pipe_config,
11166 connector_state));
11167 else
11168 pipe_config->output_types |= BIT(encoder->type);
11169 }
11171 encoder_retry:
11172 /* Ensure the port clock defaults are reset when retrying. */
11173 pipe_config->port_clock = 0;
11174 pipe_config->pixel_multiplier = 1;
11176 /* Fill in default crtc timings, allow encoders to overwrite them. */
11177 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11178 CRTC_STEREO_DOUBLE);
11180 /* Pass our mode to the connectors and the CRTC to give them a chance to
11181 * adjust it according to limitations or connector properties, and also
11182 * a chance to reject the mode entirely.
11183 */
11184 for_each_new_connector_in_state(state, connector, connector_state, i) {
11185 if (connector_state->crtc != crtc)
11186 continue;
11188 encoder = to_intel_encoder(connector_state->best_encoder);
11190 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11191 DRM_DEBUG_KMS("Encoder config failure\n");
11192 goto fail;
11193 }
11194 }
11196 /* Set default port clock if not overwritten by the encoder. Needs to be
11197 * done afterwards in case the encoder adjusts the mode. */
11198 if (!pipe_config->port_clock)
11199 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11200 * pipe_config->pixel_multiplier;
11202 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11203 if (ret < 0) {
11204 DRM_DEBUG_KMS("CRTC fixup failed\n");
11205 goto fail;
11206 }
11208 if (ret == RETRY) {
11209 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11210 ret = -EINVAL;
11211 goto fail;
11212 }
11214 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11215 retry = false;
11216 goto encoder_retry;
11217 }
11219 /* Dithering seems to not pass-through bits correctly when it should, so
11220 * only enable it on 6bpc panels and when its not a compliance
11221 * test requesting 6bpc video pattern.
11222 */
11223 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11224 !pipe_config->dither_force_disable;
11225 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11226 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11228 fail:
11229 return ret;
11230 }
11232 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11233 {
11234 int diff;
11236 if (clock1 == clock2)
11237 return true;
11239 if (!clock1 || !clock2)
11240 return false;
11242 diff = abs(clock1 - clock2);
11244 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11245 return true;
11247 return false;
11248 }
11250 static bool
11251 intel_compare_m_n(unsigned int m, unsigned int n,
11252 unsigned int m2, unsigned int n2,
11253 bool exact)
11254 {
11255 if (m == m2 && n == n2)
11256 return true;
11258 if (exact || !m || !n || !m2 || !n2)
11259 return false;
11261 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11263 if (n > n2) {
11264 while (n > n2) {
11265 m2 <<= 1;
11266 n2 <<= 1;
11267 }
11268 } else if (n < n2) {
11269 while (n < n2) {
11270 m <<= 1;
11271 n <<= 1;
11272 }
11273 }
11275 if (n != n2)
11276 return false;
11278 return intel_fuzzy_clock_check(m, m2);
11279 }
11281 static bool
11282 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11283 struct intel_link_m_n *m2_n2,
11284 bool adjust)
11285 {
11286 if (m_n->tu == m2_n2->tu &&
11287 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11288 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11289 intel_compare_m_n(m_n->link_m, m_n->link_n,
11290 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11291 if (adjust)
11292 *m2_n2 = *m_n;
11294 return true;
11295 }
11297 return false;
11298 }
11300 static void __printf(3, 4)
11301 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11302 {
11303 struct va_format vaf;
11304 va_list args;
11306 va_start(args, format);
11307 vaf.fmt = format;
11308 vaf.va = &args;
11310 if (adjust)
11311 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11312 else
11313 drm_err("mismatch in %s %pV", name, &vaf);
11315 va_end(args);
11316 }
11318 static bool
11319 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11320 struct intel_crtc_state *current_config,
11321 struct intel_crtc_state *pipe_config,
11322 bool adjust)
11323 {
11324 bool ret = true;
11325 bool fixup_inherited = adjust &&
11326 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11327 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11329 #define PIPE_CONF_CHECK_X(name) do { \
11330 if (current_config->name != pipe_config->name) { \
11331 pipe_config_err(adjust, __stringify(name), \
11332 "(expected 0x%08x, found 0x%08x)\n", \
11333 current_config->name, \
11334 pipe_config->name); \
11335 ret = false; \
11336 } \
11337 } while (0)
11339 #define PIPE_CONF_CHECK_I(name) do { \
11340 if (current_config->name != pipe_config->name) { \
11341 pipe_config_err(adjust, __stringify(name), \
11342 "(expected %i, found %i)\n", \
11343 current_config->name, \
11344 pipe_config->name); \
11345 ret = false; \
11346 } \
11347 } while (0)
11349 #define PIPE_CONF_CHECK_BOOL(name) do { \
11350 if (current_config->name != pipe_config->name) { \
11351 pipe_config_err(adjust, __stringify(name), \
11352 "(expected %s, found %s)\n", \
11353 yesno(current_config->name), \
11354 yesno(pipe_config->name)); \
11355 ret = false; \
11356 } \
11357 } while (0)
11359 /*
11360 * Checks state where we only read out the enabling, but not the entire
11361 * state itself (like full infoframes or ELD for audio). These states
11362 * require a full modeset on bootup to fix up.
11363 */
11364 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11365 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11366 PIPE_CONF_CHECK_BOOL(name); \
11367 } else { \
11368 pipe_config_err(adjust, __stringify(name), \
11369 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11370 yesno(current_config->name), \
11371 yesno(pipe_config->name)); \
11372 ret = false; \
11373 } \
11374 } while (0)
11376 #define PIPE_CONF_CHECK_P(name) do { \
11377 if (current_config->name != pipe_config->name) { \
11378 pipe_config_err(adjust, __stringify(name), \
11379 "(expected %p, found %p)\n", \
11380 current_config->name, \
11381 pipe_config->name); \
11382 ret = false; \
11383 } \
11384 } while (0)
11386 #define PIPE_CONF_CHECK_M_N(name) do { \
11387 if (!intel_compare_link_m_n(¤t_config->name, \
11388 &pipe_config->name,\
11389 adjust)) { \
11390 pipe_config_err(adjust, __stringify(name), \
11391 "(expected tu %i gmch %i/%i link %i/%i, " \
11392 "found tu %i, gmch %i/%i link %i/%i)\n", \
11393 current_config->name.tu, \
11394 current_config->name.gmch_m, \
11395 current_config->name.gmch_n, \
11396 current_config->name.link_m, \
11397 current_config->name.link_n, \
11398 pipe_config->name.tu, \
11399 pipe_config->name.gmch_m, \
11400 pipe_config->name.gmch_n, \
11401 pipe_config->name.link_m, \
11402 pipe_config->name.link_n); \
11403 ret = false; \
11404 } \
11405 } while (0)
11407 /* This is required for BDW+ where there is only one set of registers for
11408 * switching between high and low RR.
11409 * This macro can be used whenever a comparison has to be made between one
11410 * hw state and multiple sw state variables.
11411 */
11412 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11413 if (!intel_compare_link_m_n(¤t_config->name, \
11414 &pipe_config->name, adjust) && \
11415 !intel_compare_link_m_n(¤t_config->alt_name, \
11416 &pipe_config->name, adjust)) { \
11417 pipe_config_err(adjust, __stringify(name), \
11418 "(expected tu %i gmch %i/%i link %i/%i, " \
11419 "or tu %i gmch %i/%i link %i/%i, " \
11420 "found tu %i, gmch %i/%i link %i/%i)\n", \
11421 current_config->name.tu, \
11422 current_config->name.gmch_m, \
11423 current_config->name.gmch_n, \
11424 current_config->name.link_m, \
11425 current_config->name.link_n, \
11426 current_config->alt_name.tu, \
11427 current_config->alt_name.gmch_m, \
11428 current_config->alt_name.gmch_n, \
11429 current_config->alt_name.link_m, \
11430 current_config->alt_name.link_n, \
11431 pipe_config->name.tu, \
11432 pipe_config->name.gmch_m, \
11433 pipe_config->name.gmch_n, \
11434 pipe_config->name.link_m, \
11435 pipe_config->name.link_n); \
11436 ret = false; \
11437 } \
11438 } while (0)
11440 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11441 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11442 pipe_config_err(adjust, __stringify(name), \
11443 "(%x) (expected %i, found %i)\n", \
11444 (mask), \
11445 current_config->name & (mask), \
11446 pipe_config->name & (mask)); \
11447 ret = false; \
11448 } \
11449 } while (0)
11451 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11452 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11453 pipe_config_err(adjust, __stringify(name), \
11454 "(expected %i, found %i)\n", \
11455 current_config->name, \
11456 pipe_config->name); \
11457 ret = false; \
11458 } \
11459 } while (0)
11461 #define PIPE_CONF_QUIRK(quirk) \
11462 ((current_config->quirks | pipe_config->quirks) & (quirk))
11464 PIPE_CONF_CHECK_I(cpu_transcoder);
11466 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11467 PIPE_CONF_CHECK_I(fdi_lanes);
11468 PIPE_CONF_CHECK_M_N(fdi_m_n);
11470 PIPE_CONF_CHECK_I(lane_count);
11471 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11473 if (INTEL_GEN(dev_priv) < 8) {
11474 PIPE_CONF_CHECK_M_N(dp_m_n);
11476 if (current_config->has_drrs)
11477 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11478 } else
11479 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11481 PIPE_CONF_CHECK_X(output_types);
11483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11491 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11493 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11494 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11495 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11497 PIPE_CONF_CHECK_I(pixel_multiplier);
11498 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11499 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11500 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11501 PIPE_CONF_CHECK_BOOL(limited_color_range);
11503 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11504 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11505 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11506 PIPE_CONF_CHECK_BOOL(ycbcr420);
11508 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11510 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11511 DRM_MODE_FLAG_INTERLACE);
11513 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11514 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11515 DRM_MODE_FLAG_PHSYNC);
11516 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11517 DRM_MODE_FLAG_NHSYNC);
11518 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11519 DRM_MODE_FLAG_PVSYNC);
11520 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11521 DRM_MODE_FLAG_NVSYNC);
11522 }
11524 PIPE_CONF_CHECK_X(gmch_pfit.control);
11525 /* pfit ratios are autocomputed by the hw on gen4+ */
11526 if (INTEL_GEN(dev_priv) < 4)
11527 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11528 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11530 if (!adjust) {
11531 PIPE_CONF_CHECK_I(pipe_src_w);
11532 PIPE_CONF_CHECK_I(pipe_src_h);
11534 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11535 if (current_config->pch_pfit.enabled) {
11536 PIPE_CONF_CHECK_X(pch_pfit.pos);
11537 PIPE_CONF_CHECK_X(pch_pfit.size);
11538 }
11540 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11541 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11542 }
11544 PIPE_CONF_CHECK_BOOL(double_wide);
11546 PIPE_CONF_CHECK_P(shared_dpll);
11547 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11548 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11549 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11550 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11551 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11552 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11553 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11554 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11555 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11556 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11557 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11558 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11559 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11560 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11561 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11562 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11563 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11564 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11565 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11566 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11567 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11568 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
11569 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
11570 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
11571 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
11572 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
11573 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
11574 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
11575 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
11576 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
11577 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
11579 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11580 PIPE_CONF_CHECK_X(dsi_pll.div);
11582 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11583 PIPE_CONF_CHECK_I(pipe_bpp);
11585 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11586 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11588 PIPE_CONF_CHECK_I(min_voltage_level);
11590 #undef PIPE_CONF_CHECK_X
11591 #undef PIPE_CONF_CHECK_I
11592 #undef PIPE_CONF_CHECK_BOOL
11593 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11594 #undef PIPE_CONF_CHECK_P
11595 #undef PIPE_CONF_CHECK_FLAGS
11596 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11597 #undef PIPE_CONF_QUIRK
11599 return ret;
11600 }
11602 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11603 const struct intel_crtc_state *pipe_config)
11604 {
11605 if (pipe_config->has_pch_encoder) {
11606 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11607 &pipe_config->fdi_m_n);
11608 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11610 /*
11611 * FDI already provided one idea for the dotclock.
11612 * Yell if the encoder disagrees.
11613 */
11614 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11615 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11616 fdi_dotclock, dotclock);
11617 }
11618 }
11620 static void verify_wm_state(struct drm_crtc *crtc,
11621 struct drm_crtc_state *new_state)
11622 {
11623 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11624 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11625 struct skl_pipe_wm hw_wm, *sw_wm;
11626 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11627 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11629 const enum pipe pipe = intel_crtc->pipe;
11630 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11632 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11633 return;
11635 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11636 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11638 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11639 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11641 if (INTEL_GEN(dev_priv) >= 11)
11642 if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
11643 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
11644 sw_ddb->enabled_slices,
11645 hw_ddb.enabled_slices);
11646 /* planes */
11647 for_each_universal_plane(dev_priv, pipe, plane) {
11648 hw_plane_wm = &hw_wm.planes[plane];
11649 sw_plane_wm = &sw_wm->planes[plane];
11651 /* Watermarks */
11652 for (level = 0; level <= max_level; level++) {
11653 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11654 &sw_plane_wm->wm[level]))
11655 continue;
11657 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11658 pipe_name(pipe), plane + 1, level,
11659 sw_plane_wm->wm[level].plane_en,
11660 sw_plane_wm->wm[level].plane_res_b,
11661 sw_plane_wm->wm[level].plane_res_l,
11662 hw_plane_wm->wm[level].plane_en,
11663 hw_plane_wm->wm[level].plane_res_b,
11664 hw_plane_wm->wm[level].plane_res_l);
11665 }
11667 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11668 &sw_plane_wm->trans_wm)) {
11669 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11670 pipe_name(pipe), plane + 1,
11671 sw_plane_wm->trans_wm.plane_en,
11672 sw_plane_wm->trans_wm.plane_res_b,
11673 sw_plane_wm->trans_wm.plane_res_l,
11674 hw_plane_wm->trans_wm.plane_en,
11675 hw_plane_wm->trans_wm.plane_res_b,
11676 hw_plane_wm->trans_wm.plane_res_l);
11677 }
11679 /* DDB */
11680 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11681 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11683 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11684 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11685 pipe_name(pipe), plane + 1,
11686 sw_ddb_entry->start, sw_ddb_entry->end,
11687 hw_ddb_entry->start, hw_ddb_entry->end);
11688 }
11689 }
11691 /*
11692 * cursor
11693 * If the cursor plane isn't active, we may not have updated it's ddb
11694 * allocation. In that case since the ddb allocation will be updated
11695 * once the plane becomes visible, we can skip this check
11696 */
11697 if (1) {
11698 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11699 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11701 /* Watermarks */
11702 for (level = 0; level <= max_level; level++) {
11703 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11704 &sw_plane_wm->wm[level]))
11705 continue;
11707 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11708 pipe_name(pipe), level,
11709 sw_plane_wm->wm[level].plane_en,
11710 sw_plane_wm->wm[level].plane_res_b,
11711 sw_plane_wm->wm[level].plane_res_l,
11712 hw_plane_wm->wm[level].plane_en,
11713 hw_plane_wm->wm[level].plane_res_b,
11714 hw_plane_wm->wm[level].plane_res_l);
11715 }
11717 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11718 &sw_plane_wm->trans_wm)) {
11719 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11720 pipe_name(pipe),
11721 sw_plane_wm->trans_wm.plane_en,
11722 sw_plane_wm->trans_wm.plane_res_b,
11723 sw_plane_wm->trans_wm.plane_res_l,
11724 hw_plane_wm->trans_wm.plane_en,
11725 hw_plane_wm->trans_wm.plane_res_b,
11726 hw_plane_wm->trans_wm.plane_res_l);
11727 }
11729 /* DDB */
11730 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11731 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11733 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11734 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11735 pipe_name(pipe),
11736 sw_ddb_entry->start, sw_ddb_entry->end,
11737 hw_ddb_entry->start, hw_ddb_entry->end);
11738 }
11739 }
11740 }
11742 static void
11743 verify_connector_state(struct drm_device *dev,
11744 struct drm_atomic_state *state,
11745 struct drm_crtc *crtc)
11746 {
11747 struct drm_connector *connector;
11748 struct drm_connector_state *new_conn_state;
11749 int i;
11751 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11752 struct drm_encoder *encoder = connector->encoder;
11753 struct drm_crtc_state *crtc_state = NULL;
11755 if (new_conn_state->crtc != crtc)
11756 continue;
11758 if (crtc)
11759 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11761 intel_connector_verify_state(crtc_state, new_conn_state);
11763 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11764 "connector's atomic encoder doesn't match legacy encoder\n");
11765 }
11766 }
11768 static void
11769 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11770 {
11771 struct intel_encoder *encoder;
11772 struct drm_connector *connector;
11773 struct drm_connector_state *old_conn_state, *new_conn_state;
11774 int i;
11776 for_each_intel_encoder(dev, encoder) {
11777 bool enabled = false, found = false;
11778 enum pipe pipe;
11780 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11781 encoder->base.base.id,
11782 encoder->base.name);
11784 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11785 new_conn_state, i) {
11786 if (old_conn_state->best_encoder == &encoder->base)
11787 found = true;
11789 if (new_conn_state->best_encoder != &encoder->base)
11790 continue;
11791 found = enabled = true;
11793 I915_STATE_WARN(new_conn_state->crtc !=
11794 encoder->base.crtc,
11795 "connector's crtc doesn't match encoder crtc\n");
11796 }
11798 if (!found)
11799 continue;
11801 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11802 "encoder's enabled state mismatch "
11803 "(expected %i, found %i)\n",
11804 !!encoder->base.crtc, enabled);
11806 if (!encoder->base.crtc) {
11807 bool active;
11809 active = encoder->get_hw_state(encoder, &pipe);
11810 I915_STATE_WARN(active,
11811 "encoder detached but still enabled on pipe %c.\n",
11812 pipe_name(pipe));
11813 }
11814 }
11815 }
11817 static void
11818 verify_crtc_state(struct drm_crtc *crtc,
11819 struct drm_crtc_state *old_crtc_state,
11820 struct drm_crtc_state *new_crtc_state)
11821 {
11822 struct drm_device *dev = crtc->dev;
11823 struct drm_i915_private *dev_priv = to_i915(dev);
11824 struct intel_encoder *encoder;
11825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11826 struct intel_crtc_state *pipe_config, *sw_config;
11827 struct drm_atomic_state *old_state;
11828 bool active;
11830 old_state = old_crtc_state->state;
11831 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11832 pipe_config = to_intel_crtc_state(old_crtc_state);
11833 memset(pipe_config, 0, sizeof(*pipe_config));
11834 pipe_config->base.crtc = crtc;
11835 pipe_config->base.state = old_state;
11837 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11839 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11841 /* we keep both pipes enabled on 830 */
11842 if (IS_I830(dev_priv))
11843 active = new_crtc_state->active;
11845 I915_STATE_WARN(new_crtc_state->active != active,
11846 "crtc active state doesn't match with hw state "
11847 "(expected %i, found %i)\n", new_crtc_state->active, active);
11849 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11850 "transitional active state does not match atomic hw state "
11851 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11853 for_each_encoder_on_crtc(dev, crtc, encoder) {
11854 enum pipe pipe;
11856 active = encoder->get_hw_state(encoder, &pipe);
11857 I915_STATE_WARN(active != new_crtc_state->active,
11858 "[ENCODER:%i] active %i with crtc active %i\n",
11859 encoder->base.base.id, active, new_crtc_state->active);
11861 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11862 "Encoder connected to wrong pipe %c\n",
11863 pipe_name(pipe));
11865 if (active)
11866 encoder->get_config(encoder, pipe_config);
11867 }
11869 intel_crtc_compute_pixel_rate(pipe_config);
11871 if (!new_crtc_state->active)
11872 return;
11874 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11876 sw_config = to_intel_crtc_state(new_crtc_state);
11877 if (!intel_pipe_config_compare(dev_priv, sw_config,
11878 pipe_config, false)) {
11879 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11880 intel_dump_pipe_config(intel_crtc, pipe_config,
11881 "[hw state]");
11882 intel_dump_pipe_config(intel_crtc, sw_config,
11883 "[sw state]");
11884 }
11885 }
11887 static void
11888 intel_verify_planes(struct intel_atomic_state *state)
11889 {
11890 struct intel_plane *plane;
11891 const struct intel_plane_state *plane_state;
11892 int i;
11894 for_each_new_intel_plane_in_state(state, plane,
11895 plane_state, i)
11896 assert_plane(plane, plane_state->base.visible);
11897 }
11899 static void
11900 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11901 struct intel_shared_dpll *pll,
11902 struct drm_crtc *crtc,
11903 struct drm_crtc_state *new_state)
11904 {
11905 struct intel_dpll_hw_state dpll_hw_state;
11906 unsigned int crtc_mask;
11907 bool active;
11909 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11911 DRM_DEBUG_KMS("%s\n", pll->info->name);
11913 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
11915 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
11916 I915_STATE_WARN(!pll->on && pll->active_mask,
11917 "pll in active use but not on in sw tracking\n");
11918 I915_STATE_WARN(pll->on && !pll->active_mask,
11919 "pll is on but not used by any active crtc\n");
11920 I915_STATE_WARN(pll->on != active,
11921 "pll on state mismatch (expected %i, found %i)\n",
11922 pll->on, active);
11923 }
11925 if (!crtc) {
11926 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11927 "more active pll users than references: %x vs %x\n",
11928 pll->active_mask, pll->state.crtc_mask);
11930 return;
11931 }
11933 crtc_mask = drm_crtc_mask(crtc);
11935 if (new_state->active)
11936 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11937 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11938 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11939 else
11940 I915_STATE_WARN(pll->active_mask & crtc_mask,
11941 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11942 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11944 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11945 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11946 crtc_mask, pll->state.crtc_mask);
11948 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11949 &dpll_hw_state,
11950 sizeof(dpll_hw_state)),
11951 "pll hw state mismatch\n");
11952 }
11954 static void
11955 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11956 struct drm_crtc_state *old_crtc_state,
11957 struct drm_crtc_state *new_crtc_state)
11958 {
11959 struct drm_i915_private *dev_priv = to_i915(dev);
11960 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11961 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11963 if (new_state->shared_dpll)
11964 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11966 if (old_state->shared_dpll &&
11967 old_state->shared_dpll != new_state->shared_dpll) {
11968 unsigned int crtc_mask = drm_crtc_mask(crtc);
11969 struct intel_shared_dpll *pll = old_state->shared_dpll;
11971 I915_STATE_WARN(pll->active_mask & crtc_mask,
11972 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11973 pipe_name(drm_crtc_index(crtc)));
11974 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11975 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11976 pipe_name(drm_crtc_index(crtc)));
11977 }
11978 }
11980 static void
11981 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11982 struct drm_atomic_state *state,
11983 struct drm_crtc_state *old_state,
11984 struct drm_crtc_state *new_state)
11985 {
11986 if (!needs_modeset(new_state) &&
11987 !to_intel_crtc_state(new_state)->update_pipe)
11988 return;
11990 verify_wm_state(crtc, new_state);
11991 verify_connector_state(crtc->dev, state, crtc);
11992 verify_crtc_state(crtc, old_state, new_state);
11993 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11994 }
11996 static void
11997 verify_disabled_dpll_state(struct drm_device *dev)
11998 {
11999 struct drm_i915_private *dev_priv = to_i915(dev);
12000 int i;
12002 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12003 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12004 }
12006 static void
12007 intel_modeset_verify_disabled(struct drm_device *dev,
12008 struct drm_atomic_state *state)
12009 {
12010 verify_encoder_state(dev, state);
12011 verify_connector_state(dev, state, NULL);
12012 verify_disabled_dpll_state(dev);
12013 }
12015 static void update_scanline_offset(struct intel_crtc *crtc)
12016 {
12017 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12019 /*
12020 * The scanline counter increments at the leading edge of hsync.
12021 *
12022 * On most platforms it starts counting from vtotal-1 on the
12023 * first active line. That means the scanline counter value is
12024 * always one less than what we would expect. Ie. just after
12025 * start of vblank, which also occurs at start of hsync (on the
12026 * last active line), the scanline counter will read vblank_start-1.
12027 *
12028 * On gen2 the scanline counter starts counting from 1 instead
12029 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12030 * to keep the value positive), instead of adding one.
12031 *
12032 * On HSW+ the behaviour of the scanline counter depends on the output
12033 * type. For DP ports it behaves like most other platforms, but on HDMI
12034 * there's an extra 1 line difference. So we need to add two instead of
12035 * one to the value.
12036 *
12037 * On VLV/CHV DSI the scanline counter would appear to increment
12038 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12039 * that means we can't tell whether we're in vblank or not while
12040 * we're on that particular line. We must still set scanline_offset
12041 * to 1 so that the vblank timestamps come out correct when we query
12042 * the scanline counter from within the vblank interrupt handler.
12043 * However if queried just before the start of vblank we'll get an
12044 * answer that's slightly in the future.
12045 */
12046 if (IS_GEN2(dev_priv)) {
12047 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12048 int vtotal;
12050 vtotal = adjusted_mode->crtc_vtotal;
12051 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12052 vtotal /= 2;
12054 crtc->scanline_offset = vtotal - 1;
12055 } else if (HAS_DDI(dev_priv) &&
12056 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12057 crtc->scanline_offset = 2;
12058 } else
12059 crtc->scanline_offset = 1;
12060 }
12062 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12063 {
12064 struct drm_device *dev = state->dev;
12065 struct drm_i915_private *dev_priv = to_i915(dev);
12066 struct drm_crtc *crtc;
12067 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12068 int i;
12070 if (!dev_priv->display.crtc_compute_clock)
12071 return;
12073 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12075 struct intel_shared_dpll *old_dpll =
12076 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12078 if (!needs_modeset(new_crtc_state))
12079 continue;
12081 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12083 if (!old_dpll)
12084 continue;
12086 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12087 }
12088 }
12090 /*
12091 * This implements the workaround described in the "notes" section of the mode
12092 * set sequence documentation. When going from no pipes or single pipe to
12093 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12094 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12095 */
12096 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12097 {
12098 struct drm_crtc_state *crtc_state;
12099 struct intel_crtc *intel_crtc;
12100 struct drm_crtc *crtc;
12101 struct intel_crtc_state *first_crtc_state = NULL;
12102 struct intel_crtc_state *other_crtc_state = NULL;
12103 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12104 int i;
12106 /* look at all crtc's that are going to be enabled in during modeset */
12107 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12108 intel_crtc = to_intel_crtc(crtc);
12110 if (!crtc_state->active || !needs_modeset(crtc_state))
12111 continue;
12113 if (first_crtc_state) {
12114 other_crtc_state = to_intel_crtc_state(crtc_state);
12115 break;
12116 } else {
12117 first_crtc_state = to_intel_crtc_state(crtc_state);
12118 first_pipe = intel_crtc->pipe;
12119 }
12120 }
12122 /* No workaround needed? */
12123 if (!first_crtc_state)
12124 return 0;
12126 /* w/a possibly needed, check how many crtc's are already enabled. */
12127 for_each_intel_crtc(state->dev, intel_crtc) {
12128 struct intel_crtc_state *pipe_config;
12130 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12131 if (IS_ERR(pipe_config))
12132 return PTR_ERR(pipe_config);
12134 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12136 if (!pipe_config->base.active ||
12137 needs_modeset(&pipe_config->base))
12138 continue;
12140 /* 2 or more enabled crtcs means no need for w/a */
12141 if (enabled_pipe != INVALID_PIPE)
12142 return 0;
12144 enabled_pipe = intel_crtc->pipe;
12145 }
12147 if (enabled_pipe != INVALID_PIPE)
12148 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12149 else if (other_crtc_state)
12150 other_crtc_state->hsw_workaround_pipe = first_pipe;
12152 return 0;
12153 }
12155 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12156 {
12157 struct drm_crtc *crtc;
12159 /* Add all pipes to the state */
12160 for_each_crtc(state->dev, crtc) {
12161 struct drm_crtc_state *crtc_state;
12163 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12164 if (IS_ERR(crtc_state))
12165 return PTR_ERR(crtc_state);
12166 }
12168 return 0;
12169 }
12171 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12172 {
12173 struct drm_crtc *crtc;
12175 /*
12176 * Add all pipes to the state, and force
12177 * a modeset on all the active ones.
12178 */
12179 for_each_crtc(state->dev, crtc) {
12180 struct drm_crtc_state *crtc_state;
12181 int ret;
12183 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12184 if (IS_ERR(crtc_state))
12185 return PTR_ERR(crtc_state);
12187 if (!crtc_state->active || needs_modeset(crtc_state))
12188 continue;
12190 crtc_state->mode_changed = true;
12192 ret = drm_atomic_add_affected_connectors(state, crtc);
12193 if (ret)
12194 return ret;
12196 ret = drm_atomic_add_affected_planes(state, crtc);
12197 if (ret)
12198 return ret;
12199 }
12201 return 0;
12202 }
12204 static int intel_modeset_checks(struct drm_atomic_state *state)
12205 {
12206 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12207 struct drm_i915_private *dev_priv = to_i915(state->dev);
12208 struct drm_crtc *crtc;
12209 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12210 int ret = 0, i;
12212 if (!check_digital_port_conflicts(state)) {
12213 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12214 return -EINVAL;
12215 }
12217 intel_state->modeset = true;
12218 intel_state->active_crtcs = dev_priv->active_crtcs;
12219 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12220 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12222 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12223 if (new_crtc_state->active)
12224 intel_state->active_crtcs |= 1 << i;
12225 else
12226 intel_state->active_crtcs &= ~(1 << i);
12228 if (old_crtc_state->active != new_crtc_state->active)
12229 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12230 }
12232 /*
12233 * See if the config requires any additional preparation, e.g.
12234 * to adjust global state with pipes off. We need to do this
12235 * here so we can get the modeset_pipe updated config for the new
12236 * mode set on this crtc. For other crtcs we need to use the
12237 * adjusted_mode bits in the crtc directly.
12238 */
12239 if (dev_priv->display.modeset_calc_cdclk) {
12240 ret = dev_priv->display.modeset_calc_cdclk(state);
12241 if (ret < 0)
12242 return ret;
12244 /*
12245 * Writes to dev_priv->cdclk.logical must protected by
12246 * holding all the crtc locks, even if we don't end up
12247 * touching the hardware
12248 */
12249 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12250 &intel_state->cdclk.logical)) {
12251 ret = intel_lock_all_pipes(state);
12252 if (ret < 0)
12253 return ret;
12254 }
12256 /* All pipes must be switched off while we change the cdclk. */
12257 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12258 &intel_state->cdclk.actual)) {
12259 ret = intel_modeset_all_pipes(state);
12260 if (ret < 0)
12261 return ret;
12262 }
12264 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12265 intel_state->cdclk.logical.cdclk,
12266 intel_state->cdclk.actual.cdclk);
12267 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12268 intel_state->cdclk.logical.voltage_level,
12269 intel_state->cdclk.actual.voltage_level);
12270 } else {
12271 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12272 }
12274 intel_modeset_clear_plls(state);
12276 if (IS_HASWELL(dev_priv))
12277 return haswell_mode_set_planes_workaround(state);
12279 return 0;
12280 }
12282 /*
12283 * Handle calculation of various watermark data at the end of the atomic check
12284 * phase. The code here should be run after the per-crtc and per-plane 'check'
12285 * handlers to ensure that all derived state has been updated.
12286 */
12287 static int calc_watermark_data(struct drm_atomic_state *state)
12288 {
12289 struct drm_device *dev = state->dev;
12290 struct drm_i915_private *dev_priv = to_i915(dev);
12292 /* Is there platform-specific watermark information to calculate? */
12293 if (dev_priv->display.compute_global_watermarks)
12294 return dev_priv->display.compute_global_watermarks(state);
12296 return 0;
12297 }
12299 /**
12300 * intel_atomic_check - validate state object
12301 * @dev: drm device
12302 * @state: state to validate
12303 */
12304 static int intel_atomic_check(struct drm_device *dev,
12305 struct drm_atomic_state *state)
12306 {
12307 struct drm_i915_private *dev_priv = to_i915(dev);
12308 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12309 struct drm_crtc *crtc;
12310 struct drm_crtc_state *old_crtc_state, *crtc_state;
12311 int ret, i;
12312 bool any_ms = false;
12314 /* Catch I915_MODE_FLAG_INHERITED */
12315 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12316 crtc_state, i) {
12317 if (crtc_state->mode.private_flags !=
12318 old_crtc_state->mode.private_flags)
12319 crtc_state->mode_changed = true;
12320 }
12322 ret = drm_atomic_helper_check_modeset(dev, state);
12323 if (ret)
12324 return ret;
12326 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12327 struct intel_crtc_state *pipe_config =
12328 to_intel_crtc_state(crtc_state);
12330 if (!needs_modeset(crtc_state))
12331 continue;
12333 if (!crtc_state->enable) {
12334 any_ms = true;
12335 continue;
12336 }
12338 ret = intel_modeset_pipe_config(crtc, pipe_config);
12339 if (ret) {
12340 intel_dump_pipe_config(to_intel_crtc(crtc),
12341 pipe_config, "[failed]");
12342 return ret;
12343 }
12345 if (i915_modparams.fastboot &&
12346 intel_pipe_config_compare(dev_priv,
12347 to_intel_crtc_state(old_crtc_state),
12348 pipe_config, true)) {
12349 crtc_state->mode_changed = false;
12350 pipe_config->update_pipe = true;
12351 }
12353 if (needs_modeset(crtc_state))
12354 any_ms = true;
12356 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12357 needs_modeset(crtc_state) ?
12358 "[modeset]" : "[fastset]");
12359 }
12361 if (any_ms) {
12362 ret = intel_modeset_checks(state);
12364 if (ret)
12365 return ret;
12366 } else {
12367 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12368 }
12370 ret = drm_atomic_helper_check_planes(dev, state);
12371 if (ret)
12372 return ret;
12374 intel_fbc_choose_crtc(dev_priv, intel_state);
12375 return calc_watermark_data(state);
12376 }
12378 static int intel_atomic_prepare_commit(struct drm_device *dev,
12379 struct drm_atomic_state *state)
12380 {
12381 return drm_atomic_helper_prepare_planes(dev, state);
12382 }
12384 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12385 {
12386 struct drm_device *dev = crtc->base.dev;
12388 if (!dev->max_vblank_count)
12389 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12391 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12392 }
12394 static void intel_update_crtc(struct drm_crtc *crtc,
12395 struct drm_atomic_state *state,
12396 struct drm_crtc_state *old_crtc_state,
12397 struct drm_crtc_state *new_crtc_state)
12398 {
12399 struct drm_device *dev = crtc->dev;
12400 struct drm_i915_private *dev_priv = to_i915(dev);
12401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12402 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12403 bool modeset = needs_modeset(new_crtc_state);
12404 struct intel_plane_state *new_plane_state =
12405 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12406 to_intel_plane(crtc->primary));
12408 if (modeset) {
12409 update_scanline_offset(intel_crtc);
12410 dev_priv->display.crtc_enable(pipe_config, state);
12412 /* vblanks work again, re-enable pipe CRC. */
12413 intel_crtc_enable_pipe_crc(intel_crtc);
12414 } else {
12415 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12416 pipe_config);
12417 }
12419 if (new_plane_state)
12420 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12422 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12423 }
12425 static void intel_update_crtcs(struct drm_atomic_state *state)
12426 {
12427 struct drm_crtc *crtc;
12428 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12429 int i;
12431 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12432 if (!new_crtc_state->active)
12433 continue;
12435 intel_update_crtc(crtc, state, old_crtc_state,
12436 new_crtc_state);
12437 }
12438 }
12440 static void skl_update_crtcs(struct drm_atomic_state *state)
12441 {
12442 struct drm_i915_private *dev_priv = to_i915(state->dev);
12443 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12444 struct drm_crtc *crtc;
12445 struct intel_crtc *intel_crtc;
12446 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12447 struct intel_crtc_state *cstate;
12448 unsigned int updated = 0;
12449 bool progress;
12450 enum pipe pipe;
12451 int i;
12452 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12453 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12455 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12457 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12458 /* ignore allocations for crtc's that have been turned off. */
12459 if (new_crtc_state->active)
12460 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12462 /* If 2nd DBuf slice required, enable it here */
12463 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
12464 icl_dbuf_slices_update(dev_priv, required_slices);
12466 /*
12467 * Whenever the number of active pipes changes, we need to make sure we
12468 * update the pipes in the right order so that their ddb allocations
12469 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12470 * cause pipe underruns and other bad stuff.
12471 */
12472 do {
12473 progress = false;
12475 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12476 bool vbl_wait = false;
12477 unsigned int cmask = drm_crtc_mask(crtc);
12479 intel_crtc = to_intel_crtc(crtc);
12480 cstate = to_intel_crtc_state(new_crtc_state);
12481 pipe = intel_crtc->pipe;
12483 if (updated & cmask || !cstate->base.active)
12484 continue;
12486 if (skl_ddb_allocation_overlaps(dev_priv,
12487 entries,
12488 &cstate->wm.skl.ddb,
12489 i))
12490 continue;
12492 updated |= cmask;
12493 entries[i] = &cstate->wm.skl.ddb;
12495 /*
12496 * If this is an already active pipe, it's DDB changed,
12497 * and this isn't the last pipe that needs updating
12498 * then we need to wait for a vblank to pass for the
12499 * new ddb allocation to take effect.
12500 */
12501 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12502 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12503 !new_crtc_state->active_changed &&
12504 intel_state->wm_results.dirty_pipes != updated)
12505 vbl_wait = true;
12507 intel_update_crtc(crtc, state, old_crtc_state,
12508 new_crtc_state);
12510 if (vbl_wait)
12511 intel_wait_for_vblank(dev_priv, pipe);
12513 progress = true;
12514 }
12515 } while (progress);
12517 /* If 2nd DBuf slice is no more required disable it */
12518 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
12519 icl_dbuf_slices_update(dev_priv, required_slices);
12520 }
12522 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12523 {
12524 struct intel_atomic_state *state, *next;
12525 struct llist_node *freed;
12527 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12528 llist_for_each_entry_safe(state, next, freed, freed)
12529 drm_atomic_state_put(&state->base);
12530 }
12532 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12533 {
12534 struct drm_i915_private *dev_priv =
12535 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12537 intel_atomic_helper_free_state(dev_priv);
12538 }
12540 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12541 {
12542 struct wait_queue_entry wait_fence, wait_reset;
12543 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12545 init_wait_entry(&wait_fence, 0);
12546 init_wait_entry(&wait_reset, 0);
12547 for (;;) {
12548 prepare_to_wait(&intel_state->commit_ready.wait,
12549 &wait_fence, TASK_UNINTERRUPTIBLE);
12550 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12551 &wait_reset, TASK_UNINTERRUPTIBLE);
12554 if (i915_sw_fence_done(&intel_state->commit_ready)
12555 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12556 break;
12558 schedule();
12559 }
12560 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12561 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12562 }
12564 static void intel_atomic_cleanup_work(struct work_struct *work)
12565 {
12566 struct drm_atomic_state *state =
12567 container_of(work, struct drm_atomic_state, commit_work);
12568 struct drm_i915_private *i915 = to_i915(state->dev);
12570 drm_atomic_helper_cleanup_planes(&i915->drm, state);
12571 drm_atomic_helper_commit_cleanup_done(state);
12572 drm_atomic_state_put(state);
12574 intel_atomic_helper_free_state(i915);
12575 }
12577 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12578 {
12579 struct drm_device *dev = state->dev;
12580 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12581 struct drm_i915_private *dev_priv = to_i915(dev);
12582 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12583 struct drm_crtc *crtc;
12584 struct intel_crtc_state *intel_cstate;
12585 u64 put_domains[I915_MAX_PIPES] = {};
12586 int i;
12588 intel_atomic_commit_fence_wait(intel_state);
12590 drm_atomic_helper_wait_for_dependencies(state);
12592 if (intel_state->modeset)
12593 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12595 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12598 if (needs_modeset(new_crtc_state) ||
12599 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12601 put_domains[to_intel_crtc(crtc)->pipe] =
12602 modeset_get_crtc_power_domains(crtc,
12603 to_intel_crtc_state(new_crtc_state));
12604 }
12606 if (!needs_modeset(new_crtc_state))
12607 continue;
12609 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12610 to_intel_crtc_state(new_crtc_state));
12612 if (old_crtc_state->active) {
12613 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12615 /*
12616 * We need to disable pipe CRC before disabling the pipe,
12617 * or we race against vblank off.
12618 */
12619 intel_crtc_disable_pipe_crc(intel_crtc);
12621 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12622 intel_crtc->active = false;
12623 intel_fbc_disable(intel_crtc);
12624 intel_disable_shared_dpll(intel_crtc);
12626 /*
12627 * Underruns don't always raise
12628 * interrupts, so check manually.
12629 */
12630 intel_check_cpu_fifo_underruns(dev_priv);
12631 intel_check_pch_fifo_underruns(dev_priv);
12633 if (!new_crtc_state->active) {
12634 /*
12635 * Make sure we don't call initial_watermarks
12636 * for ILK-style watermark updates.
12637 *
12638 * No clue what this is supposed to achieve.
12639 */
12640 if (INTEL_GEN(dev_priv) >= 9)
12641 dev_priv->display.initial_watermarks(intel_state,
12642 to_intel_crtc_state(new_crtc_state));
12643 }
12644 }
12645 }
12647 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12648 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12649 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12651 if (intel_state->modeset) {
12652 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12654 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12656 /*
12657 * SKL workaround: bspec recommends we disable the SAGV when we
12658 * have more then one pipe enabled
12659 */
12660 if (!intel_can_enable_sagv(state))
12661 intel_disable_sagv(dev_priv);
12663 intel_modeset_verify_disabled(dev, state);
12664 }
12666 /* Complete the events for pipes that have now been disabled */
12667 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12668 bool modeset = needs_modeset(new_crtc_state);
12670 /* Complete events for now disable pipes here. */
12671 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12672 spin_lock_irq(&dev->event_lock);
12673 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12674 spin_unlock_irq(&dev->event_lock);
12676 new_crtc_state->event = NULL;
12677 }
12678 }
12680 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12681 dev_priv->display.update_crtcs(state);
12683 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12684 * already, but still need the state for the delayed optimization. To
12685 * fix this:
12686 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12687 * - schedule that vblank worker _before_ calling hw_done
12688 * - at the start of commit_tail, cancel it _synchrously
12689 * - switch over to the vblank wait helper in the core after that since
12690 * we don't need out special handling any more.
12691 */
12692 drm_atomic_helper_wait_for_flip_done(dev, state);
12694 /*
12695 * Now that the vblank has passed, we can go ahead and program the
12696 * optimal watermarks on platforms that need two-step watermark
12697 * programming.
12698 *
12699 * TODO: Move this (and other cleanup) to an async worker eventually.
12700 */
12701 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12702 intel_cstate = to_intel_crtc_state(new_crtc_state);
12704 if (dev_priv->display.optimize_watermarks)
12705 dev_priv->display.optimize_watermarks(intel_state,
12706 intel_cstate);
12707 }
12709 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12710 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12712 if (put_domains[i])
12713 modeset_put_power_domains(dev_priv, put_domains[i]);
12715 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12716 }
12718 if (intel_state->modeset)
12719 intel_verify_planes(intel_state);
12721 if (intel_state->modeset && intel_can_enable_sagv(state))
12722 intel_enable_sagv(dev_priv);
12724 drm_atomic_helper_commit_hw_done(state);
12726 if (intel_state->modeset) {
12727 /* As one of the primary mmio accessors, KMS has a high
12728 * likelihood of triggering bugs in unclaimed access. After we
12729 * finish modesetting, see if an error has been flagged, and if
12730 * so enable debugging for the next modeset - and hope we catch
12731 * the culprit.
12732 */
12733 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12734 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12735 }
12737 /*
12738 * Defer the cleanup of the old state to a separate worker to not
12739 * impede the current task (userspace for blocking modesets) that
12740 * are executed inline. For out-of-line asynchronous modesets/flips,
12741 * deferring to a new worker seems overkill, but we would place a
12742 * schedule point (cond_resched()) here anyway to keep latencies
12743 * down.
12744 */
12745 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
12746 schedule_work(&state->commit_work);
12747 }
12749 static void intel_atomic_commit_work(struct work_struct *work)
12750 {
12751 struct drm_atomic_state *state =
12752 container_of(work, struct drm_atomic_state, commit_work);
12754 intel_atomic_commit_tail(state);
12755 }
12757 static int __i915_sw_fence_call
12758 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12759 enum i915_sw_fence_notify notify)
12760 {
12761 struct intel_atomic_state *state =
12762 container_of(fence, struct intel_atomic_state, commit_ready);
12764 switch (notify) {
12765 case FENCE_COMPLETE:
12766 /* we do blocking waits in the worker, nothing to do here */
12767 break;
12768 case FENCE_FREE:
12769 {
12770 struct intel_atomic_helper *helper =
12771 &to_i915(state->base.dev)->atomic_helper;
12773 if (llist_add(&state->freed, &helper->free_list))
12774 schedule_work(&helper->free_work);
12775 break;
12776 }
12777 }
12779 return NOTIFY_DONE;
12780 }
12782 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12783 {
12784 struct drm_plane_state *old_plane_state, *new_plane_state;
12785 struct drm_plane *plane;
12786 int i;
12788 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12789 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12790 intel_fb_obj(new_plane_state->fb),
12791 to_intel_plane(plane)->frontbuffer_bit);
12792 }
12794 /**
12795 * intel_atomic_commit - commit validated state object
12796 * @dev: DRM device
12797 * @state: the top-level driver state object
12798 * @nonblock: nonblocking commit
12799 *
12800 * This function commits a top-level state object that has been validated
12801 * with drm_atomic_helper_check().
12802 *
12803 * RETURNS
12804 * Zero for success or -errno.
12805 */
12806 static int intel_atomic_commit(struct drm_device *dev,
12807 struct drm_atomic_state *state,
12808 bool nonblock)
12809 {
12810 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12811 struct drm_i915_private *dev_priv = to_i915(dev);
12812 int ret = 0;
12814 drm_atomic_state_get(state);
12815 i915_sw_fence_init(&intel_state->commit_ready,
12816 intel_atomic_commit_ready);
12818 /*
12819 * The intel_legacy_cursor_update() fast path takes care
12820 * of avoiding the vblank waits for simple cursor
12821 * movement and flips. For cursor on/off and size changes,
12822 * we want to perform the vblank waits so that watermark
12823 * updates happen during the correct frames. Gen9+ have
12824 * double buffered watermarks and so shouldn't need this.
12825 *
12826 * Unset state->legacy_cursor_update before the call to
12827 * drm_atomic_helper_setup_commit() because otherwise
12828 * drm_atomic_helper_wait_for_flip_done() is a noop and
12829 * we get FIFO underruns because we didn't wait
12830 * for vblank.
12831 *
12832 * FIXME doing watermarks and fb cleanup from a vblank worker
12833 * (assuming we had any) would solve these problems.
12834 */
12835 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12836 struct intel_crtc_state *new_crtc_state;
12837 struct intel_crtc *crtc;
12838 int i;
12840 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12841 if (new_crtc_state->wm.need_postvbl_update ||
12842 new_crtc_state->update_wm_post)
12843 state->legacy_cursor_update = false;
12844 }
12846 ret = intel_atomic_prepare_commit(dev, state);
12847 if (ret) {
12848 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12849 i915_sw_fence_commit(&intel_state->commit_ready);
12850 return ret;
12851 }
12853 ret = drm_atomic_helper_setup_commit(state, nonblock);
12854 if (!ret)
12855 ret = drm_atomic_helper_swap_state(state, true);
12857 if (ret) {
12858 i915_sw_fence_commit(&intel_state->commit_ready);
12860 drm_atomic_helper_cleanup_planes(dev, state);
12861 return ret;
12862 }
12863 dev_priv->wm.distrust_bios_wm = false;
12864 intel_shared_dpll_swap_state(state);
12865 intel_atomic_track_fbs(state);
12867 if (intel_state->modeset) {
12868 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12869 sizeof(intel_state->min_cdclk));
12870 memcpy(dev_priv->min_voltage_level,
12871 intel_state->min_voltage_level,
12872 sizeof(intel_state->min_voltage_level));
12873 dev_priv->active_crtcs = intel_state->active_crtcs;
12874 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12875 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12876 }
12878 drm_atomic_state_get(state);
12879 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12881 i915_sw_fence_commit(&intel_state->commit_ready);
12882 if (nonblock && intel_state->modeset) {
12883 queue_work(dev_priv->modeset_wq, &state->commit_work);
12884 } else if (nonblock) {
12885 queue_work(system_unbound_wq, &state->commit_work);
12886 } else {
12887 if (intel_state->modeset)
12888 flush_workqueue(dev_priv->modeset_wq);
12889 intel_atomic_commit_tail(state);
12890 }
12892 return 0;
12893 }
12895 static const struct drm_crtc_funcs intel_crtc_funcs = {
12896 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12897 .set_config = drm_atomic_helper_set_config,
12898 .destroy = intel_crtc_destroy,
12899 .page_flip = drm_atomic_helper_page_flip,
12900 .atomic_duplicate_state = intel_crtc_duplicate_state,
12901 .atomic_destroy_state = intel_crtc_destroy_state,
12902 .set_crc_source = intel_crtc_set_crc_source,
12903 };
12905 struct wait_rps_boost {
12906 struct wait_queue_entry wait;
12908 struct drm_crtc *crtc;
12909 struct i915_request *request;
12910 };
12912 static int do_rps_boost(struct wait_queue_entry *_wait,
12913 unsigned mode, int sync, void *key)
12914 {
12915 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12916 struct i915_request *rq = wait->request;
12918 /*
12919 * If we missed the vblank, but the request is already running it
12920 * is reasonable to assume that it will complete before the next
12921 * vblank without our intervention, so leave RPS alone.
12922 */
12923 if (!i915_request_started(rq))
12924 gen6_rps_boost(rq, NULL);
12925 i915_request_put(rq);
12927 drm_crtc_vblank_put(wait->crtc);
12929 list_del(&wait->wait.entry);
12930 kfree(wait);
12931 return 1;
12932 }
12934 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12935 struct dma_fence *fence)
12936 {
12937 struct wait_rps_boost *wait;
12939 if (!dma_fence_is_i915(fence))
12940 return;
12942 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12943 return;
12945 if (drm_crtc_vblank_get(crtc))
12946 return;
12948 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12949 if (!wait) {
12950 drm_crtc_vblank_put(crtc);
12951 return;
12952 }
12954 wait->request = to_request(dma_fence_get(fence));
12955 wait->crtc = crtc;
12957 wait->wait.func = do_rps_boost;
12958 wait->wait.flags = 0;
12960 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12961 }
12963 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
12964 {
12965 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12966 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12967 struct drm_framebuffer *fb = plane_state->base.fb;
12968 struct i915_vma *vma;
12970 if (plane->id == PLANE_CURSOR &&
12971 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12972 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12973 const int align = intel_cursor_alignment(dev_priv);
12975 return i915_gem_object_attach_phys(obj, align);
12976 }
12978 vma = intel_pin_and_fence_fb_obj(fb,
12979 plane_state->base.rotation,
12980 intel_plane_uses_fence(plane_state),
12981 &plane_state->flags);
12982 if (IS_ERR(vma))
12983 return PTR_ERR(vma);
12985 plane_state->vma = vma;
12987 return 0;
12988 }
12990 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
12991 {
12992 struct i915_vma *vma;
12994 vma = fetch_and_zero(&old_plane_state->vma);
12995 if (vma)
12996 intel_unpin_fb_vma(vma, old_plane_state->flags);
12997 }
12999 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
13000 {
13001 struct i915_sched_attr attr = {
13002 .priority = I915_PRIORITY_DISPLAY,
13003 };
13005 i915_gem_object_wait_priority(obj, 0, &attr);
13006 }
13008 /**
13009 * intel_prepare_plane_fb - Prepare fb for usage on plane
13010 * @plane: drm plane to prepare for
13011 * @new_state: the plane state being prepared
13012 *
13013 * Prepares a framebuffer for usage on a display plane. Generally this
13014 * involves pinning the underlying object and updating the frontbuffer tracking
13015 * bits. Some older platforms need special physical address handling for
13016 * cursor planes.
13017 *
13018 * Must be called with struct_mutex held.
13019 *
13020 * Returns 0 on success, negative error code on failure.
13021 */
13022 int
13023 intel_prepare_plane_fb(struct drm_plane *plane,
13024 struct drm_plane_state *new_state)
13025 {
13026 struct intel_atomic_state *intel_state =
13027 to_intel_atomic_state(new_state->state);
13028 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13029 struct drm_framebuffer *fb = new_state->fb;
13030 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13031 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13032 int ret;
13034 if (old_obj) {
13035 struct drm_crtc_state *crtc_state =
13036 drm_atomic_get_new_crtc_state(new_state->state,
13037 plane->state->crtc);
13039 /* Big Hammer, we also need to ensure that any pending
13040 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13041 * current scanout is retired before unpinning the old
13042 * framebuffer. Note that we rely on userspace rendering
13043 * into the buffer attached to the pipe they are waiting
13044 * on. If not, userspace generates a GPU hang with IPEHR
13045 * point to the MI_WAIT_FOR_EVENT.
13046 *
13047 * This should only fail upon a hung GPU, in which case we
13048 * can safely continue.
13049 */
13050 if (needs_modeset(crtc_state)) {
13051 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13052 old_obj->resv, NULL,
13053 false, 0,
13054 GFP_KERNEL);
13055 if (ret < 0)
13056 return ret;
13057 }
13058 }
13060 if (new_state->fence) { /* explicit fencing */
13061 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13062 new_state->fence,
13063 I915_FENCE_TIMEOUT,
13064 GFP_KERNEL);
13065 if (ret < 0)
13066 return ret;
13067 }
13069 if (!obj)
13070 return 0;
13072 ret = i915_gem_object_pin_pages(obj);
13073 if (ret)
13074 return ret;
13076 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13077 if (ret) {
13078 i915_gem_object_unpin_pages(obj);
13079 return ret;
13080 }
13082 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13084 fb_obj_bump_render_priority(obj);
13086 mutex_unlock(&dev_priv->drm.struct_mutex);
13087 i915_gem_object_unpin_pages(obj);
13088 if (ret)
13089 return ret;
13091 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13093 if (!new_state->fence) { /* implicit fencing */
13094 struct dma_fence *fence;
13096 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13097 obj->resv, NULL,
13098 false, I915_FENCE_TIMEOUT,
13099 GFP_KERNEL);
13100 if (ret < 0)
13101 return ret;
13103 fence = reservation_object_get_excl_rcu(obj->resv);
13104 if (fence) {
13105 add_rps_boost_after_vblank(new_state->crtc, fence);
13106 dma_fence_put(fence);
13107 }
13108 } else {
13109 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13110 }
13112 /*
13113 * We declare pageflips to be interactive and so merit a small bias
13114 * towards upclocking to deliver the frame on time. By only changing
13115 * the RPS thresholds to sample more regularly and aim for higher
13116 * clocks we can hopefully deliver low power workloads (like kodi)
13117 * that are not quite steady state without resorting to forcing
13118 * maximum clocks following a vblank miss (see do_rps_boost()).
13119 */
13120 if (!intel_state->rps_interactive) {
13121 intel_rps_mark_interactive(dev_priv, true);
13122 intel_state->rps_interactive = true;
13123 }
13125 return 0;
13126 }
13128 /**
13129 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13130 * @plane: drm plane to clean up for
13131 * @old_state: the state from the previous modeset
13132 *
13133 * Cleans up a framebuffer that has just been removed from a plane.
13134 *
13135 * Must be called with struct_mutex held.
13136 */
13137 void
13138 intel_cleanup_plane_fb(struct drm_plane *plane,
13139 struct drm_plane_state *old_state)
13140 {
13141 struct intel_atomic_state *intel_state =
13142 to_intel_atomic_state(old_state->state);
13143 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13145 if (intel_state->rps_interactive) {
13146 intel_rps_mark_interactive(dev_priv, false);
13147 intel_state->rps_interactive = false;
13148 }
13150 /* Should only be called after a successful intel_prepare_plane_fb()! */
13151 mutex_lock(&dev_priv->drm.struct_mutex);
13152 intel_plane_unpin_fb(to_intel_plane_state(old_state));
13153 mutex_unlock(&dev_priv->drm.struct_mutex);
13154 }
13156 int
13157 skl_max_scale(struct intel_crtc *intel_crtc,
13158 struct intel_crtc_state *crtc_state,
13159 uint32_t pixel_format)
13160 {
13161 struct drm_i915_private *dev_priv;
13162 int max_scale, mult;
13163 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13165 if (!intel_crtc || !crtc_state->base.enable)
13166 return DRM_PLANE_HELPER_NO_SCALING;
13168 dev_priv = to_i915(intel_crtc->base.dev);
13170 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13171 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13173 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13174 max_dotclk *= 2;
13176 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13177 return DRM_PLANE_HELPER_NO_SCALING;
13179 /*
13180 * skl max scale is lower of:
13181 * close to 3 but not 3, -1 is for that purpose
13182 * or
13183 * cdclk/crtc_clock
13184 */
13185 mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
13186 tmpclk1 = (1 << 16) * mult - 1;
13187 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13188 max_scale = min(tmpclk1, tmpclk2);
13190 return max_scale;
13191 }
13193 static int
13194 intel_check_primary_plane(struct intel_plane *plane,
13195 struct intel_crtc_state *crtc_state,
13196 struct intel_plane_state *state)
13197 {
13198 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13199 struct drm_crtc *crtc = state->base.crtc;
13200 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13201 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13202 bool can_position = false;
13203 int ret;
13204 uint32_t pixel_format = 0;
13206 if (INTEL_GEN(dev_priv) >= 9) {
13207 /* use scaler when colorkey is not required */
13208 if (!state->ckey.flags) {
13209 min_scale = 1;
13210 if (state->base.fb)
13211 pixel_format = state->base.fb->format->format;
13212 max_scale = skl_max_scale(to_intel_crtc(crtc),
13213 crtc_state, pixel_format);
13214 }
13215 can_position = true;
13216 }
13218 ret = drm_atomic_helper_check_plane_state(&state->base,
13219 &crtc_state->base,
13220 min_scale, max_scale,
13221 can_position, true);
13222 if (ret)
13223 return ret;
13225 if (!state->base.fb)
13226 return 0;
13228 if (INTEL_GEN(dev_priv) >= 9) {
13229 ret = skl_check_plane_surface(crtc_state, state);
13230 if (ret)
13231 return ret;
13233 state->ctl = skl_plane_ctl(crtc_state, state);
13234 } else {
13235 ret = i9xx_check_plane_surface(state);
13236 if (ret)
13237 return ret;
13239 state->ctl = i9xx_plane_ctl(crtc_state, state);
13240 }
13242 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
13243 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
13245 return 0;
13246 }
13248 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13249 struct drm_crtc_state *old_crtc_state)
13250 {
13251 struct drm_device *dev = crtc->dev;
13252 struct drm_i915_private *dev_priv = to_i915(dev);
13253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13254 struct intel_crtc_state *old_intel_cstate =
13255 to_intel_crtc_state(old_crtc_state);
13256 struct intel_atomic_state *old_intel_state =
13257 to_intel_atomic_state(old_crtc_state->state);
13258 struct intel_crtc_state *intel_cstate =
13259 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13260 bool modeset = needs_modeset(&intel_cstate->base);
13262 if (!modeset &&
13263 (intel_cstate->base.color_mgmt_changed ||
13264 intel_cstate->update_pipe)) {
13265 intel_color_set_csc(&intel_cstate->base);
13266 intel_color_load_luts(&intel_cstate->base);
13267 }
13269 /* Perform vblank evasion around commit operation */
13270 intel_pipe_update_start(intel_cstate);
13272 if (modeset)
13273 goto out;
13275 if (intel_cstate->update_pipe)
13276 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13277 else if (INTEL_GEN(dev_priv) >= 9)
13278 skl_detach_scalers(intel_crtc);
13280 out:
13281 if (dev_priv->display.atomic_update_watermarks)
13282 dev_priv->display.atomic_update_watermarks(old_intel_state,
13283 intel_cstate);
13284 }
13286 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13287 struct intel_crtc_state *crtc_state)
13288 {
13289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13291 if (!IS_GEN2(dev_priv))
13292 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13294 if (crtc_state->has_pch_encoder) {
13295 enum pipe pch_transcoder =
13296 intel_crtc_pch_transcoder(crtc);
13298 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13299 }
13300 }
13302 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13303 struct drm_crtc_state *old_crtc_state)
13304 {
13305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13306 struct intel_atomic_state *old_intel_state =
13307 to_intel_atomic_state(old_crtc_state->state);
13308 struct intel_crtc_state *new_crtc_state =
13309 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13311 intel_pipe_update_end(new_crtc_state);
13313 if (new_crtc_state->update_pipe &&
13314 !needs_modeset(&new_crtc_state->base) &&
13315 old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13316 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
13317 }
13319 /**
13320 * intel_plane_destroy - destroy a plane
13321 * @plane: plane to destroy
13322 *
13323 * Common destruction function for all types of planes (primary, cursor,
13324 * sprite).
13325 */
13326 void intel_plane_destroy(struct drm_plane *plane)
13327 {
13328 drm_plane_cleanup(plane);
13329 kfree(to_intel_plane(plane));
13330 }
13332 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
13333 u32 format, u64 modifier)
13334 {
13335 switch (modifier) {
13336 case DRM_FORMAT_MOD_LINEAR:
13337 case I915_FORMAT_MOD_X_TILED:
13338 break;
13339 default:
13340 return false;
13341 }
13343 switch (format) {
13344 case DRM_FORMAT_C8:
13345 case DRM_FORMAT_RGB565:
13346 case DRM_FORMAT_XRGB1555:
13347 case DRM_FORMAT_XRGB8888:
13348 return modifier == DRM_FORMAT_MOD_LINEAR ||
13349 modifier == I915_FORMAT_MOD_X_TILED;
13350 default:
13351 return false;
13352 }
13353 }
13355 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
13356 u32 format, u64 modifier)
13357 {
13358 switch (modifier) {
13359 case DRM_FORMAT_MOD_LINEAR:
13360 case I915_FORMAT_MOD_X_TILED:
13361 break;
13362 default:
13363 return false;
13364 }
13366 switch (format) {
13367 case DRM_FORMAT_C8:
13368 case DRM_FORMAT_RGB565:
13369 case DRM_FORMAT_XRGB8888:
13370 case DRM_FORMAT_XBGR8888:
13371 case DRM_FORMAT_XRGB2101010:
13372 case DRM_FORMAT_XBGR2101010:
13373 return modifier == DRM_FORMAT_MOD_LINEAR ||
13374 modifier == I915_FORMAT_MOD_X_TILED;
13375 default:
13376 return false;
13377 }
13378 }
13380 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
13381 u32 format, u64 modifier)
13382 {
13383 struct intel_plane *plane = to_intel_plane(_plane);
13385 switch (modifier) {
13386 case DRM_FORMAT_MOD_LINEAR:
13387 case I915_FORMAT_MOD_X_TILED:
13388 case I915_FORMAT_MOD_Y_TILED:
13389 case I915_FORMAT_MOD_Yf_TILED:
13390 break;
13391 case I915_FORMAT_MOD_Y_TILED_CCS:
13392 case I915_FORMAT_MOD_Yf_TILED_CCS:
13393 if (!plane->has_ccs)
13394 return false;
13395 break;
13396 default:
13397 return false;
13398 }
13400 switch (format) {
13401 case DRM_FORMAT_XRGB8888:
13402 case DRM_FORMAT_XBGR8888:
13403 case DRM_FORMAT_ARGB8888:
13404 case DRM_FORMAT_ABGR8888:
13405 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13406 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13407 return true;
13408 /* fall through */
13409 case DRM_FORMAT_RGB565:
13410 case DRM_FORMAT_XRGB2101010:
13411 case DRM_FORMAT_XBGR2101010:
13412 case DRM_FORMAT_YUYV:
13413 case DRM_FORMAT_YVYU:
13414 case DRM_FORMAT_UYVY:
13415 case DRM_FORMAT_VYUY:
13416 case DRM_FORMAT_NV12:
13417 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13418 return true;
13419 /* fall through */
13420 case DRM_FORMAT_C8:
13421 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13422 modifier == I915_FORMAT_MOD_X_TILED ||
13423 modifier == I915_FORMAT_MOD_Y_TILED)
13424 return true;
13425 /* fall through */
13426 default:
13427 return false;
13428 }
13429 }
13431 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
13432 u32 format, u64 modifier)
13433 {
13434 return modifier == DRM_FORMAT_MOD_LINEAR &&
13435 format == DRM_FORMAT_ARGB8888;
13436 }
13438 static struct drm_plane_funcs skl_plane_funcs = {
13439 .update_plane = drm_atomic_helper_update_plane,
13440 .disable_plane = drm_atomic_helper_disable_plane,
13441 .destroy = intel_plane_destroy,
13442 .atomic_get_property = intel_plane_atomic_get_property,
13443 .atomic_set_property = intel_plane_atomic_set_property,
13444 .atomic_duplicate_state = intel_plane_duplicate_state,
13445 .atomic_destroy_state = intel_plane_destroy_state,
13446 .format_mod_supported = skl_plane_format_mod_supported,
13447 };
13449 static struct drm_plane_funcs i965_plane_funcs = {
13450 .update_plane = drm_atomic_helper_update_plane,
13451 .disable_plane = drm_atomic_helper_disable_plane,
13452 .destroy = intel_plane_destroy,
13453 .atomic_get_property = intel_plane_atomic_get_property,
13454 .atomic_set_property = intel_plane_atomic_set_property,
13455 .atomic_duplicate_state = intel_plane_duplicate_state,
13456 .atomic_destroy_state = intel_plane_destroy_state,
13457 .format_mod_supported = i965_plane_format_mod_supported,
13458 };
13460 static struct drm_plane_funcs i8xx_plane_funcs = {
13461 .update_plane = drm_atomic_helper_update_plane,
13462 .disable_plane = drm_atomic_helper_disable_plane,
13463 .destroy = intel_plane_destroy,
13464 .atomic_get_property = intel_plane_atomic_get_property,
13465 .atomic_set_property = intel_plane_atomic_set_property,
13466 .atomic_duplicate_state = intel_plane_duplicate_state,
13467 .atomic_destroy_state = intel_plane_destroy_state,
13468 .format_mod_supported = i8xx_plane_format_mod_supported,
13469 };
13471 static int
13472 intel_legacy_cursor_update(struct drm_plane *plane,
13473 struct drm_crtc *crtc,
13474 struct drm_framebuffer *fb,
13475 int crtc_x, int crtc_y,
13476 unsigned int crtc_w, unsigned int crtc_h,
13477 uint32_t src_x, uint32_t src_y,
13478 uint32_t src_w, uint32_t src_h,
13479 struct drm_modeset_acquire_ctx *ctx)
13480 {
13481 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13482 int ret;
13483 struct drm_plane_state *old_plane_state, *new_plane_state;
13484 struct intel_plane *intel_plane = to_intel_plane(plane);
13485 struct drm_framebuffer *old_fb;
13486 struct drm_crtc_state *crtc_state = crtc->state;
13488 /*
13489 * When crtc is inactive or there is a modeset pending,
13490 * wait for it to complete in the slowpath
13491 */
13492 if (!crtc_state->active || needs_modeset(crtc_state) ||
13493 to_intel_crtc_state(crtc_state)->update_pipe)
13494 goto slow;
13496 old_plane_state = plane->state;
13497 /*
13498 * Don't do an async update if there is an outstanding commit modifying
13499 * the plane. This prevents our async update's changes from getting
13500 * overridden by a previous synchronous update's state.
13501 */
13502 if (old_plane_state->commit &&
13503 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13504 goto slow;
13506 /*
13507 * If any parameters change that may affect watermarks,
13508 * take the slowpath. Only changing fb or position should be
13509 * in the fastpath.
13510 */
13511 if (old_plane_state->crtc != crtc ||
13512 old_plane_state->src_w != src_w ||
13513 old_plane_state->src_h != src_h ||
13514 old_plane_state->crtc_w != crtc_w ||
13515 old_plane_state->crtc_h != crtc_h ||
13516 !old_plane_state->fb != !fb)
13517 goto slow;
13519 new_plane_state = intel_plane_duplicate_state(plane);
13520 if (!new_plane_state)
13521 return -ENOMEM;
13523 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13525 new_plane_state->src_x = src_x;
13526 new_plane_state->src_y = src_y;
13527 new_plane_state->src_w = src_w;
13528 new_plane_state->src_h = src_h;
13529 new_plane_state->crtc_x = crtc_x;
13530 new_plane_state->crtc_y = crtc_y;
13531 new_plane_state->crtc_w = crtc_w;
13532 new_plane_state->crtc_h = crtc_h;
13534 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13535 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13536 to_intel_plane_state(plane->state),
13537 to_intel_plane_state(new_plane_state));
13538 if (ret)
13539 goto out_free;
13541 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13542 if (ret)
13543 goto out_free;
13545 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13546 if (ret)
13547 goto out_unlock;
13549 intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
13551 old_fb = old_plane_state->fb;
13552 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13553 intel_plane->frontbuffer_bit);
13555 /* Swap plane state */
13556 plane->state = new_plane_state;
13558 if (plane->state->visible) {
13559 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13560 intel_plane->update_plane(intel_plane,
13561 to_intel_crtc_state(crtc->state),
13562 to_intel_plane_state(plane->state));
13563 } else {
13564 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13565 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13566 }
13568 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13570 out_unlock:
13571 mutex_unlock(&dev_priv->drm.struct_mutex);
13572 out_free:
13573 if (ret)
13574 intel_plane_destroy_state(plane, new_plane_state);
13575 else
13576 intel_plane_destroy_state(plane, old_plane_state);
13577 return ret;
13579 slow:
13580 return drm_atomic_helper_update_plane(plane, crtc, fb,
13581 crtc_x, crtc_y, crtc_w, crtc_h,
13582 src_x, src_y, src_w, src_h, ctx);
13583 }
13585 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13586 .update_plane = intel_legacy_cursor_update,
13587 .disable_plane = drm_atomic_helper_disable_plane,
13588 .destroy = intel_plane_destroy,
13589 .atomic_get_property = intel_plane_atomic_get_property,
13590 .atomic_set_property = intel_plane_atomic_set_property,
13591 .atomic_duplicate_state = intel_plane_duplicate_state,
13592 .atomic_destroy_state = intel_plane_destroy_state,
13593 .format_mod_supported = intel_cursor_format_mod_supported,
13594 };
13596 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13597 enum i9xx_plane_id i9xx_plane)
13598 {
13599 if (!HAS_FBC(dev_priv))
13600 return false;
13602 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13603 return i9xx_plane == PLANE_A; /* tied to pipe A */
13604 else if (IS_IVYBRIDGE(dev_priv))
13605 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13606 i9xx_plane == PLANE_C;
13607 else if (INTEL_GEN(dev_priv) >= 4)
13608 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13609 else
13610 return i9xx_plane == PLANE_A;
13611 }
13613 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13614 enum pipe pipe, enum plane_id plane_id)
13615 {
13616 if (!HAS_FBC(dev_priv))
13617 return false;
13619 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13620 }
13622 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
13623 enum pipe pipe, enum plane_id plane_id)
13624 {
13625 if (plane_id == PLANE_PRIMARY) {
13626 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13627 return false;
13628 else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
13629 !IS_GEMINILAKE(dev_priv))
13630 return false;
13631 } else if (plane_id >= PLANE_SPRITE0) {
13632 if (plane_id == PLANE_CURSOR)
13633 return false;
13634 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
13635 if (plane_id != PLANE_SPRITE0)
13636 return false;
13637 } else {
13638 if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
13639 IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13640 return false;
13641 }
13642 }
13643 return true;
13644 }
13646 static struct intel_plane *
13647 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13648 {
13649 struct intel_plane *primary = NULL;
13650 struct intel_plane_state *state = NULL;
13651 const struct drm_plane_funcs *plane_funcs;
13652 const uint32_t *intel_primary_formats;
13653 unsigned int supported_rotations;
13654 unsigned int num_formats;
13655 const uint64_t *modifiers;
13656 int ret;
13658 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13659 if (!primary) {
13660 ret = -ENOMEM;
13661 goto fail;
13662 }
13664 state = intel_create_plane_state(&primary->base);
13665 if (!state) {
13666 ret = -ENOMEM;
13667 goto fail;
13668 }
13670 primary->base.state = &state->base;
13672 primary->can_scale = false;
13673 primary->max_downscale = 1;
13674 if (INTEL_GEN(dev_priv) >= 9) {
13675 primary->can_scale = true;
13676 state->scaler_id = -1;
13677 }
13678 primary->pipe = pipe;
13679 /*
13680 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13681 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13682 */
13683 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13684 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13685 else
13686 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13687 primary->id = PLANE_PRIMARY;
13688 primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13690 if (INTEL_GEN(dev_priv) >= 9)
13691 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13692 primary->pipe,
13693 primary->id);
13694 else
13695 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13696 primary->i9xx_plane);
13698 if (primary->has_fbc) {
13699 struct intel_fbc *fbc = &dev_priv->fbc;
13701 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13702 }
13704 primary->check_plane = intel_check_primary_plane;
13706 if (INTEL_GEN(dev_priv) >= 9) {
13707 primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
13708 PLANE_PRIMARY);
13710 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13711 intel_primary_formats = skl_pri_planar_formats;
13712 num_formats = ARRAY_SIZE(skl_pri_planar_formats);
13713 } else {
13714 intel_primary_formats = skl_primary_formats;
13715 num_formats = ARRAY_SIZE(skl_primary_formats);
13716 }
13718 if (primary->has_ccs)
13719 modifiers = skl_format_modifiers_ccs;
13720 else
13721 modifiers = skl_format_modifiers_noccs;
13723 primary->update_plane = skl_update_plane;
13724 primary->disable_plane = skl_disable_plane;
13725 primary->get_hw_state = skl_plane_get_hw_state;
13727 plane_funcs = &skl_plane_funcs;
13728 } else if (INTEL_GEN(dev_priv) >= 4) {
13729 intel_primary_formats = i965_primary_formats;
13730 num_formats = ARRAY_SIZE(i965_primary_formats);
13731 modifiers = i9xx_format_modifiers;
13733 primary->update_plane = i9xx_update_plane;
13734 primary->disable_plane = i9xx_disable_plane;
13735 primary->get_hw_state = i9xx_plane_get_hw_state;
13737 plane_funcs = &i965_plane_funcs;
13738 } else {
13739 intel_primary_formats = i8xx_primary_formats;
13740 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13741 modifiers = i9xx_format_modifiers;
13743 primary->update_plane = i9xx_update_plane;
13744 primary->disable_plane = i9xx_disable_plane;
13745 primary->get_hw_state = i9xx_plane_get_hw_state;
13747 plane_funcs = &i8xx_plane_funcs;
13748 }
13750 if (INTEL_GEN(dev_priv) >= 9)
13751 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13752 0, plane_funcs,
13753 intel_primary_formats, num_formats,
13754 modifiers,
13755 DRM_PLANE_TYPE_PRIMARY,
13756 "plane 1%c", pipe_name(pipe));
13757 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13758 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13759 0, plane_funcs,
13760 intel_primary_formats, num_formats,
13761 modifiers,
13762 DRM_PLANE_TYPE_PRIMARY,
13763 "primary %c", pipe_name(pipe));
13764 else
13765 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13766 0, plane_funcs,
13767 intel_primary_formats, num_formats,
13768 modifiers,
13769 DRM_PLANE_TYPE_PRIMARY,
13770 "plane %c",
13771 plane_name(primary->i9xx_plane));
13772 if (ret)
13773 goto fail;
13775 if (INTEL_GEN(dev_priv) >= 10) {
13776 supported_rotations =
13777 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13778 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13779 DRM_MODE_REFLECT_X;
13780 } else if (INTEL_GEN(dev_priv) >= 9) {
13781 supported_rotations =
13782 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13783 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13784 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13785 supported_rotations =
13786 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13787 DRM_MODE_REFLECT_X;
13788 } else if (INTEL_GEN(dev_priv) >= 4) {
13789 supported_rotations =
13790 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13791 } else {
13792 supported_rotations = DRM_MODE_ROTATE_0;
13793 }
13795 if (INTEL_GEN(dev_priv) >= 4)
13796 drm_plane_create_rotation_property(&primary->base,
13797 DRM_MODE_ROTATE_0,
13798 supported_rotations);
13800 if (INTEL_GEN(dev_priv) >= 9)
13801 drm_plane_create_color_properties(&primary->base,
13802 BIT(DRM_COLOR_YCBCR_BT601) |
13803 BIT(DRM_COLOR_YCBCR_BT709),
13804 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13805 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13806 DRM_COLOR_YCBCR_BT709,
13807 DRM_COLOR_YCBCR_LIMITED_RANGE);
13809 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13811 return primary;
13813 fail:
13814 kfree(state);
13815 kfree(primary);
13817 return ERR_PTR(ret);
13818 }
13820 static struct intel_plane *
13821 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13822 enum pipe pipe)
13823 {
13824 struct intel_plane *cursor = NULL;
13825 struct intel_plane_state *state = NULL;
13826 int ret;
13828 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13829 if (!cursor) {
13830 ret = -ENOMEM;
13831 goto fail;
13832 }
13834 state = intel_create_plane_state(&cursor->base);
13835 if (!state) {
13836 ret = -ENOMEM;
13837 goto fail;
13838 }
13840 cursor->base.state = &state->base;
13842 cursor->can_scale = false;
13843 cursor->max_downscale = 1;
13844 cursor->pipe = pipe;
13845 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13846 cursor->id = PLANE_CURSOR;
13847 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13849 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13850 cursor->update_plane = i845_update_cursor;
13851 cursor->disable_plane = i845_disable_cursor;
13852 cursor->get_hw_state = i845_cursor_get_hw_state;
13853 cursor->check_plane = i845_check_cursor;
13854 } else {
13855 cursor->update_plane = i9xx_update_cursor;
13856 cursor->disable_plane = i9xx_disable_cursor;
13857 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13858 cursor->check_plane = i9xx_check_cursor;
13859 }
13861 cursor->cursor.base = ~0;
13862 cursor->cursor.cntl = ~0;
13864 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13865 cursor->cursor.size = ~0;
13867 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13868 0, &intel_cursor_plane_funcs,
13869 intel_cursor_formats,
13870 ARRAY_SIZE(intel_cursor_formats),
13871 cursor_format_modifiers,
13872 DRM_PLANE_TYPE_CURSOR,
13873 "cursor %c", pipe_name(pipe));
13874 if (ret)
13875 goto fail;
13877 if (INTEL_GEN(dev_priv) >= 4)
13878 drm_plane_create_rotation_property(&cursor->base,
13879 DRM_MODE_ROTATE_0,
13880 DRM_MODE_ROTATE_0 |
13881 DRM_MODE_ROTATE_180);
13883 if (INTEL_GEN(dev_priv) >= 9)
13884 state->scaler_id = -1;
13886 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13888 return cursor;
13890 fail:
13891 kfree(state);
13892 kfree(cursor);
13894 return ERR_PTR(ret);
13895 }
13897 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13898 struct intel_crtc_state *crtc_state)
13899 {
13900 struct intel_crtc_scaler_state *scaler_state =
13901 &crtc_state->scaler_state;
13902 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13903 int i;
13905 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13906 if (!crtc->num_scalers)
13907 return;
13909 for (i = 0; i < crtc->num_scalers; i++) {
13910 struct intel_scaler *scaler = &scaler_state->scalers[i];
13912 scaler->in_use = 0;
13913 scaler->mode = PS_SCALER_MODE_DYN;
13914 }
13916 scaler_state->scaler_id = -1;
13917 }
13919 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13920 {
13921 struct intel_crtc *intel_crtc;
13922 struct intel_crtc_state *crtc_state = NULL;
13923 struct intel_plane *primary = NULL;
13924 struct intel_plane *cursor = NULL;
13925 int sprite, ret;
13927 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13928 if (!intel_crtc)
13929 return -ENOMEM;
13931 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13932 if (!crtc_state) {
13933 ret = -ENOMEM;
13934 goto fail;
13935 }
13936 intel_crtc->config = crtc_state;
13937 intel_crtc->base.state = &crtc_state->base;
13938 crtc_state->base.crtc = &intel_crtc->base;
13940 primary = intel_primary_plane_create(dev_priv, pipe);
13941 if (IS_ERR(primary)) {
13942 ret = PTR_ERR(primary);
13943 goto fail;
13944 }
13945 intel_crtc->plane_ids_mask |= BIT(primary->id);
13947 for_each_sprite(dev_priv, pipe, sprite) {
13948 struct intel_plane *plane;
13950 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13951 if (IS_ERR(plane)) {
13952 ret = PTR_ERR(plane);
13953 goto fail;
13954 }
13955 intel_crtc->plane_ids_mask |= BIT(plane->id);
13956 }
13958 cursor = intel_cursor_plane_create(dev_priv, pipe);
13959 if (IS_ERR(cursor)) {
13960 ret = PTR_ERR(cursor);
13961 goto fail;
13962 }
13963 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13965 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13966 &primary->base, &cursor->base,
13967 &intel_crtc_funcs,
13968 "pipe %c", pipe_name(pipe));
13969 if (ret)
13970 goto fail;
13972 intel_crtc->pipe = pipe;
13974 /* initialize shared scalers */
13975 intel_crtc_init_scalers(intel_crtc, crtc_state);
13977 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
13978 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
13979 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
13981 if (INTEL_GEN(dev_priv) < 9) {
13982 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
13984 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13985 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
13986 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
13987 }
13989 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13991 intel_color_init(&intel_crtc->base);
13993 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13995 return 0;
13997 fail:
13998 /*
13999 * drm_mode_config_cleanup() will free up any
14000 * crtcs/planes already initialized.
14001 */
14002 kfree(crtc_state);
14003 kfree(intel_crtc);
14005 return ret;
14006 }
14008 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14009 {
14010 struct drm_device *dev = connector->base.dev;
14012 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14014 if (!connector->base.state->crtc)
14015 return INVALID_PIPE;
14017 return to_intel_crtc(connector->base.state->crtc)->pipe;
14018 }
14020 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14021 struct drm_file *file)
14022 {
14023 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14024 struct drm_crtc *drmmode_crtc;
14025 struct intel_crtc *crtc;
14027 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14028 if (!drmmode_crtc)
14029 return -ENOENT;
14031 crtc = to_intel_crtc(drmmode_crtc);
14032 pipe_from_crtc_id->pipe = crtc->pipe;
14034 return 0;
14035 }
14037 static int intel_encoder_clones(struct intel_encoder *encoder)
14038 {
14039 struct drm_device *dev = encoder->base.dev;
14040 struct intel_encoder *source_encoder;
14041 int index_mask = 0;
14042 int entry = 0;
14044 for_each_intel_encoder(dev, source_encoder) {
14045 if (encoders_cloneable(encoder, source_encoder))
14046 index_mask |= (1 << entry);
14048 entry++;
14049 }
14051 return index_mask;
14052 }
14054 static bool has_edp_a(struct drm_i915_private *dev_priv)
14055 {
14056 if (!IS_MOBILE(dev_priv))
14057 return false;
14059 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14060 return false;
14062 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14063 return false;
14065 return true;
14066 }
14068 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14069 {
14070 if (INTEL_GEN(dev_priv) >= 9)
14071 return false;
14073 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14074 return false;
14076 if (IS_CHERRYVIEW(dev_priv))
14077 return false;
14079 if (HAS_PCH_LPT_H(dev_priv) &&
14080 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14081 return false;
14083 /* DDI E can't be used if DDI A requires 4 lanes */
14084 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14085 return false;
14087 if (!dev_priv->vbt.int_crt_support)
14088 return false;
14090 return true;
14091 }
14093 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14094 {
14095 int pps_num;
14096 int pps_idx;
14098 if (HAS_DDI(dev_priv))
14099 return;
14100 /*
14101 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14102 * everywhere where registers can be write protected.
14103 */
14104 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14105 pps_num = 2;
14106 else
14107 pps_num = 1;
14109 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14110 u32 val = I915_READ(PP_CONTROL(pps_idx));
14112 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14113 I915_WRITE(PP_CONTROL(pps_idx), val);
14114 }
14115 }
14117 static void intel_pps_init(struct drm_i915_private *dev_priv)
14118 {
14119 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14120 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14121 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14122 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14123 else
14124 dev_priv->pps_mmio_base = PPS_BASE;
14126 intel_pps_unlock_regs_wa(dev_priv);
14127 }
14129 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14130 {
14131 struct intel_encoder *encoder;
14132 bool dpd_is_edp = false;
14134 intel_pps_init(dev_priv);
14136 /*
14137 * intel_edp_init_connector() depends on this completing first, to
14138 * prevent the registeration of both eDP and LVDS and the incorrect
14139 * sharing of the PPS.
14140 */
14141 intel_lvds_init(dev_priv);
14143 if (intel_crt_present(dev_priv))
14144 intel_crt_init(dev_priv);
14146 if (IS_ICELAKE(dev_priv)) {
14147 intel_ddi_init(dev_priv, PORT_A);
14148 intel_ddi_init(dev_priv, PORT_B);
14149 intel_ddi_init(dev_priv, PORT_C);
14150 intel_ddi_init(dev_priv, PORT_D);
14151 intel_ddi_init(dev_priv, PORT_E);
14152 intel_ddi_init(dev_priv, PORT_F);
14153 } else if (IS_GEN9_LP(dev_priv)) {
14154 /*
14155 * FIXME: Broxton doesn't support port detection via the
14156 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14157 * detect the ports.
14158 */
14159 intel_ddi_init(dev_priv, PORT_A);
14160 intel_ddi_init(dev_priv, PORT_B);
14161 intel_ddi_init(dev_priv, PORT_C);
14163 vlv_dsi_init(dev_priv);
14164 } else if (HAS_DDI(dev_priv)) {
14165 int found;
14167 /*
14168 * Haswell uses DDI functions to detect digital outputs.
14169 * On SKL pre-D0 the strap isn't connected, so we assume
14170 * it's there.
14171 */
14172 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14173 /* WaIgnoreDDIAStrap: skl */
14174 if (found || IS_GEN9_BC(dev_priv))
14175 intel_ddi_init(dev_priv, PORT_A);
14177 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14178 * register */
14179 found = I915_READ(SFUSE_STRAP);
14181 if (found & SFUSE_STRAP_DDIB_DETECTED)
14182 intel_ddi_init(dev_priv, PORT_B);
14183 if (found & SFUSE_STRAP_DDIC_DETECTED)
14184 intel_ddi_init(dev_priv, PORT_C);
14185 if (found & SFUSE_STRAP_DDID_DETECTED)
14186 intel_ddi_init(dev_priv, PORT_D);
14187 if (found & SFUSE_STRAP_DDIF_DETECTED)
14188 intel_ddi_init(dev_priv, PORT_F);
14189 /*
14190 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14191 */
14192 if (IS_GEN9_BC(dev_priv) &&
14193 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14194 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14195 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14196 intel_ddi_init(dev_priv, PORT_E);
14198 } else if (HAS_PCH_SPLIT(dev_priv)) {
14199 int found;
14200 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14202 if (has_edp_a(dev_priv))
14203 intel_dp_init(dev_priv, DP_A, PORT_A);
14205 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14206 /* PCH SDVOB multiplex with HDMIB */
14207 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14208 if (!found)
14209 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14210 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14211 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14212 }
14214 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14215 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14217 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14218 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14220 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14221 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14223 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14224 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14225 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14226 bool has_edp, has_port;
14228 /*
14229 * The DP_DETECTED bit is the latched state of the DDC
14230 * SDA pin at boot. However since eDP doesn't require DDC
14231 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14232 * eDP ports may have been muxed to an alternate function.
14233 * Thus we can't rely on the DP_DETECTED bit alone to detect
14234 * eDP ports. Consult the VBT as well as DP_DETECTED to
14235 * detect eDP ports.
14236 *
14237 * Sadly the straps seem to be missing sometimes even for HDMI
14238 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14239 * and VBT for the presence of the port. Additionally we can't
14240 * trust the port type the VBT declares as we've seen at least
14241 * HDMI ports that the VBT claim are DP or eDP.
14242 */
14243 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14244 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14245 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14246 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14247 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14248 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14250 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14251 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14252 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14253 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14254 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14255 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14257 if (IS_CHERRYVIEW(dev_priv)) {
14258 /*
14259 * eDP not supported on port D,
14260 * so no need to worry about it
14261 */
14262 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14263 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14264 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14265 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14266 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14267 }
14269 vlv_dsi_init(dev_priv);
14270 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14271 bool found = false;
14273 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14274 DRM_DEBUG_KMS("probing SDVOB\n");
14275 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14276 if (!found && IS_G4X(dev_priv)) {
14277 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14278 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14279 }
14281 if (!found && IS_G4X(dev_priv))
14282 intel_dp_init(dev_priv, DP_B, PORT_B);
14283 }
14285 /* Before G4X SDVOC doesn't have its own detect register */
14287 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14288 DRM_DEBUG_KMS("probing SDVOC\n");
14289 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14290 }
14292 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14294 if (IS_G4X(dev_priv)) {
14295 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14296 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14297 }
14298 if (IS_G4X(dev_priv))
14299 intel_dp_init(dev_priv, DP_C, PORT_C);
14300 }
14302 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14303 intel_dp_init(dev_priv, DP_D, PORT_D);
14304 } else if (IS_GEN2(dev_priv))
14305 intel_dvo_init(dev_priv);
14307 if (SUPPORTS_TV(dev_priv))
14308 intel_tv_init(dev_priv);
14310 intel_psr_init(dev_priv);
14312 for_each_intel_encoder(&dev_priv->drm, encoder) {
14313 encoder->base.possible_crtcs = encoder->crtc_mask;
14314 encoder->base.possible_clones =
14315 intel_encoder_clones(encoder);
14316 }
14318 intel_init_pch_refclk(dev_priv);
14320 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14321 }
14323 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14324 {
14325 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14326 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14328 drm_framebuffer_cleanup(fb);
14330 i915_gem_object_lock(obj);
14331 WARN_ON(!obj->framebuffer_references--);
14332 i915_gem_object_unlock(obj);
14334 i915_gem_object_put(obj);
14336 kfree(intel_fb);
14337 }
14339 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14340 struct drm_file *file,
14341 unsigned int *handle)
14342 {
14343 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14345 if (obj->userptr.mm) {
14346 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14347 return -EINVAL;
14348 }
14350 return drm_gem_handle_create(file, &obj->base, handle);
14351 }
14353 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14354 struct drm_file *file,
14355 unsigned flags, unsigned color,
14356 struct drm_clip_rect *clips,
14357 unsigned num_clips)
14358 {
14359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14361 i915_gem_object_flush_if_display(obj);
14362 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14364 return 0;
14365 }
14367 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14368 .destroy = intel_user_framebuffer_destroy,
14369 .create_handle = intel_user_framebuffer_create_handle,
14370 .dirty = intel_user_framebuffer_dirty,
14371 };
14373 static
14374 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14375 uint64_t fb_modifier, uint32_t pixel_format)
14376 {
14377 u32 gen = INTEL_GEN(dev_priv);
14379 if (gen >= 9) {
14380 int cpp = drm_format_plane_cpp(pixel_format, 0);
14382 /* "The stride in bytes must not exceed the of the size of 8K
14383 * pixels and 32K bytes."
14384 */
14385 return min(8192 * cpp, 32768);
14386 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14387 return 32*1024;
14388 } else if (gen >= 4) {
14389 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14390 return 16*1024;
14391 else
14392 return 32*1024;
14393 } else if (gen >= 3) {
14394 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14395 return 8*1024;
14396 else
14397 return 16*1024;
14398 } else {
14399 /* XXX DSPC is limited to 4k tiled */
14400 return 8*1024;
14401 }
14402 }
14404 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14405 struct drm_i915_gem_object *obj,
14406 struct drm_mode_fb_cmd2 *mode_cmd)
14407 {
14408 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14409 struct drm_framebuffer *fb = &intel_fb->base;
14410 struct drm_format_name_buf format_name;
14411 u32 pitch_limit;
14412 unsigned int tiling, stride;
14413 int ret = -EINVAL;
14414 int i;
14416 i915_gem_object_lock(obj);
14417 obj->framebuffer_references++;
14418 tiling = i915_gem_object_get_tiling(obj);
14419 stride = i915_gem_object_get_stride(obj);
14420 i915_gem_object_unlock(obj);
14422 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14423 /*
14424 * If there's a fence, enforce that
14425 * the fb modifier and tiling mode match.
14426 */
14427 if (tiling != I915_TILING_NONE &&
14428 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14429 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14430 goto err;
14431 }
14432 } else {
14433 if (tiling == I915_TILING_X) {
14434 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14435 } else if (tiling == I915_TILING_Y) {
14436 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14437 goto err;
14438 }
14439 }
14441 /* Passed in modifier sanity checking. */
14442 switch (mode_cmd->modifier[0]) {
14443 case I915_FORMAT_MOD_Y_TILED_CCS:
14444 case I915_FORMAT_MOD_Yf_TILED_CCS:
14445 switch (mode_cmd->pixel_format) {
14446 case DRM_FORMAT_XBGR8888:
14447 case DRM_FORMAT_ABGR8888:
14448 case DRM_FORMAT_XRGB8888:
14449 case DRM_FORMAT_ARGB8888:
14450 break;
14451 default:
14452 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14453 goto err;
14454 }
14455 /* fall through */
14456 case I915_FORMAT_MOD_Y_TILED:
14457 case I915_FORMAT_MOD_Yf_TILED:
14458 if (INTEL_GEN(dev_priv) < 9) {
14459 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14460 mode_cmd->modifier[0]);
14461 goto err;
14462 }
14463 case DRM_FORMAT_MOD_LINEAR:
14464 case I915_FORMAT_MOD_X_TILED:
14465 break;
14466 default:
14467 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14468 mode_cmd->modifier[0]);
14469 goto err;
14470 }
14472 /*
14473 * gen2/3 display engine uses the fence if present,
14474 * so the tiling mode must match the fb modifier exactly.
14475 */
14476 if (INTEL_GEN(dev_priv) < 4 &&
14477 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14478 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14479 goto err;
14480 }
14482 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14483 mode_cmd->pixel_format);
14484 if (mode_cmd->pitches[0] > pitch_limit) {
14485 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14486 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14487 "tiled" : "linear",
14488 mode_cmd->pitches[0], pitch_limit);
14489 goto err;
14490 }
14492 /*
14493 * If there's a fence, enforce that
14494 * the fb pitch and fence stride match.
14495 */
14496 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14497 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14498 mode_cmd->pitches[0], stride);
14499 goto err;
14500 }
14502 /* Reject formats not supported by any plane early. */
14503 switch (mode_cmd->pixel_format) {
14504 case DRM_FORMAT_C8:
14505 case DRM_FORMAT_RGB565:
14506 case DRM_FORMAT_XRGB8888:
14507 case DRM_FORMAT_ARGB8888:
14508 break;
14509 case DRM_FORMAT_XRGB1555:
14510 if (INTEL_GEN(dev_priv) > 3) {
14511 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14512 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14513 goto err;
14514 }
14515 break;
14516 case DRM_FORMAT_ABGR8888:
14517 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14518 INTEL_GEN(dev_priv) < 9) {
14519 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14520 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14521 goto err;
14522 }
14523 break;
14524 case DRM_FORMAT_XBGR8888:
14525 case DRM_FORMAT_XRGB2101010:
14526 case DRM_FORMAT_XBGR2101010:
14527 if (INTEL_GEN(dev_priv) < 4) {
14528 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14529 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14530 goto err;
14531 }
14532 break;
14533 case DRM_FORMAT_ABGR2101010:
14534 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14535 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14536 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14537 goto err;
14538 }
14539 break;
14540 case DRM_FORMAT_YUYV:
14541 case DRM_FORMAT_UYVY:
14542 case DRM_FORMAT_YVYU:
14543 case DRM_FORMAT_VYUY:
14544 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14545 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14546 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14547 goto err;
14548 }
14549 break;
14550 case DRM_FORMAT_NV12:
14551 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14552 IS_BROXTON(dev_priv)) {
14553 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14554 drm_get_format_name(mode_cmd->pixel_format,
14555 &format_name));
14556 goto err;
14557 }
14558 break;
14559 default:
14560 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14561 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14562 goto err;
14563 }
14565 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14566 if (mode_cmd->offsets[0] != 0)
14567 goto err;
14569 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14571 if (fb->format->format == DRM_FORMAT_NV12 &&
14572 (fb->width < SKL_MIN_YUV_420_SRC_W ||
14573 fb->height < SKL_MIN_YUV_420_SRC_H ||
14574 (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14575 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14576 return -EINVAL;
14577 }
14579 for (i = 0; i < fb->format->num_planes; i++) {
14580 u32 stride_alignment;
14582 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14583 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14584 goto err;
14585 }
14587 stride_alignment = intel_fb_stride_alignment(fb, i);
14589 /*
14590 * Display WA #0531: skl,bxt,kbl,glk
14591 *
14592 * Render decompression and plane width > 3840
14593 * combined with horizontal panning requires the
14594 * plane stride to be a multiple of 4. We'll just
14595 * require the entire fb to accommodate that to avoid
14596 * potential runtime errors at plane configuration time.
14597 */
14598 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14599 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14600 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14601 stride_alignment *= 4;
14603 if (fb->pitches[i] & (stride_alignment - 1)) {
14604 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14605 i, fb->pitches[i], stride_alignment);
14606 goto err;
14607 }
14609 fb->obj[i] = &obj->base;
14610 }
14612 ret = intel_fill_fb_info(dev_priv, fb);
14613 if (ret)
14614 goto err;
14616 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14617 if (ret) {
14618 DRM_ERROR("framebuffer init failed %d\n", ret);
14619 goto err;
14620 }
14622 return 0;
14624 err:
14625 i915_gem_object_lock(obj);
14626 obj->framebuffer_references--;
14627 i915_gem_object_unlock(obj);
14628 return ret;
14629 }
14631 static struct drm_framebuffer *
14632 intel_user_framebuffer_create(struct drm_device *dev,
14633 struct drm_file *filp,
14634 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14635 {
14636 struct drm_framebuffer *fb;
14637 struct drm_i915_gem_object *obj;
14638 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14640 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14641 if (!obj)
14642 return ERR_PTR(-ENOENT);
14644 fb = intel_framebuffer_create(obj, &mode_cmd);
14645 if (IS_ERR(fb))
14646 i915_gem_object_put(obj);
14648 return fb;
14649 }
14651 static void intel_atomic_state_free(struct drm_atomic_state *state)
14652 {
14653 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14655 drm_atomic_state_default_release(state);
14657 i915_sw_fence_fini(&intel_state->commit_ready);
14659 kfree(state);
14660 }
14662 static enum drm_mode_status
14663 intel_mode_valid(struct drm_device *dev,
14664 const struct drm_display_mode *mode)
14665 {
14666 struct drm_i915_private *dev_priv = to_i915(dev);
14667 int hdisplay_max, htotal_max;
14668 int vdisplay_max, vtotal_max;
14670 /*
14671 * Can't reject DBLSCAN here because Xorg ddxen can add piles
14672 * of DBLSCAN modes to the output's mode list when they detect
14673 * the scaling mode property on the connector. And they don't
14674 * ask the kernel to validate those modes in any way until
14675 * modeset time at which point the client gets a protocol error.
14676 * So in order to not upset those clients we silently ignore the
14677 * DBLSCAN flag on such connectors. For other connectors we will
14678 * reject modes with the DBLSCAN flag in encoder->compute_config().
14679 * And we always reject DBLSCAN modes in connector->mode_valid()
14680 * as we never want such modes on the connector's mode list.
14681 */
14683 if (mode->vscan > 1)
14684 return MODE_NO_VSCAN;
14686 if (mode->flags & DRM_MODE_FLAG_HSKEW)
14687 return MODE_H_ILLEGAL;
14689 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14690 DRM_MODE_FLAG_NCSYNC |
14691 DRM_MODE_FLAG_PCSYNC))
14692 return MODE_HSYNC;
14694 if (mode->flags & (DRM_MODE_FLAG_BCAST |
14695 DRM_MODE_FLAG_PIXMUX |
14696 DRM_MODE_FLAG_CLKDIV2))
14697 return MODE_BAD;
14699 if (INTEL_GEN(dev_priv) >= 9 ||
14700 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
14701 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
14702 vdisplay_max = 4096;
14703 htotal_max = 8192;
14704 vtotal_max = 8192;
14705 } else if (INTEL_GEN(dev_priv) >= 3) {
14706 hdisplay_max = 4096;
14707 vdisplay_max = 4096;
14708 htotal_max = 8192;
14709 vtotal_max = 8192;
14710 } else {
14711 hdisplay_max = 2048;
14712 vdisplay_max = 2048;
14713 htotal_max = 4096;
14714 vtotal_max = 4096;
14715 }
14717 if (mode->hdisplay > hdisplay_max ||
14718 mode->hsync_start > htotal_max ||
14719 mode->hsync_end > htotal_max ||
14720 mode->htotal > htotal_max)
14721 return MODE_H_ILLEGAL;
14723 if (mode->vdisplay > vdisplay_max ||
14724 mode->vsync_start > vtotal_max ||
14725 mode->vsync_end > vtotal_max ||
14726 mode->vtotal > vtotal_max)
14727 return MODE_V_ILLEGAL;
14729 return MODE_OK;
14730 }
14732 static const struct drm_mode_config_funcs intel_mode_funcs = {
14733 .fb_create = intel_user_framebuffer_create,
14734 .get_format_info = intel_get_format_info,
14735 .output_poll_changed = intel_fbdev_output_poll_changed,
14736 .mode_valid = intel_mode_valid,
14737 .atomic_check = intel_atomic_check,
14738 .atomic_commit = intel_atomic_commit,
14739 .atomic_state_alloc = intel_atomic_state_alloc,
14740 .atomic_state_clear = intel_atomic_state_clear,
14741 .atomic_state_free = intel_atomic_state_free,
14742 };
14744 /**
14745 * intel_init_display_hooks - initialize the display modesetting hooks
14746 * @dev_priv: device private
14747 */
14748 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14749 {
14750 intel_init_cdclk_hooks(dev_priv);
14752 if (INTEL_GEN(dev_priv) >= 9) {
14753 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14754 dev_priv->display.get_initial_plane_config =
14755 skylake_get_initial_plane_config;
14756 dev_priv->display.crtc_compute_clock =
14757 haswell_crtc_compute_clock;
14758 dev_priv->display.crtc_enable = haswell_crtc_enable;
14759 dev_priv->display.crtc_disable = haswell_crtc_disable;
14760 } else if (HAS_DDI(dev_priv)) {
14761 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14762 dev_priv->display.get_initial_plane_config =
14763 i9xx_get_initial_plane_config;
14764 dev_priv->display.crtc_compute_clock =
14765 haswell_crtc_compute_clock;
14766 dev_priv->display.crtc_enable = haswell_crtc_enable;
14767 dev_priv->display.crtc_disable = haswell_crtc_disable;
14768 } else if (HAS_PCH_SPLIT(dev_priv)) {
14769 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14770 dev_priv->display.get_initial_plane_config =
14771 i9xx_get_initial_plane_config;
14772 dev_priv->display.crtc_compute_clock =
14773 ironlake_crtc_compute_clock;
14774 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14775 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14776 } else if (IS_CHERRYVIEW(dev_priv)) {
14777 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14778 dev_priv->display.get_initial_plane_config =
14779 i9xx_get_initial_plane_config;
14780 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14781 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14782 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14783 } else if (IS_VALLEYVIEW(dev_priv)) {
14784 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14785 dev_priv->display.get_initial_plane_config =
14786 i9xx_get_initial_plane_config;
14787 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14788 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14789 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14790 } else if (IS_G4X(dev_priv)) {
14791 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14792 dev_priv->display.get_initial_plane_config =
14793 i9xx_get_initial_plane_config;
14794 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14795 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14796 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14797 } else if (IS_PINEVIEW(dev_priv)) {
14798 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14799 dev_priv->display.get_initial_plane_config =
14800 i9xx_get_initial_plane_config;
14801 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14802 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14803 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14804 } else if (!IS_GEN2(dev_priv)) {
14805 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14806 dev_priv->display.get_initial_plane_config =
14807 i9xx_get_initial_plane_config;
14808 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14809 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14810 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14811 } else {
14812 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14813 dev_priv->display.get_initial_plane_config =
14814 i9xx_get_initial_plane_config;
14815 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14816 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14817 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14818 }
14820 if (IS_GEN5(dev_priv)) {
14821 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14822 } else if (IS_GEN6(dev_priv)) {
14823 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14824 } else if (IS_IVYBRIDGE(dev_priv)) {
14825 /* FIXME: detect B0+ stepping and use auto training */
14826 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14827 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14828 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14829 }
14831 if (INTEL_GEN(dev_priv) >= 9)
14832 dev_priv->display.update_crtcs = skl_update_crtcs;
14833 else
14834 dev_priv->display.update_crtcs = intel_update_crtcs;
14835 }
14837 /*
14838 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14839 */
14840 static void quirk_ssc_force_disable(struct drm_device *dev)
14841 {
14842 struct drm_i915_private *dev_priv = to_i915(dev);
14843 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14844 DRM_INFO("applying lvds SSC disable quirk\n");
14845 }
14847 /*
14848 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14849 * brightness value
14850 */
14851 static void quirk_invert_brightness(struct drm_device *dev)
14852 {
14853 struct drm_i915_private *dev_priv = to_i915(dev);
14854 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14855 DRM_INFO("applying inverted panel brightness quirk\n");
14856 }
14858 /* Some VBT's incorrectly indicate no backlight is present */
14859 static void quirk_backlight_present(struct drm_device *dev)
14860 {
14861 struct drm_i915_private *dev_priv = to_i915(dev);
14862 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14863 DRM_INFO("applying backlight present quirk\n");
14864 }
14866 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14867 * which is 300 ms greater than eDP spec T12 min.
14868 */
14869 static void quirk_increase_t12_delay(struct drm_device *dev)
14870 {
14871 struct drm_i915_private *dev_priv = to_i915(dev);
14873 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14874 DRM_INFO("Applying T12 delay quirk\n");
14875 }
14877 /*
14878 * GeminiLake NUC HDMI outputs require additional off time
14879 * this allows the onboard retimer to correctly sync to signal
14880 */
14881 static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
14882 {
14883 struct drm_i915_private *dev_priv = to_i915(dev);
14885 dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
14886 DRM_INFO("Applying Increase DDI Disabled quirk\n");
14887 }
14889 struct intel_quirk {
14890 int device;
14891 int subsystem_vendor;
14892 int subsystem_device;
14893 void (*hook)(struct drm_device *dev);
14894 };
14896 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14897 struct intel_dmi_quirk {
14898 void (*hook)(struct drm_device *dev);
14899 const struct dmi_system_id (*dmi_id_list)[];
14900 };
14902 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14903 {
14904 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14905 return 1;
14906 }
14908 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14909 {
14910 .dmi_id_list = &(const struct dmi_system_id[]) {
14911 {
14912 .callback = intel_dmi_reverse_brightness,
14913 .ident = "NCR Corporation",
14914 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14915 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14916 },
14917 },
14918 { } /* terminating entry */
14919 },
14920 .hook = quirk_invert_brightness,
14921 },
14922 };
14924 static struct intel_quirk intel_quirks[] = {
14925 /* Lenovo U160 cannot use SSC on LVDS */
14926 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14928 /* Sony Vaio Y cannot use SSC on LVDS */
14929 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14931 /* Acer Aspire 5734Z must invert backlight brightness */
14932 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14934 /* Acer/eMachines G725 */
14935 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14937 /* Acer/eMachines e725 */
14938 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14940 /* Acer/Packard Bell NCL20 */
14941 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14943 /* Acer Aspire 4736Z */
14944 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14946 /* Acer Aspire 5336 */
14947 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14949 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14950 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14952 /* Acer C720 Chromebook (Core i3 4005U) */
14953 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14955 /* Apple Macbook 2,1 (Core 2 T7400) */
14956 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14958 /* Apple Macbook 4,1 */
14959 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14961 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14962 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14964 /* HP Chromebook 14 (Celeron 2955U) */
14965 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14967 /* Dell Chromebook 11 */
14968 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14970 /* Dell Chromebook 11 (2015 version) */
14971 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14973 /* Toshiba Satellite P50-C-18C */
14974 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14976 /* GeminiLake NUC */
14977 { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
14978 { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
14979 /* ASRock ITX*/
14980 { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
14981 { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
14982 };
14984 static void intel_init_quirks(struct drm_device *dev)
14985 {
14986 struct pci_dev *d = dev->pdev;
14987 int i;
14989 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14990 struct intel_quirk *q = &intel_quirks[i];
14992 if (d->device == q->device &&
14993 (d->subsystem_vendor == q->subsystem_vendor ||
14994 q->subsystem_vendor == PCI_ANY_ID) &&
14995 (d->subsystem_device == q->subsystem_device ||
14996 q->subsystem_device == PCI_ANY_ID))
14997 q->hook(dev);
14998 }
14999 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15000 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15001 intel_dmi_quirks[i].hook(dev);
15002 }
15003 }
15005 /* Disable the VGA plane that we never use */
15006 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15007 {
15008 struct pci_dev *pdev = dev_priv->drm.pdev;
15009 u8 sr1;
15010 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15012 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15013 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15014 outb(SR01, VGA_SR_INDEX);
15015 sr1 = inb(VGA_SR_DATA);
15016 outb(sr1 | 1<<5, VGA_SR_DATA);
15017 vga_put(pdev, VGA_RSRC_LEGACY_IO);
15018 udelay(300);
15020 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15021 POSTING_READ(vga_reg);
15022 }
15024 void intel_modeset_init_hw(struct drm_device *dev)
15025 {
15026 struct drm_i915_private *dev_priv = to_i915(dev);
15028 intel_update_cdclk(dev_priv);
15029 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15030 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15031 }
15033 /*
15034 * Calculate what we think the watermarks should be for the state we've read
15035 * out of the hardware and then immediately program those watermarks so that
15036 * we ensure the hardware settings match our internal state.
15037 *
15038 * We can calculate what we think WM's should be by creating a duplicate of the
15039 * current state (which was constructed during hardware readout) and running it
15040 * through the atomic check code to calculate new watermark values in the
15041 * state object.
15042 */
15043 static void sanitize_watermarks(struct drm_device *dev)
15044 {
15045 struct drm_i915_private *dev_priv = to_i915(dev);
15046 struct drm_atomic_state *state;
15047 struct intel_atomic_state *intel_state;
15048 struct drm_crtc *crtc;
15049 struct drm_crtc_state *cstate;
15050 struct drm_modeset_acquire_ctx ctx;
15051 int ret;
15052 int i;
15054 /* Only supported on platforms that use atomic watermark design */
15055 if (!dev_priv->display.optimize_watermarks)
15056 return;
15058 /*
15059 * We need to hold connection_mutex before calling duplicate_state so
15060 * that the connector loop is protected.
15061 */
15062 drm_modeset_acquire_init(&ctx, 0);
15063 retry:
15064 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15065 if (ret == -EDEADLK) {
15066 drm_modeset_backoff(&ctx);
15067 goto retry;
15068 } else if (WARN_ON(ret)) {
15069 goto fail;
15070 }
15072 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15073 if (WARN_ON(IS_ERR(state)))
15074 goto fail;
15076 intel_state = to_intel_atomic_state(state);
15078 /*
15079 * Hardware readout is the only time we don't want to calculate
15080 * intermediate watermarks (since we don't trust the current
15081 * watermarks).
15082 */
15083 if (!HAS_GMCH_DISPLAY(dev_priv))
15084 intel_state->skip_intermediate_wm = true;
15086 ret = intel_atomic_check(dev, state);
15087 if (ret) {
15088 /*
15089 * If we fail here, it means that the hardware appears to be
15090 * programmed in a way that shouldn't be possible, given our
15091 * understanding of watermark requirements. This might mean a
15092 * mistake in the hardware readout code or a mistake in the
15093 * watermark calculations for a given platform. Raise a WARN
15094 * so that this is noticeable.
15095 *
15096 * If this actually happens, we'll have to just leave the
15097 * BIOS-programmed watermarks untouched and hope for the best.
15098 */
15099 WARN(true, "Could not determine valid watermarks for inherited state\n");
15100 goto put_state;
15101 }
15103 /* Write calculated watermark values back */
15104 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15105 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15107 cs->wm.need_postvbl_update = true;
15108 dev_priv->display.optimize_watermarks(intel_state, cs);
15110 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15111 }
15113 put_state:
15114 drm_atomic_state_put(state);
15115 fail:
15116 drm_modeset_drop_locks(&ctx);
15117 drm_modeset_acquire_fini(&ctx);
15118 }
15120 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15121 {
15122 if (IS_GEN5(dev_priv)) {
15123 u32 fdi_pll_clk =
15124 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15126 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15127 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
15128 dev_priv->fdi_pll_freq = 270000;
15129 } else {
15130 return;
15131 }
15133 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15134 }
15136 int intel_modeset_init(struct drm_device *dev)
15137 {
15138 struct drm_i915_private *dev_priv = to_i915(dev);
15139 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15140 enum pipe pipe;
15141 struct intel_crtc *crtc;
15143 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15145 drm_mode_config_init(dev);
15147 dev->mode_config.min_width = 0;
15148 dev->mode_config.min_height = 0;
15150 dev->mode_config.preferred_depth = 24;
15151 dev->mode_config.prefer_shadow = 1;
15153 dev->mode_config.allow_fb_modifiers = true;
15155 dev->mode_config.funcs = &intel_mode_funcs;
15157 init_llist_head(&dev_priv->atomic_helper.free_list);
15158 INIT_WORK(&dev_priv->atomic_helper.free_work,
15159 intel_atomic_helper_free_state_worker);
15161 intel_init_quirks(dev);
15163 intel_init_pm(dev_priv);
15165 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15166 return 0;
15168 /*
15169 * There may be no VBT; and if the BIOS enabled SSC we can
15170 * just keep using it to avoid unnecessary flicker. Whereas if the
15171 * BIOS isn't using it, don't assume it will work even if the VBT
15172 * indicates as much.
15173 */
15174 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15175 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15176 DREF_SSC1_ENABLE);
15178 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15179 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15180 bios_lvds_use_ssc ? "en" : "dis",
15181 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15182 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15183 }
15184 }
15186 /* maximum framebuffer dimensions */
15187 if (IS_GEN2(dev_priv)) {
15188 dev->mode_config.max_width = 2048;
15189 dev->mode_config.max_height = 2048;
15190 } else if (IS_GEN3(dev_priv)) {
15191 dev->mode_config.max_width = 4096;
15192 dev->mode_config.max_height = 4096;
15193 } else {
15194 dev->mode_config.max_width = 8192;
15195 dev->mode_config.max_height = 8192;
15196 }
15198 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15199 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15200 dev->mode_config.cursor_height = 1023;
15201 } else if (IS_GEN2(dev_priv)) {
15202 dev->mode_config.cursor_width = 64;
15203 dev->mode_config.cursor_height = 64;
15204 } else {
15205 dev->mode_config.cursor_width = 256;
15206 dev->mode_config.cursor_height = 256;
15207 }
15209 dev->mode_config.fb_base = ggtt->gmadr.start;
15211 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15212 INTEL_INFO(dev_priv)->num_pipes,
15213 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15215 for_each_pipe(dev_priv, pipe) {
15216 int ret;
15218 ret = intel_crtc_init(dev_priv, pipe);
15219 if (ret) {
15220 drm_mode_config_cleanup(dev);
15221 return ret;
15222 }
15223 }
15225 intel_shared_dpll_init(dev);
15226 intel_update_fdi_pll_freq(dev_priv);
15228 intel_update_czclk(dev_priv);
15229 intel_modeset_init_hw(dev);
15231 if (dev_priv->max_cdclk_freq == 0)
15232 intel_update_max_cdclk(dev_priv);
15234 /* Just disable it once at startup */
15235 i915_disable_vga(dev_priv);
15236 intel_setup_outputs(dev_priv);
15238 drm_modeset_lock_all(dev);
15239 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15240 drm_modeset_unlock_all(dev);
15242 for_each_intel_crtc(dev, crtc) {
15243 struct intel_initial_plane_config plane_config = {};
15245 if (!crtc->active)
15246 continue;
15248 /*
15249 * Note that reserving the BIOS fb up front prevents us
15250 * from stuffing other stolen allocations like the ring
15251 * on top. This prevents some ugliness at boot time, and
15252 * can even allow for smooth boot transitions if the BIOS
15253 * fb is large enough for the active pipe configuration.
15254 */
15255 dev_priv->display.get_initial_plane_config(crtc,
15256 &plane_config);
15258 /*
15259 * If the fb is shared between multiple heads, we'll
15260 * just get the first one.
15261 */
15262 intel_find_initial_plane_obj(crtc, &plane_config);
15263 }
15265 /*
15266 * Make sure hardware watermarks really match the state we read out.
15267 * Note that we need to do this after reconstructing the BIOS fb's
15268 * since the watermark calculation done here will use pstate->fb.
15269 */
15270 if (!HAS_GMCH_DISPLAY(dev_priv))
15271 sanitize_watermarks(dev);
15273 return 0;
15274 }
15276 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15277 {
15278 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15279 /* 640x480@60Hz, ~25175 kHz */
15280 struct dpll clock = {
15281 .m1 = 18,
15282 .m2 = 7,
15283 .p1 = 13,
15284 .p2 = 4,
15285 .n = 2,
15286 };
15287 u32 dpll, fp;
15288 int i;
15290 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15292 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15293 pipe_name(pipe), clock.vco, clock.dot);
15295 fp = i9xx_dpll_compute_fp(&clock);
15296 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15297 DPLL_VGA_MODE_DIS |
15298 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15299 PLL_P2_DIVIDE_BY_4 |
15300 PLL_REF_INPUT_DREFCLK |
15301 DPLL_VCO_ENABLE;
15303 I915_WRITE(FP0(pipe), fp);
15304 I915_WRITE(FP1(pipe), fp);
15306 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15307 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15308 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15309 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15310 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15311 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15312 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15314 /*
15315 * Apparently we need to have VGA mode enabled prior to changing
15316 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15317 * dividers, even though the register value does change.
15318 */
15319 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15320 I915_WRITE(DPLL(pipe), dpll);
15322 /* Wait for the clocks to stabilize. */
15323 POSTING_READ(DPLL(pipe));
15324 udelay(150);
15326 /* The pixel multiplier can only be updated once the
15327 * DPLL is enabled and the clocks are stable.
15328 *
15329 * So write it again.
15330 */
15331 I915_WRITE(DPLL(pipe), dpll);
15333 /* We do this three times for luck */
15334 for (i = 0; i < 3 ; i++) {
15335 I915_WRITE(DPLL(pipe), dpll);
15336 POSTING_READ(DPLL(pipe));
15337 udelay(150); /* wait for warmup */
15338 }
15340 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15341 POSTING_READ(PIPECONF(pipe));
15343 intel_wait_for_pipe_scanline_moving(crtc);
15344 }
15346 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15347 {
15348 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15350 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15351 pipe_name(pipe));
15353 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15354 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15355 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15356 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15357 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15359 I915_WRITE(PIPECONF(pipe), 0);
15360 POSTING_READ(PIPECONF(pipe));
15362 intel_wait_for_pipe_scanline_stopped(crtc);
15364 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15365 POSTING_READ(DPLL(pipe));
15366 }
15368 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
15369 struct intel_plane *plane)
15370 {
15371 enum pipe pipe;
15373 if (!plane->get_hw_state(plane, &pipe))
15374 return true;
15376 return pipe == crtc->pipe;
15377 }
15379 static void
15380 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15381 {
15382 struct intel_crtc *crtc;
15384 if (INTEL_GEN(dev_priv) >= 4)
15385 return;
15387 for_each_intel_crtc(&dev_priv->drm, crtc) {
15388 struct intel_plane *plane =
15389 to_intel_plane(crtc->base.primary);
15391 if (intel_plane_mapping_ok(crtc, plane))
15392 continue;
15394 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15395 plane->base.name);
15396 intel_plane_disable_noatomic(crtc, plane);
15397 }
15398 }
15400 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15401 {
15402 struct drm_device *dev = crtc->base.dev;
15403 struct intel_encoder *encoder;
15405 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15406 return true;
15408 return false;
15409 }
15411 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15412 {
15413 struct drm_device *dev = encoder->base.dev;
15414 struct intel_connector *connector;
15416 for_each_connector_on_encoder(dev, &encoder->base, connector)
15417 return connector;
15419 return NULL;
15420 }
15422 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15423 enum pipe pch_transcoder)
15424 {
15425 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15426 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15427 }
15429 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15430 struct drm_modeset_acquire_ctx *ctx)
15431 {
15432 struct drm_device *dev = crtc->base.dev;
15433 struct drm_i915_private *dev_priv = to_i915(dev);
15434 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15436 /* Clear any frame start delays used for debugging left by the BIOS */
15437 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15438 i915_reg_t reg = PIPECONF(cpu_transcoder);
15440 I915_WRITE(reg,
15441 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15442 }
15444 /* restore vblank interrupts to correct state */
15445 drm_crtc_vblank_reset(&crtc->base);
15446 if (crtc->active) {
15447 struct intel_plane *plane;
15449 drm_crtc_vblank_on(&crtc->base);
15451 /* Disable everything but the primary plane */
15452 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15453 const struct intel_plane_state *plane_state =
15454 to_intel_plane_state(plane->base.state);
15456 if (plane_state->base.visible &&
15457 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15458 intel_plane_disable_noatomic(crtc, plane);
15459 }
15460 }
15462 /* Adjust the state of the output pipe according to whether we
15463 * have active connectors/encoders. */
15464 if (crtc->active && !intel_crtc_has_encoders(crtc))
15465 intel_crtc_disable_noatomic(&crtc->base, ctx);
15467 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15468 /*
15469 * We start out with underrun reporting disabled to avoid races.
15470 * For correct bookkeeping mark this on active crtcs.
15471 *
15472 * Also on gmch platforms we dont have any hardware bits to
15473 * disable the underrun reporting. Which means we need to start
15474 * out with underrun reporting disabled also on inactive pipes,
15475 * since otherwise we'll complain about the garbage we read when
15476 * e.g. coming up after runtime pm.
15477 *
15478 * No protection against concurrent access is required - at
15479 * worst a fifo underrun happens which also sets this to false.
15480 */
15481 crtc->cpu_fifo_underrun_disabled = true;
15482 /*
15483 * We track the PCH trancoder underrun reporting state
15484 * within the crtc. With crtc for pipe A housing the underrun
15485 * reporting state for PCH transcoder A, crtc for pipe B housing
15486 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15487 * and marking underrun reporting as disabled for the non-existing
15488 * PCH transcoders B and C would prevent enabling the south
15489 * error interrupt (see cpt_can_enable_serr_int()).
15490 */
15491 if (has_pch_trancoder(dev_priv, crtc->pipe))
15492 crtc->pch_fifo_underrun_disabled = true;
15493 }
15494 }
15496 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15497 {
15498 struct intel_connector *connector;
15500 /* We need to check both for a crtc link (meaning that the
15501 * encoder is active and trying to read from a pipe) and the
15502 * pipe itself being active. */
15503 bool has_active_crtc = encoder->base.crtc &&
15504 to_intel_crtc(encoder->base.crtc)->active;
15506 connector = intel_encoder_find_connector(encoder);
15507 if (connector && !has_active_crtc) {
15508 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15509 encoder->base.base.id,
15510 encoder->base.name);
15512 /* Connector is active, but has no active pipe. This is
15513 * fallout from our resume register restoring. Disable
15514 * the encoder manually again. */
15515 if (encoder->base.crtc) {
15516 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15518 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15519 encoder->base.base.id,
15520 encoder->base.name);
15521 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15522 if (encoder->post_disable)
15523 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15524 }
15525 encoder->base.crtc = NULL;
15527 /* Inconsistent output/port/pipe state happens presumably due to
15528 * a bug in one of the get_hw_state functions. Or someplace else
15529 * in our code, like the register restore mess on resume. Clamp
15530 * things to off as a safer default. */
15532 connector->base.dpms = DRM_MODE_DPMS_OFF;
15533 connector->base.encoder = NULL;
15534 }
15536 /* notify opregion of the sanitized encoder state */
15537 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15538 }
15540 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15541 {
15542 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15544 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15545 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15546 i915_disable_vga(dev_priv);
15547 }
15548 }
15550 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15551 {
15552 /* This function can be called both from intel_modeset_setup_hw_state or
15553 * at a very early point in our resume sequence, where the power well
15554 * structures are not yet restored. Since this function is at a very
15555 * paranoid "someone might have enabled VGA while we were not looking"
15556 * level, just check if the power well is enabled instead of trying to
15557 * follow the "don't touch the power well if we don't need it" policy
15558 * the rest of the driver uses. */
15559 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15560 return;
15562 i915_redisable_vga_power_on(dev_priv);
15564 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15565 }
15567 /* FIXME read out full plane state for all planes */
15568 static void readout_plane_state(struct intel_crtc *crtc)
15569 {
15570 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15571 struct intel_crtc_state *crtc_state =
15572 to_intel_crtc_state(crtc->base.state);
15573 struct intel_plane *plane;
15575 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15576 struct intel_plane_state *plane_state =
15577 to_intel_plane_state(plane->base.state);
15578 enum pipe pipe;
15579 bool visible;
15581 visible = plane->get_hw_state(plane, &pipe);
15583 intel_set_plane_visible(crtc_state, plane_state, visible);
15584 }
15585 }
15587 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15588 {
15589 struct drm_i915_private *dev_priv = to_i915(dev);
15590 enum pipe pipe;
15591 struct intel_crtc *crtc;
15592 struct intel_encoder *encoder;
15593 struct intel_connector *connector;
15594 struct drm_connector_list_iter conn_iter;
15595 int i;
15597 dev_priv->active_crtcs = 0;
15599 for_each_intel_crtc(dev, crtc) {
15600 struct intel_crtc_state *crtc_state =
15601 to_intel_crtc_state(crtc->base.state);
15603 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15604 memset(crtc_state, 0, sizeof(*crtc_state));
15605 crtc_state->base.crtc = &crtc->base;
15607 crtc_state->base.active = crtc_state->base.enable =
15608 dev_priv->display.get_pipe_config(crtc, crtc_state);
15610 crtc->base.enabled = crtc_state->base.enable;
15611 crtc->active = crtc_state->base.active;
15613 if (crtc_state->base.active)
15614 dev_priv->active_crtcs |= 1 << crtc->pipe;
15616 readout_plane_state(crtc);
15618 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15619 crtc->base.base.id, crtc->base.name,
15620 enableddisabled(crtc_state->base.active));
15621 }
15623 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15624 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15626 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15627 &pll->state.hw_state);
15628 pll->state.crtc_mask = 0;
15629 for_each_intel_crtc(dev, crtc) {
15630 struct intel_crtc_state *crtc_state =
15631 to_intel_crtc_state(crtc->base.state);
15633 if (crtc_state->base.active &&
15634 crtc_state->shared_dpll == pll)
15635 pll->state.crtc_mask |= 1 << crtc->pipe;
15636 }
15637 pll->active_mask = pll->state.crtc_mask;
15639 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15640 pll->info->name, pll->state.crtc_mask, pll->on);
15641 }
15643 for_each_intel_encoder(dev, encoder) {
15644 pipe = 0;
15646 if (encoder->get_hw_state(encoder, &pipe)) {
15647 struct intel_crtc_state *crtc_state;
15649 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15650 crtc_state = to_intel_crtc_state(crtc->base.state);
15652 encoder->base.crtc = &crtc->base;
15653 encoder->get_config(encoder, crtc_state);
15654 } else {
15655 encoder->base.crtc = NULL;
15656 }
15658 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15659 encoder->base.base.id, encoder->base.name,
15660 enableddisabled(encoder->base.crtc),
15661 pipe_name(pipe));
15662 }
15664 drm_connector_list_iter_begin(dev, &conn_iter);
15665 for_each_intel_connector_iter(connector, &conn_iter) {
15666 if (connector->get_hw_state(connector)) {
15667 connector->base.dpms = DRM_MODE_DPMS_ON;
15669 encoder = connector->encoder;
15670 connector->base.encoder = &encoder->base;
15672 if (encoder->base.crtc &&
15673 encoder->base.crtc->state->active) {
15674 /*
15675 * This has to be done during hardware readout
15676 * because anything calling .crtc_disable may
15677 * rely on the connector_mask being accurate.
15678 */
15679 encoder->base.crtc->state->connector_mask |=
15680 drm_connector_mask(&connector->base);
15681 encoder->base.crtc->state->encoder_mask |=
15682 drm_encoder_mask(&encoder->base);
15683 }
15685 } else {
15686 connector->base.dpms = DRM_MODE_DPMS_OFF;
15687 connector->base.encoder = NULL;
15688 }
15689 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15690 connector->base.base.id, connector->base.name,
15691 enableddisabled(connector->base.encoder));
15692 }
15693 drm_connector_list_iter_end(&conn_iter);
15695 for_each_intel_crtc(dev, crtc) {
15696 struct intel_crtc_state *crtc_state =
15697 to_intel_crtc_state(crtc->base.state);
15698 int min_cdclk = 0;
15700 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15701 if (crtc_state->base.active) {
15702 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15703 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15704 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15705 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15706 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15708 /*
15709 * The initial mode needs to be set in order to keep
15710 * the atomic core happy. It wants a valid mode if the
15711 * crtc's enabled, so we do the above call.
15712 *
15713 * But we don't set all the derived state fully, hence
15714 * set a flag to indicate that a full recalculation is
15715 * needed on the next commit.
15716 */
15717 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15719 intel_crtc_compute_pixel_rate(crtc_state);
15721 if (dev_priv->display.modeset_calc_cdclk) {
15722 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15723 if (WARN_ON(min_cdclk < 0))
15724 min_cdclk = 0;
15725 }
15727 drm_calc_timestamping_constants(&crtc->base,
15728 &crtc_state->base.adjusted_mode);
15729 update_scanline_offset(crtc);
15730 }
15732 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15733 dev_priv->min_voltage_level[crtc->pipe] =
15734 crtc_state->min_voltage_level;
15736 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15737 }
15738 }
15740 static void
15741 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15742 {
15743 struct intel_encoder *encoder;
15745 for_each_intel_encoder(&dev_priv->drm, encoder) {
15746 u64 get_domains;
15747 enum intel_display_power_domain domain;
15748 struct intel_crtc_state *crtc_state;
15750 if (!encoder->get_power_domains)
15751 continue;
15753 /*
15754 * MST-primary and inactive encoders don't have a crtc state
15755 * and neither of these require any power domain references.
15756 */
15757 if (!encoder->base.crtc)
15758 continue;
15760 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
15761 get_domains = encoder->get_power_domains(encoder, crtc_state);
15762 for_each_power_domain(domain, get_domains)
15763 intel_display_power_get(dev_priv, domain);
15764 }
15765 }
15767 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15768 {
15769 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15770 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15771 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15772 DARBF_GATING_DIS);
15774 if (IS_HASWELL(dev_priv)) {
15775 /*
15776 * WaRsPkgCStateDisplayPMReq:hsw
15777 * System hang if this isn't done before disabling all planes!
15778 */
15779 I915_WRITE(CHICKEN_PAR1_1,
15780 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15781 }
15782 }
15784 /* Scan out the current hw modeset state,
15785 * and sanitizes it to the current state
15786 */
15787 static void
15788 intel_modeset_setup_hw_state(struct drm_device *dev,
15789 struct drm_modeset_acquire_ctx *ctx)
15790 {
15791 struct drm_i915_private *dev_priv = to_i915(dev);
15792 enum pipe pipe;
15793 struct intel_crtc *crtc;
15794 struct intel_encoder *encoder;
15795 int i;
15797 intel_early_display_was(dev_priv);
15798 intel_modeset_readout_hw_state(dev);
15800 /* HW state is read out, now we need to sanitize this mess. */
15801 get_encoder_power_domains(dev_priv);
15803 intel_sanitize_plane_mapping(dev_priv);
15805 for_each_intel_encoder(dev, encoder) {
15806 intel_sanitize_encoder(encoder);
15807 }
15809 for_each_pipe(dev_priv, pipe) {
15810 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15812 intel_sanitize_crtc(crtc, ctx);
15813 intel_dump_pipe_config(crtc, crtc->config,
15814 "[setup_hw_state]");
15815 }
15817 intel_modeset_update_connector_atomic_state(dev);
15819 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15820 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15822 if (!pll->on || pll->active_mask)
15823 continue;
15825 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
15826 pll->info->name);
15828 pll->info->funcs->disable(dev_priv, pll);
15829 pll->on = false;
15830 }
15832 if (IS_G4X(dev_priv)) {
15833 g4x_wm_get_hw_state(dev);
15834 g4x_wm_sanitize(dev_priv);
15835 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15836 vlv_wm_get_hw_state(dev);
15837 vlv_wm_sanitize(dev_priv);
15838 } else if (INTEL_GEN(dev_priv) >= 9) {
15839 skl_wm_get_hw_state(dev);
15840 } else if (HAS_PCH_SPLIT(dev_priv)) {
15841 ilk_wm_get_hw_state(dev);
15842 }
15844 for_each_intel_crtc(dev, crtc) {
15845 u64 put_domains;
15847 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15848 if (WARN_ON(put_domains))
15849 modeset_put_power_domains(dev_priv, put_domains);
15850 }
15851 intel_display_set_init_power(dev_priv, false);
15853 intel_power_domains_verify_state(dev_priv);
15855 intel_fbc_init_pipe_state(dev_priv);
15856 }
15858 void intel_display_resume(struct drm_device *dev)
15859 {
15860 struct drm_i915_private *dev_priv = to_i915(dev);
15861 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15862 struct drm_modeset_acquire_ctx ctx;
15863 int ret;
15865 dev_priv->modeset_restore_state = NULL;
15866 if (state)
15867 state->acquire_ctx = &ctx;
15869 drm_modeset_acquire_init(&ctx, 0);
15871 while (1) {
15872 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15873 if (ret != -EDEADLK)
15874 break;
15876 drm_modeset_backoff(&ctx);
15877 }
15879 if (!ret)
15880 ret = __intel_display_resume(dev, state, &ctx);
15882 intel_enable_ipc(dev_priv);
15883 drm_modeset_drop_locks(&ctx);
15884 drm_modeset_acquire_fini(&ctx);
15886 if (ret)
15887 DRM_ERROR("Restoring old state failed with %i\n", ret);
15888 if (state)
15889 drm_atomic_state_put(state);
15890 }
15892 int intel_connector_register(struct drm_connector *connector)
15893 {
15894 struct intel_connector *intel_connector = to_intel_connector(connector);
15895 int ret;
15897 ret = intel_backlight_device_register(intel_connector);
15898 if (ret)
15899 goto err;
15901 return 0;
15903 err:
15904 return ret;
15905 }
15907 void intel_connector_unregister(struct drm_connector *connector)
15908 {
15909 struct intel_connector *intel_connector = to_intel_connector(connector);
15911 intel_backlight_device_unregister(intel_connector);
15912 intel_panel_destroy_backlight(connector);
15913 }
15915 static void intel_hpd_poll_fini(struct drm_device *dev)
15916 {
15917 struct intel_connector *connector;
15918 struct drm_connector_list_iter conn_iter;
15920 /* Kill all the work that may have been queued by hpd. */
15921 drm_connector_list_iter_begin(dev, &conn_iter);
15922 for_each_intel_connector_iter(connector, &conn_iter) {
15923 if (connector->modeset_retry_work.func)
15924 cancel_work_sync(&connector->modeset_retry_work);
15925 if (connector->hdcp_shim) {
15926 cancel_delayed_work_sync(&connector->hdcp_check_work);
15927 cancel_work_sync(&connector->hdcp_prop_work);
15928 }
15929 }
15930 drm_connector_list_iter_end(&conn_iter);
15931 }
15933 void intel_modeset_cleanup(struct drm_device *dev)
15934 {
15935 struct drm_i915_private *dev_priv = to_i915(dev);
15937 flush_workqueue(dev_priv->modeset_wq);
15939 flush_work(&dev_priv->atomic_helper.free_work);
15940 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15942 intel_disable_gt_powersave(dev_priv);
15944 /*
15945 * Interrupts and polling as the first thing to avoid creating havoc.
15946 * Too much stuff here (turning of connectors, ...) would
15947 * experience fancy races otherwise.
15948 */
15949 intel_irq_uninstall(dev_priv);
15951 /*
15952 * Due to the hpd irq storm handling the hotplug work can re-arm the
15953 * poll handlers. Hence disable polling after hpd handling is shut down.
15954 */
15955 intel_hpd_poll_fini(dev);
15957 /* poll work can call into fbdev, hence clean that up afterwards */
15958 intel_fbdev_fini(dev_priv);
15960 intel_unregister_dsm_handler();
15962 intel_fbc_global_disable(dev_priv);
15964 /* flush any delayed tasks or pending work */
15965 flush_scheduled_work();
15967 drm_mode_config_cleanup(dev);
15969 intel_cleanup_overlay(dev_priv);
15971 intel_cleanup_gt_powersave(dev_priv);
15973 intel_teardown_gmbus(dev_priv);
15975 destroy_workqueue(dev_priv->modeset_wq);
15976 }
15978 void intel_connector_attach_encoder(struct intel_connector *connector,
15979 struct intel_encoder *encoder)
15980 {
15981 connector->encoder = encoder;
15982 drm_connector_attach_encoder(&connector->base, &encoder->base);
15983 }
15985 /*
15986 * set vga decode state - true == enable VGA decode
15987 */
15988 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15989 {
15990 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15991 u16 gmch_ctrl;
15993 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15994 DRM_ERROR("failed to read control word\n");
15995 return -EIO;
15996 }
15998 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15999 return 0;
16001 if (state)
16002 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16003 else
16004 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16006 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16007 DRM_ERROR("failed to write control word\n");
16008 return -EIO;
16009 }
16011 return 0;
16012 }
16014 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16016 struct intel_display_error_state {
16018 u32 power_well_driver;
16020 int num_transcoders;
16022 struct intel_cursor_error_state {
16023 u32 control;
16024 u32 position;
16025 u32 base;
16026 u32 size;
16027 } cursor[I915_MAX_PIPES];
16029 struct intel_pipe_error_state {
16030 bool power_domain_on;
16031 u32 source;
16032 u32 stat;
16033 } pipe[I915_MAX_PIPES];
16035 struct intel_plane_error_state {
16036 u32 control;
16037 u32 stride;
16038 u32 size;
16039 u32 pos;
16040 u32 addr;
16041 u32 surface;
16042 u32 tile_offset;
16043 } plane[I915_MAX_PIPES];
16045 struct intel_transcoder_error_state {
16046 bool power_domain_on;
16047 enum transcoder cpu_transcoder;
16049 u32 conf;
16051 u32 htotal;
16052 u32 hblank;
16053 u32 hsync;
16054 u32 vtotal;
16055 u32 vblank;
16056 u32 vsync;
16057 } transcoder[4];
16058 };
16060 struct intel_display_error_state *
16061 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16062 {
16063 struct intel_display_error_state *error;
16064 int transcoders[] = {
16065 TRANSCODER_A,
16066 TRANSCODER_B,
16067 TRANSCODER_C,
16068 TRANSCODER_EDP,
16069 };
16070 int i;
16072 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16073 return NULL;
16075 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16076 if (error == NULL)
16077 return NULL;
16079 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16080 error->power_well_driver =
16081 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
16083 for_each_pipe(dev_priv, i) {
16084 error->pipe[i].power_domain_on =
16085 __intel_display_power_is_enabled(dev_priv,
16086 POWER_DOMAIN_PIPE(i));
16087 if (!error->pipe[i].power_domain_on)
16088 continue;
16090 error->cursor[i].control = I915_READ(CURCNTR(i));
16091 error->cursor[i].position = I915_READ(CURPOS(i));
16092 error->cursor[i].base = I915_READ(CURBASE(i));
16094 error->plane[i].control = I915_READ(DSPCNTR(i));
16095 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16096 if (INTEL_GEN(dev_priv) <= 3) {
16097 error->plane[i].size = I915_READ(DSPSIZE(i));
16098 error->plane[i].pos = I915_READ(DSPPOS(i));
16099 }
16100 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16101 error->plane[i].addr = I915_READ(DSPADDR(i));
16102 if (INTEL_GEN(dev_priv) >= 4) {
16103 error->plane[i].surface = I915_READ(DSPSURF(i));
16104 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16105 }
16107 error->pipe[i].source = I915_READ(PIPESRC(i));
16109 if (HAS_GMCH_DISPLAY(dev_priv))
16110 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16111 }
16113 /* Note: this does not include DSI transcoders. */
16114 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16115 if (HAS_DDI(dev_priv))
16116 error->num_transcoders++; /* Account for eDP. */
16118 for (i = 0; i < error->num_transcoders; i++) {
16119 enum transcoder cpu_transcoder = transcoders[i];
16121 error->transcoder[i].power_domain_on =
16122 __intel_display_power_is_enabled(dev_priv,
16123 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16124 if (!error->transcoder[i].power_domain_on)
16125 continue;
16127 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16129 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16130 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16131 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16132 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16133 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16134 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16135 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16136 }
16138 return error;
16139 }
16141 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16143 void
16144 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16145 struct intel_display_error_state *error)
16146 {
16147 struct drm_i915_private *dev_priv = m->i915;
16148 int i;
16150 if (!error)
16151 return;
16153 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16154 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16155 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16156 error->power_well_driver);
16157 for_each_pipe(dev_priv, i) {
16158 err_printf(m, "Pipe [%d]:\n", i);
16159 err_printf(m, " Power: %s\n",
16160 onoff(error->pipe[i].power_domain_on));
16161 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16162 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16164 err_printf(m, "Plane [%d]:\n", i);
16165 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16166 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16167 if (INTEL_GEN(dev_priv) <= 3) {
16168 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16169 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16170 }
16171 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16172 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16173 if (INTEL_GEN(dev_priv) >= 4) {
16174 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16175 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16176 }
16178 err_printf(m, "Cursor [%d]:\n", i);
16179 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16180 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16181 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16182 }
16184 for (i = 0; i < error->num_transcoders; i++) {
16185 err_printf(m, "CPU transcoder: %s\n",
16186 transcoder_name(error->transcoder[i].cpu_transcoder));
16187 err_printf(m, " Power: %s\n",
16188 onoff(error->transcoder[i].power_domain_on));
16189 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16190 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16191 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16192 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16193 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16194 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16195 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16196 }
16197 }
16199 #endif