drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/if_bridge.h>
  31 #include <net/dsa.h>
  32
  33 #include "b53_regs.h"
  34 #include "b53_priv.h"
  35
  36 struct b53_mib_desc {
  37         u8 size;
  38         u8 offset;
  39         const char *name;
  40 };
  41
  42 /* BCM5365 MIB counters */
  43 static const struct b53_mib_desc b53_mibs_65[] = {
  44         { 8, 0x00, "TxOctets" },
  45         { 4, 0x08, "TxDropPkts" },
  46         { 4, 0x10, "TxBroadcastPkts" },
  47         { 4, 0x14, "TxMulticastPkts" },
  48         { 4, 0x18, "TxUnicastPkts" },
  49         { 4, 0x1c, "TxCollisions" },
  50         { 4, 0x20, "TxSingleCollision" },
  51         { 4, 0x24, "TxMultipleCollision" },
  52         { 4, 0x28, "TxDeferredTransmit" },
  53         { 4, 0x2c, "TxLateCollision" },
  54         { 4, 0x30, "TxExcessiveCollision" },
  55         { 4, 0x38, "TxPausePkts" },
  56         { 8, 0x44, "RxOctets" },
  57         { 4, 0x4c, "RxUndersizePkts" },
  58         { 4, 0x50, "RxPausePkts" },
  59         { 4, 0x54, "Pkts64Octets" },
  60         { 4, 0x58, "Pkts65to127Octets" },
  61         { 4, 0x5c, "Pkts128to255Octets" },
  62         { 4, 0x60, "Pkts256to511Octets" },
  63         { 4, 0x64, "Pkts512to1023Octets" },
  64         { 4, 0x68, "Pkts1024to1522Octets" },
  65         { 4, 0x6c, "RxOversizePkts" },
  66         { 4, 0x70, "RxJabbers" },
  67         { 4, 0x74, "RxAlignmentErrors" },
  68         { 4, 0x78, "RxFCSErrors" },
  69         { 8, 0x7c, "RxGoodOctets" },
  70         { 4, 0x84, "RxDropPkts" },
  71         { 4, 0x88, "RxUnicastPkts" },
  72         { 4, 0x8c, "RxMulticastPkts" },
  73         { 4, 0x90, "RxBroadcastPkts" },
  74         { 4, 0x94, "RxSAChanges" },
  75         { 4, 0x98, "RxFragments" },
  76 };
  77
  78 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  79
  80 /* BCM63xx MIB counters */
  81 static const struct b53_mib_desc b53_mibs_63xx[] = {
  82         { 8, 0x00, "TxOctets" },
  83         { 4, 0x08, "TxDropPkts" },
  84         { 4, 0x0c, "TxQoSPkts" },
  85         { 4, 0x10, "TxBroadcastPkts" },
  86         { 4, 0x14, "TxMulticastPkts" },
  87         { 4, 0x18, "TxUnicastPkts" },
  88         { 4, 0x1c, "TxCollisions" },
  89         { 4, 0x20, "TxSingleCollision" },
  90         { 4, 0x24, "TxMultipleCollision" },
  91         { 4, 0x28, "TxDeferredTransmit" },
  92         { 4, 0x2c, "TxLateCollision" },
  93         { 4, 0x30, "TxExcessiveCollision" },
  94         { 4, 0x38, "TxPausePkts" },
  95         { 8, 0x3c, "TxQoSOctets" },
  96         { 8, 0x44, "RxOctets" },
  97         { 4, 0x4c, "RxUndersizePkts" },
  98         { 4, 0x50, "RxPausePkts" },
  99         { 4, 0x54, "Pkts64Octets" },
 100         { 4, 0x58, "Pkts65to127Octets" },
 101         { 4, 0x5c, "Pkts128to255Octets" },
 102         { 4, 0x60, "Pkts256to511Octets" },
 103         { 4, 0x64, "Pkts512to1023Octets" },
 104         { 4, 0x68, "Pkts1024to1522Octets" },
 105         { 4, 0x6c, "RxOversizePkts" },
 106         { 4, 0x70, "RxJabbers" },
 107         { 4, 0x74, "RxAlignmentErrors" },
 108         { 4, 0x78, "RxFCSErrors" },
 109         { 8, 0x7c, "RxGoodOctets" },
 110         { 4, 0x84, "RxDropPkts" },
 111         { 4, 0x88, "RxUnicastPkts" },
 112         { 4, 0x8c, "RxMulticastPkts" },
 113         { 4, 0x90, "RxBroadcastPkts" },
 114         { 4, 0x94, "RxSAChanges" },
 115         { 4, 0x98, "RxFragments" },
 116         { 4, 0xa0, "RxSymbolErrors" },
 117         { 4, 0xa4, "RxQoSPkts" },
 118         { 8, 0xa8, "RxQoSOctets" },
 119         { 4, 0xb0, "Pkts1523to2047Octets" },
 120         { 4, 0xb4, "Pkts2048to4095Octets" },
 121         { 4, 0xb8, "Pkts4096to8191Octets" },
 122         { 4, 0xbc, "Pkts8192to9728Octets" },
 123         { 4, 0xc0, "RxDiscarded" },
 124 };
 125
 126 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 127
 128 /* MIB counters */
 129 static const struct b53_mib_desc b53_mibs[] = {
 130         { 8, 0x00, "TxOctets" },
 131         { 4, 0x08, "TxDropPkts" },
 132         { 4, 0x10, "TxBroadcastPkts" },
 133         { 4, 0x14, "TxMulticastPkts" },
 134         { 4, 0x18, "TxUnicastPkts" },
 135         { 4, 0x1c, "TxCollisions" },
 136         { 4, 0x20, "TxSingleCollision" },
 137         { 4, 0x24, "TxMultipleCollision" },
 138         { 4, 0x28, "TxDeferredTransmit" },
 139         { 4, 0x2c, "TxLateCollision" },
 140         { 4, 0x30, "TxExcessiveCollision" },
 141         { 4, 0x38, "TxPausePkts" },
 142         { 8, 0x50, "RxOctets" },
 143         { 4, 0x58, "RxUndersizePkts" },
 144         { 4, 0x5c, "RxPausePkts" },
 145         { 4, 0x60, "Pkts64Octets" },
 146         { 4, 0x64, "Pkts65to127Octets" },
 147         { 4, 0x68, "Pkts128to255Octets" },
 148         { 4, 0x6c, "Pkts256to511Octets" },
 149         { 4, 0x70, "Pkts512to1023Octets" },
 150         { 4, 0x74, "Pkts1024to1522Octets" },
 151         { 4, 0x78, "RxOversizePkts" },
 152         { 4, 0x7c, "RxJabbers" },
 153         { 4, 0x80, "RxAlignmentErrors" },
 154         { 4, 0x84, "RxFCSErrors" },
 155         { 8, 0x88, "RxGoodOctets" },
 156         { 4, 0x90, "RxDropPkts" },
 157         { 4, 0x94, "RxUnicastPkts" },
 158         { 4, 0x98, "RxMulticastPkts" },
 159         { 4, 0x9c, "RxBroadcastPkts" },
 160         { 4, 0xa0, "RxSAChanges" },
 161         { 4, 0xa4, "RxFragments" },
 162         { 4, 0xa8, "RxJumboPkts" },
 163         { 4, 0xac, "RxSymbolErrors" },
 164         { 4, 0xc0, "RxDiscarded" },
 165 };
 166
 167 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 168
 169 static const struct b53_mib_desc b53_mibs_58xx[] = {
 170         { 8, 0x00, "TxOctets" },
 171         { 4, 0x08, "TxDropPkts" },
 172         { 4, 0x0c, "TxQPKTQ0" },
 173         { 4, 0x10, "TxBroadcastPkts" },
 174         { 4, 0x14, "TxMulticastPkts" },
 175         { 4, 0x18, "TxUnicastPKts" },
 176         { 4, 0x1c, "TxCollisions" },
 177         { 4, 0x20, "TxSingleCollision" },
 178         { 4, 0x24, "TxMultipleCollision" },
 179         { 4, 0x28, "TxDeferredCollision" },
 180         { 4, 0x2c, "TxLateCollision" },
 181         { 4, 0x30, "TxExcessiveCollision" },
 182         { 4, 0x34, "TxFrameInDisc" },
 183         { 4, 0x38, "TxPausePkts" },
 184         { 4, 0x3c, "TxQPKTQ1" },
 185         { 4, 0x40, "TxQPKTQ2" },
 186         { 4, 0x44, "TxQPKTQ3" },
 187         { 4, 0x48, "TxQPKTQ4" },
 188         { 4, 0x4c, "TxQPKTQ5" },
 189         { 8, 0x50, "RxOctets" },
 190         { 4, 0x58, "RxUndersizePkts" },
 191         { 4, 0x5c, "RxPausePkts" },
 192         { 4, 0x60, "RxPkts64Octets" },
 193         { 4, 0x64, "RxPkts65to127Octets" },
 194         { 4, 0x68, "RxPkts128to255Octets" },
 195         { 4, 0x6c, "RxPkts256to511Octets" },
 196         { 4, 0x70, "RxPkts512to1023Octets" },
 197         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 198         { 4, 0x78, "RxOversizePkts" },
 199         { 4, 0x7c, "RxJabbers" },
 200         { 4, 0x80, "RxAlignmentErrors" },
 201         { 4, 0x84, "RxFCSErrors" },
 202         { 8, 0x88, "RxGoodOctets" },
 203         { 4, 0x90, "RxDropPkts" },
 204         { 4, 0x94, "RxUnicastPkts" },
 205         { 4, 0x98, "RxMulticastPkts" },
 206         { 4, 0x9c, "RxBroadcastPkts" },
 207         { 4, 0xa0, "RxSAChanges" },
 208         { 4, 0xa4, "RxFragments" },
 209         { 4, 0xa8, "RxJumboPkt" },
 210         { 4, 0xac, "RxSymblErr" },
 211         { 4, 0xb0, "InRangeErrCount" },
 212         { 4, 0xb4, "OutRangeErrCount" },
 213         { 4, 0xb8, "EEELpiEvent" },
 214         { 4, 0xbc, "EEELpiDuration" },
 215         { 4, 0xc0, "RxDiscard" },
 216         { 4, 0xc8, "TxQPKTQ6" },
 217         { 4, 0xcc, "TxQPKTQ7" },
 218         { 4, 0xd0, "TxPkts64Octets" },
 219         { 4, 0xd4, "TxPkts65to127Octets" },
 220         { 4, 0xd8, "TxPkts128to255Octets" },
 221         { 4, 0xdc, "TxPkts256to511Ocets" },
 222         { 4, 0xe0, "TxPkts512to1023Ocets" },
 223         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 224 };
 225
 226 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 227
 228 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 229 {
 230         unsigned int i;
 231
 232         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 233
 234         for (i = 0; i < 10; i++) {
 235                 u8 vta;
 236
 237                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 238                 if (!(vta & VTA_START_CMD))
 239                         return 0;
 240
 241                 usleep_range(100, 200);
 242         }
 243
 244         return -EIO;
 245 }
 246
 247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 248                                struct b53_vlan *vlan)
 249 {
 250         if (is5325(dev)) {
 251                 u32 entry = 0;
 252
 253                 if (vlan->members) {
 254                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 255                                  VA_UNTAG_S_25) | vlan->members;
 256                         if (dev->core_rev >= 3)
 257                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 258                         else
 259                                 entry |= VA_VALID_25;
 260                 }
 261
 262                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 263                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 264                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 265         } else if (is5365(dev)) {
 266                 u16 entry = 0;
 267
 268                 if (vlan->members)
 269                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 270                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 271
 272                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 274                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 275         } else {
 276                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 277                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 278                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 279
 280                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 281         }
 282
 283         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 284                 vid, vlan->members, vlan->untag);
 285 }
 286
 287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 288                                struct b53_vlan *vlan)
 289 {
 290         if (is5325(dev)) {
 291                 u32 entry = 0;
 292
 293                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 294                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 295                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 296
 297                 if (dev->core_rev >= 3)
 298                         vlan->valid = !!(entry & VA_VALID_25_R4);
 299                 else
 300                         vlan->valid = !!(entry & VA_VALID_25);
 301                 vlan->members = entry & VA_MEMBER_MASK;
 302                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 303
 304         } else if (is5365(dev)) {
 305                 u16 entry = 0;
 306
 307                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 308                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 309                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 310
 311                 vlan->valid = !!(entry & VA_VALID_65);
 312                 vlan->members = entry & VA_MEMBER_MASK;
 313                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 314         } else {
 315                 u32 entry = 0;
 316
 317                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 318                 b53_do_vlan_op(dev, VTA_CMD_READ);
 319                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 320                 vlan->members = entry & VTE_MEMBERS;
 321                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 322                 vlan->valid = true;
 323         }
 324 }
 325
 326 static void b53_set_forwarding(struct b53_device *dev, int enable)
 327 {
 328         u8 mgmt;
 329
 330         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 331
 332         if (enable)
 333                 mgmt |= SM_SW_FWD_EN;
 334         else
 335                 mgmt &= ~SM_SW_FWD_EN;
 336
 337         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 338
 339         /* Include IMP port in dumb forwarding mode
 340          */
 341         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 342         mgmt |= B53_MII_DUMB_FWDG_EN;
 343         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 344 }
 345
 346 static void b53_enable_vlan(struct b53_device *dev, bool enable)
 347 {
 348         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 349
 350         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 351         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 352         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 353
 354         if (is5325(dev) || is5365(dev)) {
 355                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 356                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 357         } else if (is63xx(dev)) {
 358                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 359                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 360         } else {
 361                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 362                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 363         }
 364
 365         mgmt &= ~SM_SW_FWD_MODE;
 366
 367         if (enable) {
 368                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 369                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 370                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 371                 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 372                 vc5 |= VC5_DROP_VTABLE_MISS;
 373
 374                 if (is5325(dev))
 375                         vc0 &= ~VC0_RESERVED_1;
 376
 377                 if (is5325(dev) || is5365(dev))
 378                         vc1 |= VC1_RX_MCST_TAG_EN;
 379
 380         } else {
 381                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 382                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 383                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 384                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 385
 386                 if (is5325(dev) || is5365(dev))
 387                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 388                 else
 389                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 390
 391                 if (is5325(dev) || is5365(dev))
 392                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 393         }
 394
 395         if (!is5325(dev) && !is5365(dev))
 396                 vc5 &= ~VC5_VID_FFF_EN;
 397
 398         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 399         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 400
 401         if (is5325(dev) || is5365(dev)) {
 402                 /* enable the high 8 bit vid check on 5325 */
 403                 if (is5325(dev) && enable)
 404                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 405                                    VC3_HIGH_8BIT_EN);
 406                 else
 407                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 408
 409                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 410                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 411         } else if (is63xx(dev)) {
 412                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 413                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 414                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 415         } else {
 416                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 417                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 418                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 419         }
 420
 421         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 422 }
 423
 424 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 425 {
 426         u32 port_mask = 0;
 427         u16 max_size = JMS_MIN_SIZE;
 428
 429         if (is5325(dev) || is5365(dev))
 430                 return -EINVAL;
 431
 432         if (enable) {
 433                 port_mask = dev->enabled_ports;
 434                 max_size = JMS_MAX_SIZE;
 435                 if (allow_10_100)
 436                         port_mask |= JPM_10_100_JUMBO_EN;
 437         }
 438
 439         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 440         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 441 }
 442
 443 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 444 {
 445         unsigned int i;
 446
 447         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 448                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 449
 450         for (i = 0; i < 10; i++) {
 451                 u8 fast_age_ctrl;
 452
 453                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 454                           &fast_age_ctrl);
 455
 456                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 457                         goto out;
 458
 459                 msleep(1);
 460         }
 461
 462         return -ETIMEDOUT;
 463 out:
 464         /* Only age dynamic entries (default behavior) */
 465         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 466         return 0;
 467 }
 468
 469 static int b53_fast_age_port(struct b53_device *dev, int port)
 470 {
 471         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 472
 473         return b53_flush_arl(dev, FAST_AGE_PORT);
 474 }
 475
 476 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 477 {
 478         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 479
 480         return b53_flush_arl(dev, FAST_AGE_VLAN);
 481 }
 482
 483 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 484 {
 485         struct b53_device *dev = ds->priv;
 486         unsigned int i;
 487         u16 pvlan;
 488
 489         /* Enable the IMP port to be in the same VLAN as the other ports
 490          * on a per-port basis such that we only have Port i and IMP in
 491          * the same VLAN.
 492          */
 493         b53_for_each_port(dev, i) {
 494                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 495                 pvlan |= BIT(cpu_port);
 496                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 497         }
 498 }
 499 EXPORT_SYMBOL(b53_imp_vlan_setup);
 500
 501 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 502 {
 503         struct b53_device *dev = ds->priv;
 504         unsigned int cpu_port = ds->ports[port].cpu_dp->index;
 505         u16 pvlan;
 506
 507         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 508         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 509
 510         /* Set this port, and only this one to be in the default VLAN,
 511          * if member of a bridge, restore its membership prior to
 512          * bringing down this port.
 513          */
 514         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 515         pvlan &= ~0x1ff;
 516         pvlan |= BIT(port);
 517         pvlan |= dev->ports[port].vlan_ctl_mask;
 518         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 519
 520         b53_imp_vlan_setup(ds, cpu_port);
 521
 522         /* If EEE was enabled, restore it */
 523         if (dev->ports[port].eee.eee_enabled)
 524                 b53_eee_enable_set(ds, port, true);
 525
 526         return 0;
 527 }
 528 EXPORT_SYMBOL(b53_enable_port);
 529
 530 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 531 {
 532         struct b53_device *dev = ds->priv;
 533         u8 reg;
 534
 535         /* Disable Tx/Rx for the port */
 536         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 537         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 538         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 539 }
 540 EXPORT_SYMBOL(b53_disable_port);
 541
 542 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 543 {
 544         bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
 545                          DSA_TAG_PROTO_NONE);
 546         struct b53_device *dev = ds->priv;
 547         u8 hdr_ctl, val;
 548         u16 reg;
 549
 550         /* Resolve which bit controls the Broadcom tag */
 551         switch (port) {
 552         case 8:
 553                 val = BRCM_HDR_P8_EN;
 554                 break;
 555         case 7:
 556                 val = BRCM_HDR_P7_EN;
 557                 break;
 558         case 5:
 559                 val = BRCM_HDR_P5_EN;
 560                 break;
 561         default:
 562                 val = 0;
 563                 break;
 564         }
 565
 566         /* Enable Broadcom tags for IMP port */
 567         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 568         if (tag_en)
 569                 hdr_ctl |= val;
 570         else
 571                 hdr_ctl &= ~val;
 572         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 573
 574         /* Registers below are only accessible on newer devices */
 575         if (!is58xx(dev))
 576                 return;
 577
 578         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 579          * allow us to tag outgoing frames
 580          */
 581         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 582         if (tag_en)
 583                 reg &= ~BIT(port);
 584         else
 585                 reg |= BIT(port);
 586         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 587
 588         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 589          * allow delivering frames to the per-port net_devices
 590          */
 591         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 592         if (tag_en)
 593                 reg &= ~BIT(port);
 594         else
 595                 reg |= BIT(port);
 596         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 597 }
 598 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 599
 600 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 601 {
 602         u8 port_ctrl;
 603
 604         /* BCM5325 CPU port is at 8 */
 605         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 606                 port = B53_CPU_PORT;
 607
 608         port_ctrl = PORT_CTRL_RX_BCST_EN |
 609                     PORT_CTRL_RX_MCST_EN |
 610                     PORT_CTRL_RX_UCST_EN;
 611         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 612
 613         b53_brcm_hdr_setup(dev->ds, port);
 614 }
 615
 616 static void b53_enable_mib(struct b53_device *dev)
 617 {
 618         u8 gc;
 619
 620         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 621         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 622         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 623 }
 624
 625 int b53_configure_vlan(struct dsa_switch *ds)
 626 {
 627         struct b53_device *dev = ds->priv;
 628         struct b53_vlan vl = { 0 };
 629         int i;
 630
 631         /* clear all vlan entries */
 632         if (is5325(dev) || is5365(dev)) {
 633                 for (i = 1; i < dev->num_vlans; i++)
 634                         b53_set_vlan_entry(dev, i, &vl);
 635         } else {
 636                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 637         }
 638
 639         b53_enable_vlan(dev, false);
 640
 641         b53_for_each_port(dev, i)
 642                 b53_write16(dev, B53_VLAN_PAGE,
 643                             B53_VLAN_PORT_DEF_TAG(i), 1);
 644
 645         if (!is5325(dev) && !is5365(dev))
 646                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 647
 648         return 0;
 649 }
 650 EXPORT_SYMBOL(b53_configure_vlan);
 651
 652 static void b53_switch_reset_gpio(struct b53_device *dev)
 653 {
 654         int gpio = dev->reset_gpio;
 655
 656         if (gpio < 0)
 657                 return;
 658
 659         /* Reset sequence: RESET low(50ms)->high(20ms)
 660          */
 661         gpio_set_value(gpio, 0);
 662         mdelay(50);
 663
 664         gpio_set_value(gpio, 1);
 665         mdelay(20);
 666
 667         dev->current_page = 0xff;
 668 }
 669
 670 static int b53_switch_reset(struct b53_device *dev)
 671 {
 672         unsigned int timeout = 1000;
 673         u8 mgmt, reg;
 674
 675         b53_switch_reset_gpio(dev);
 676
 677         if (is539x(dev)) {
 678                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 679                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 680         }
 681
 682         /* This is specific to 58xx devices here, do not use is58xx() which
 683          * covers the larger Starfigther 2 family, including 7445/7278 which
 684          * still use this driver as a library and need to perform the reset
 685          * earlier.
 686          */
 687         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 688             dev->chip_id == BCM583XX_DEVICE_ID) {
 689                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 690                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 691                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 692
 693                 do {
 694                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 695                         if (!(reg & SW_RST))
 696                                 break;
 697
 698                         usleep_range(1000, 2000);
 699                 } while (timeout-- > 0);
 700
 701                 if (timeout == 0)
 702                         return -ETIMEDOUT;
 703         }
 704
 705         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 706
 707         if (!(mgmt & SM_SW_FWD_EN)) {
 708                 mgmt &= ~SM_SW_FWD_MODE;
 709                 mgmt |= SM_SW_FWD_EN;
 710
 711                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 712                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 713
 714                 if (!(mgmt & SM_SW_FWD_EN)) {
 715                         dev_err(dev->dev, "Failed to enable switch!\n");
 716                         return -EINVAL;
 717                 }
 718         }
 719
 720         b53_enable_mib(dev);
 721
 722         return b53_flush_arl(dev, FAST_AGE_STATIC);
 723 }
 724
 725 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 726 {
 727         struct b53_device *priv = ds->priv;
 728         u16 value = 0;
 729         int ret;
 730
 731         if (priv->ops->phy_read16)
 732                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 733         else
 734                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 735                                  reg * 2, &value);
 736
 737         return ret ? ret : value;
 738 }
 739
 740 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 741 {
 742         struct b53_device *priv = ds->priv;
 743
 744         if (priv->ops->phy_write16)
 745                 return priv->ops->phy_write16(priv, addr, reg, val);
 746
 747         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 748 }
 749
 750 static int b53_reset_switch(struct b53_device *priv)
 751 {
 752         /* reset vlans */
 753         priv->enable_jumbo = false;
 754
 755         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 756         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 757
 758         return b53_switch_reset(priv);
 759 }
 760
 761 static int b53_apply_config(struct b53_device *priv)
 762 {
 763         /* disable switching */
 764         b53_set_forwarding(priv, 0);
 765
 766         b53_configure_vlan(priv->ds);
 767
 768         /* enable switching */
 769         b53_set_forwarding(priv, 1);
 770
 771         return 0;
 772 }
 773
 774 static void b53_reset_mib(struct b53_device *priv)
 775 {
 776         u8 gc;
 777
 778         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 779
 780         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 781         msleep(1);
 782         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 783         msleep(1);
 784 }
 785
 786 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 787 {
 788         if (is5365(dev))
 789                 return b53_mibs_65;
 790         else if (is63xx(dev))
 791                 return b53_mibs_63xx;
 792         else if (is58xx(dev))
 793                 return b53_mibs_58xx;
 794         else
 795                 return b53_mibs;
 796 }
 797
 798 static unsigned int b53_get_mib_size(struct b53_device *dev)
 799 {
 800         if (is5365(dev))
 801                 return B53_MIBS_65_SIZE;
 802         else if (is63xx(dev))
 803                 return B53_MIBS_63XX_SIZE;
 804         else if (is58xx(dev))
 805                 return B53_MIBS_58XX_SIZE;
 806         else
 807                 return B53_MIBS_SIZE;
 808 }
 809
 810 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 811 {
 812         /* These ports typically do not have built-in PHYs */
 813         switch (port) {
 814         case B53_CPU_PORT_25:
 815         case 7:
 816         case B53_CPU_PORT:
 817                 return NULL;
 818         }
 819
 820         return mdiobus_get_phy(ds->slave_mii_bus, port);
 821 }
 822
 823 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 824                      uint8_t *data)
 825 {
 826         struct b53_device *dev = ds->priv;
 827         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 828         unsigned int mib_size = b53_get_mib_size(dev);
 829         struct phy_device *phydev;
 830         unsigned int i;
 831
 832         if (stringset == ETH_SS_STATS) {
 833                 for (i = 0; i < mib_size; i++)
 834                         strlcpy(data + i * ETH_GSTRING_LEN,
 835                                 mibs[i].name, ETH_GSTRING_LEN);
 836         } else if (stringset == ETH_SS_PHY_STATS) {
 837                 phydev = b53_get_phy_device(ds, port);
 838                 if (!phydev)
 839                         return;
 840
 841                 phy_ethtool_get_strings(phydev, data);
 842         }
 843 }
 844 EXPORT_SYMBOL(b53_get_strings);
 845
 846 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 847 {
 848         struct b53_device *dev = ds->priv;
 849         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 850         unsigned int mib_size = b53_get_mib_size(dev);
 851         const struct b53_mib_desc *s;
 852         unsigned int i;
 853         u64 val = 0;
 854
 855         if (is5365(dev) && port == 5)
 856                 port = 8;
 857
 858         mutex_lock(&dev->stats_mutex);
 859
 860         for (i = 0; i < mib_size; i++) {
 861                 s = &mibs[i];
 862
 863                 if (s->size == 8) {
 864                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 865                 } else {
 866                         u32 val32;
 867
 868                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 869                                    &val32);
 870                         val = val32;
 871                 }
 872                 data[i] = (u64)val;
 873         }
 874
 875         mutex_unlock(&dev->stats_mutex);
 876 }
 877 EXPORT_SYMBOL(b53_get_ethtool_stats);
 878
 879 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
 880 {
 881         struct phy_device *phydev;
 882
 883         phydev = b53_get_phy_device(ds, port);
 884         if (!phydev)
 885                 return;
 886
 887         phy_ethtool_get_stats(phydev, NULL, data);
 888 }
 889 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
 890
 891 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
 892 {
 893         struct b53_device *dev = ds->priv;
 894         struct phy_device *phydev;
 895
 896         if (sset == ETH_SS_STATS) {
 897                 return b53_get_mib_size(dev);
 898         } else if (sset == ETH_SS_PHY_STATS) {
 899                 phydev = b53_get_phy_device(ds, port);
 900                 if (!phydev)
 901                         return 0;
 902
 903                 return phy_ethtool_get_sset_count(phydev);
 904         }
 905
 906         return 0;
 907 }
 908 EXPORT_SYMBOL(b53_get_sset_count);
 909
 910 static int b53_setup(struct dsa_switch *ds)
 911 {
 912         struct b53_device *dev = ds->priv;
 913         unsigned int port;
 914         int ret;
 915
 916         ret = b53_reset_switch(dev);
 917         if (ret) {
 918                 dev_err(ds->dev, "failed to reset switch\n");
 919                 return ret;
 920         }
 921
 922         b53_reset_mib(dev);
 923
 924         ret = b53_apply_config(dev);
 925         if (ret)
 926                 dev_err(ds->dev, "failed to apply configuration\n");
 927
 928         /* Configure IMP/CPU port, disable unused ports. Enabled
 929          * ports will be configured with .port_enable
 930          */
 931         for (port = 0; port < dev->num_ports; port++) {
 932                 if (dsa_is_cpu_port(ds, port))
 933                         b53_enable_cpu_port(dev, port);
 934                 else if (dsa_is_unused_port(ds, port))
 935                         b53_disable_port(ds, port, NULL);
 936         }
 937
 938         return ret;
 939 }
 940
 941 static void b53_adjust_link(struct dsa_switch *ds, int port,
 942                             struct phy_device *phydev)
 943 {
 944         struct b53_device *dev = ds->priv;
 945         struct ethtool_eee *p = &dev->ports[port].eee;
 946         u8 rgmii_ctrl = 0, reg = 0, off;
 947
 948         if (!phy_is_pseudo_fixed_link(phydev))
 949                 return;
 950
 951         /* Override the port settings */
 952         if (port == dev->cpu_port) {
 953                 off = B53_PORT_OVERRIDE_CTRL;
 954                 reg = PORT_OVERRIDE_EN;
 955         } else {
 956                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 957                 reg = GMII_PO_EN;
 958         }
 959
 960         /* Set the link UP */
 961         if (phydev->link)
 962                 reg |= PORT_OVERRIDE_LINK;
 963
 964         if (phydev->duplex == DUPLEX_FULL)
 965                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
 966
 967         switch (phydev->speed) {
 968         case 2000:
 969                 reg |= PORT_OVERRIDE_SPEED_2000M;
 970                 /* fallthrough */
 971         case SPEED_1000:
 972                 reg |= PORT_OVERRIDE_SPEED_1000M;
 973                 break;
 974         case SPEED_100:
 975                 reg |= PORT_OVERRIDE_SPEED_100M;
 976                 break;
 977         case SPEED_10:
 978                 reg |= PORT_OVERRIDE_SPEED_10M;
 979                 break;
 980         default:
 981                 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
 982                 return;
 983         }
 984
 985         /* Enable flow control on BCM5301x's CPU port */
 986         if (is5301x(dev) && port == dev->cpu_port)
 987                 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
 988
 989         if (phydev->pause) {
 990                 if (phydev->asym_pause)
 991                         reg |= PORT_OVERRIDE_TX_FLOW;
 992                 reg |= PORT_OVERRIDE_RX_FLOW;
 993         }
 994
 995         b53_write8(dev, B53_CTRL_PAGE, off, reg);
 996
 997         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
 998                 if (port == 8)
 999                         off = B53_RGMII_CTRL_IMP;
1000                 else
1001                         off = B53_RGMII_CTRL_P(port);
1002
1003                 /* Configure the port RGMII clock delay by DLL disabled and
1004                  * tx_clk aligned timing (restoring to reset defaults)
1005                  */
1006                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1007                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1008                                 RGMII_CTRL_TIMING_SEL);
1009
1010                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1011                  * sure that we enable the port TX clock internal delay to
1012                  * account for this internal delay that is inserted, otherwise
1013                  * the switch won't be able to receive correctly.
1014                  *
1015                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1016                  * any delay neither on transmission nor reception, so the
1017                  * BCM53125 must also be configured accordingly to account for
1018                  * the lack of delay and introduce
1019                  *
1020                  * The BCM53125 switch has its RX clock and TX clock control
1021                  * swapped, hence the reason why we modify the TX clock path in
1022                  * the "RGMII" case
1023                  */
1024                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1025                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1026                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1027                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1028                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1029                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1030
1031                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1032                          phy_modes(phydev->interface));
1033         }
1034
1035         /* configure MII port if necessary */
1036         if (is5325(dev)) {
1037                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1038                           &reg);
1039
1040                 /* reverse mii needs to be enabled */
1041                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1042                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1043                                    reg | PORT_OVERRIDE_RV_MII_25);
1044                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1045                                   &reg);
1046
1047                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1048                                 dev_err(ds->dev,
1049                                         "Failed to enable reverse MII mode\n");
1050                                 return;
1051                         }
1052                 }
1053         } else if (is5301x(dev)) {
1054                 if (port != dev->cpu_port) {
1055                         u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1056                         u8 gmii_po;
1057
1058                         b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1059                         gmii_po |= GMII_PO_LINK |
1060                                    GMII_PO_RX_FLOW |
1061                                    GMII_PO_TX_FLOW |
1062                                    GMII_PO_EN |
1063                                    GMII_PO_SPEED_2000M;
1064                         b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1065                 }
1066         }
1067
1068         /* Re-negotiate EEE if it was enabled already */
1069         p->eee_enabled = b53_eee_init(ds, port, phydev);
1070 }
1071
1072 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1073 {
1074         return 0;
1075 }
1076 EXPORT_SYMBOL(b53_vlan_filtering);
1077
1078 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1079                      const struct switchdev_obj_port_vlan *vlan)
1080 {
1081         struct b53_device *dev = ds->priv;
1082
1083         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1084                 return -EOPNOTSUPP;
1085
1086         if (vlan->vid_end > dev->num_vlans)
1087                 return -ERANGE;
1088
1089         b53_enable_vlan(dev, true);
1090
1091         return 0;
1092 }
1093 EXPORT_SYMBOL(b53_vlan_prepare);
1094
1095 void b53_vlan_add(struct dsa_switch *ds, int port,
1096                   const struct switchdev_obj_port_vlan *vlan)
1097 {
1098         struct b53_device *dev = ds->priv;
1099         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1100         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1101         struct b53_vlan *vl;
1102         u16 vid;
1103
1104         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1105                 vl = &dev->vlans[vid];
1106
1107                 b53_get_vlan_entry(dev, vid, vl);
1108
1109                 vl->members |= BIT(port);
1110                 if (untagged && !dsa_is_cpu_port(ds, port))
1111                         vl->untag |= BIT(port);
1112                 else
1113                         vl->untag &= ~BIT(port);
1114
1115                 b53_set_vlan_entry(dev, vid, vl);
1116                 b53_fast_age_vlan(dev, vid);
1117         }
1118
1119         if (pvid) {
1120                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1121                             vlan->vid_end);
1122                 b53_fast_age_vlan(dev, vid);
1123         }
1124 }
1125 EXPORT_SYMBOL(b53_vlan_add);
1126
1127 int b53_vlan_del(struct dsa_switch *ds, int port,
1128                  const struct switchdev_obj_port_vlan *vlan)
1129 {
1130         struct b53_device *dev = ds->priv;
1131         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1132         struct b53_vlan *vl;
1133         u16 vid;
1134         u16 pvid;
1135
1136         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1137
1138         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1139                 vl = &dev->vlans[vid];
1140
1141                 b53_get_vlan_entry(dev, vid, vl);
1142
1143                 vl->members &= ~BIT(port);
1144
1145                 if (pvid == vid) {
1146                         if (is5325(dev) || is5365(dev))
1147                                 pvid = 1;
1148                         else
1149                                 pvid = 0;
1150                 }
1151
1152                 if (untagged && !dsa_is_cpu_port(ds, port))
1153                         vl->untag &= ~(BIT(port));
1154
1155                 b53_set_vlan_entry(dev, vid, vl);
1156                 b53_fast_age_vlan(dev, vid);
1157         }
1158
1159         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1160         b53_fast_age_vlan(dev, pvid);
1161
1162         return 0;
1163 }
1164 EXPORT_SYMBOL(b53_vlan_del);
1165
1166 /* Address Resolution Logic routines */
1167 static int b53_arl_op_wait(struct b53_device *dev)
1168 {
1169         unsigned int timeout = 10;
1170         u8 reg;
1171
1172         do {
1173                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1174                 if (!(reg & ARLTBL_START_DONE))
1175                         return 0;
1176
1177                 usleep_range(1000, 2000);
1178         } while (timeout--);
1179
1180         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1181
1182         return -ETIMEDOUT;
1183 }
1184
1185 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1186 {
1187         u8 reg;
1188
1189         if (op > ARLTBL_RW)
1190                 return -EINVAL;
1191
1192         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1193         reg |= ARLTBL_START_DONE;
1194         if (op)
1195                 reg |= ARLTBL_RW;
1196         else
1197                 reg &= ~ARLTBL_RW;
1198         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1199
1200         return b53_arl_op_wait(dev);
1201 }
1202
1203 static int b53_arl_read(struct b53_device *dev, u64 mac,
1204                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1205                         bool is_valid)
1206 {
1207         unsigned int i;
1208         int ret;
1209
1210         ret = b53_arl_op_wait(dev);
1211         if (ret)
1212                 return ret;
1213
1214         /* Read the bins */
1215         for (i = 0; i < dev->num_arl_entries; i++) {
1216                 u64 mac_vid;
1217                 u32 fwd_entry;
1218
1219                 b53_read64(dev, B53_ARLIO_PAGE,
1220                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1221                 b53_read32(dev, B53_ARLIO_PAGE,
1222                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1223                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1224
1225                 if (!(fwd_entry & ARLTBL_VALID))
1226                         continue;
1227                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1228                         continue;
1229                 *idx = i;
1230         }
1231
1232         return -ENOENT;
1233 }
1234
1235 static int b53_arl_op(struct b53_device *dev, int op, int port,
1236                       const unsigned char *addr, u16 vid, bool is_valid)
1237 {
1238         struct b53_arl_entry ent;
1239         u32 fwd_entry;
1240         u64 mac, mac_vid = 0;
1241         u8 idx = 0;
1242         int ret;
1243
1244         /* Convert the array into a 64-bit MAC */
1245         mac = ether_addr_to_u64(addr);
1246
1247         /* Perform a read for the given MAC and VID */
1248         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1249         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1250
1251         /* Issue a read operation for this MAC */
1252         ret = b53_arl_rw_op(dev, 1);
1253         if (ret)
1254                 return ret;
1255
1256         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1257         /* If this is a read, just finish now */
1258         if (op)
1259                 return ret;
1260
1261         /* We could not find a matching MAC, so reset to a new entry */
1262         if (ret) {
1263                 fwd_entry = 0;
1264                 idx = 1;
1265         }
1266
1267         memset(&ent, 0, sizeof(ent));
1268         ent.port = port;
1269         ent.is_valid = is_valid;
1270         ent.vid = vid;
1271         ent.is_static = true;
1272         memcpy(ent.mac, addr, ETH_ALEN);
1273         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1274
1275         b53_write64(dev, B53_ARLIO_PAGE,
1276                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1277         b53_write32(dev, B53_ARLIO_PAGE,
1278                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1279
1280         return b53_arl_rw_op(dev, 0);
1281 }
1282
1283 int b53_fdb_add(struct dsa_switch *ds, int port,
1284                 const unsigned char *addr, u16 vid)
1285 {
1286         struct b53_device *priv = ds->priv;
1287
1288         /* 5325 and 5365 require some more massaging, but could
1289          * be supported eventually
1290          */
1291         if (is5325(priv) || is5365(priv))
1292                 return -EOPNOTSUPP;
1293
1294         return b53_arl_op(priv, 0, port, addr, vid, true);
1295 }
1296 EXPORT_SYMBOL(b53_fdb_add);
1297
1298 int b53_fdb_del(struct dsa_switch *ds, int port,
1299                 const unsigned char *addr, u16 vid)
1300 {
1301         struct b53_device *priv = ds->priv;
1302
1303         return b53_arl_op(priv, 0, port, addr, vid, false);
1304 }
1305 EXPORT_SYMBOL(b53_fdb_del);
1306
1307 static int b53_arl_search_wait(struct b53_device *dev)
1308 {
1309         unsigned int timeout = 1000;
1310         u8 reg;
1311
1312         do {
1313                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1314                 if (!(reg & ARL_SRCH_STDN))
1315                         return 0;
1316
1317                 if (reg & ARL_SRCH_VLID)
1318                         return 0;
1319
1320                 usleep_range(1000, 2000);
1321         } while (timeout--);
1322
1323         return -ETIMEDOUT;
1324 }
1325
1326 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1327                               struct b53_arl_entry *ent)
1328 {
1329         u64 mac_vid;
1330         u32 fwd_entry;
1331
1332         b53_read64(dev, B53_ARLIO_PAGE,
1333                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1334         b53_read32(dev, B53_ARLIO_PAGE,
1335                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1336         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1337 }
1338
1339 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1340                         dsa_fdb_dump_cb_t *cb, void *data)
1341 {
1342         if (!ent->is_valid)
1343                 return 0;
1344
1345         if (port != ent->port)
1346                 return 0;
1347
1348         return cb(ent->mac, ent->vid, ent->is_static, data);
1349 }
1350
1351 int b53_fdb_dump(struct dsa_switch *ds, int port,
1352                  dsa_fdb_dump_cb_t *cb, void *data)
1353 {
1354         struct b53_device *priv = ds->priv;
1355         struct b53_arl_entry results[2];
1356         unsigned int count = 0;
1357         int ret;
1358         u8 reg;
1359
1360         /* Start search operation */
1361         reg = ARL_SRCH_STDN;
1362         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1363
1364         do {
1365                 ret = b53_arl_search_wait(priv);
1366                 if (ret)
1367                         return ret;
1368
1369                 b53_arl_search_rd(priv, 0, &results[0]);
1370                 ret = b53_fdb_copy(port, &results[0], cb, data);
1371                 if (ret)
1372                         return ret;
1373
1374                 if (priv->num_arl_entries > 2) {
1375                         b53_arl_search_rd(priv, 1, &results[1]);
1376                         ret = b53_fdb_copy(port, &results[1], cb, data);
1377                         if (ret)
1378                                 return ret;
1379
1380                         if (!results[0].is_valid && !results[1].is_valid)
1381                                 break;
1382                 }
1383
1384         } while (count++ < 1024);
1385
1386         return 0;
1387 }
1388 EXPORT_SYMBOL(b53_fdb_dump);
1389
1390 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1391 {
1392         struct b53_device *dev = ds->priv;
1393         s8 cpu_port = ds->ports[port].cpu_dp->index;
1394         u16 pvlan, reg;
1395         unsigned int i;
1396
1397         /* Make this port leave the all VLANs join since we will have proper
1398          * VLAN entries from now on
1399          */
1400         if (is58xx(dev)) {
1401                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1402                 reg &= ~BIT(port);
1403                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1404                         reg &= ~BIT(cpu_port);
1405                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1406         }
1407
1408         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1409
1410         b53_for_each_port(dev, i) {
1411                 if (dsa_to_port(ds, i)->bridge_dev != br)
1412                         continue;
1413
1414                 /* Add this local port to the remote port VLAN control
1415                  * membership and update the remote port bitmask
1416                  */
1417                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1418                 reg |= BIT(port);
1419                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1420                 dev->ports[i].vlan_ctl_mask = reg;
1421
1422                 pvlan |= BIT(i);
1423         }
1424
1425         /* Configure the local port VLAN control membership to include
1426          * remote ports and update the local port bitmask
1427          */
1428         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1429         dev->ports[port].vlan_ctl_mask = pvlan;
1430
1431         return 0;
1432 }
1433 EXPORT_SYMBOL(b53_br_join);
1434
1435 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1436 {
1437         struct b53_device *dev = ds->priv;
1438         struct b53_vlan *vl = &dev->vlans[0];
1439         s8 cpu_port = ds->ports[port].cpu_dp->index;
1440         unsigned int i;
1441         u16 pvlan, reg, pvid;
1442
1443         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1444
1445         b53_for_each_port(dev, i) {
1446                 /* Don't touch the remaining ports */
1447                 if (dsa_to_port(ds, i)->bridge_dev != br)
1448                         continue;
1449
1450                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1451                 reg &= ~BIT(port);
1452                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1453                 dev->ports[port].vlan_ctl_mask = reg;
1454
1455                 /* Prevent self removal to preserve isolation */
1456                 if (port != i)
1457                         pvlan &= ~BIT(i);
1458         }
1459
1460         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1461         dev->ports[port].vlan_ctl_mask = pvlan;
1462
1463         if (is5325(dev) || is5365(dev))
1464                 pvid = 1;
1465         else
1466                 pvid = 0;
1467
1468         /* Make this port join all VLANs without VLAN entries */
1469         if (is58xx(dev)) {
1470                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1471                 reg |= BIT(port);
1472                 if (!(reg & BIT(cpu_port)))
1473                         reg |= BIT(cpu_port);
1474                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1475         } else {
1476                 b53_get_vlan_entry(dev, pvid, vl);
1477                 vl->members |= BIT(port) | BIT(cpu_port);
1478                 vl->untag |= BIT(port) | BIT(cpu_port);
1479                 b53_set_vlan_entry(dev, pvid, vl);
1480         }
1481 }
1482 EXPORT_SYMBOL(b53_br_leave);
1483
1484 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1485 {
1486         struct b53_device *dev = ds->priv;
1487         u8 hw_state;
1488         u8 reg;
1489
1490         switch (state) {
1491         case BR_STATE_DISABLED:
1492                 hw_state = PORT_CTRL_DIS_STATE;
1493                 break;
1494         case BR_STATE_LISTENING:
1495                 hw_state = PORT_CTRL_LISTEN_STATE;
1496                 break;
1497         case BR_STATE_LEARNING:
1498                 hw_state = PORT_CTRL_LEARN_STATE;
1499                 break;
1500         case BR_STATE_FORWARDING:
1501                 hw_state = PORT_CTRL_FWD_STATE;
1502                 break;
1503         case BR_STATE_BLOCKING:
1504                 hw_state = PORT_CTRL_BLOCK_STATE;
1505                 break;
1506         default:
1507                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1508                 return;
1509         }
1510
1511         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1512         reg &= ~PORT_CTRL_STP_STATE_MASK;
1513         reg |= hw_state;
1514         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1515 }
1516 EXPORT_SYMBOL(b53_br_set_stp_state);
1517
1518 void b53_br_fast_age(struct dsa_switch *ds, int port)
1519 {
1520         struct b53_device *dev = ds->priv;
1521
1522         if (b53_fast_age_port(dev, port))
1523                 dev_err(ds->dev, "fast ageing failed\n");
1524 }
1525 EXPORT_SYMBOL(b53_br_fast_age);
1526
1527 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1528 {
1529         /* Broadcom switches will accept enabling Broadcom tags on the
1530          * following ports: 5, 7 and 8, any other port is not supported
1531          */
1532         switch (port) {
1533         case B53_CPU_PORT_25:
1534         case 7:
1535         case B53_CPU_PORT:
1536                 return true;
1537         }
1538
1539         return false;
1540 }
1541
1542 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1543 {
1544         bool ret = b53_possible_cpu_port(ds, port);
1545
1546         if (!ret)
1547                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1548                          port);
1549         return ret;
1550 }
1551
1552 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
1553 {
1554         struct b53_device *dev = ds->priv;
1555
1556         /* Older models (5325, 5365) support a different tag format that we do
1557          * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1558          * mode to be turned on which means we need to specifically manage ARL
1559          * misses on multicast addresses (TBD).
1560          */
1561         if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1562             !b53_can_enable_brcm_tags(ds, port))
1563                 return DSA_TAG_PROTO_NONE;
1564
1565         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1566          * which requires us to use the prepended Broadcom tag type
1567          */
1568         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1569                 return DSA_TAG_PROTO_BRCM_PREPEND;
1570
1571         return DSA_TAG_PROTO_BRCM;
1572 }
1573 EXPORT_SYMBOL(b53_get_tag_protocol);
1574
1575 int b53_mirror_add(struct dsa_switch *ds, int port,
1576                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1577 {
1578         struct b53_device *dev = ds->priv;
1579         u16 reg, loc;
1580
1581         if (ingress)
1582                 loc = B53_IG_MIR_CTL;
1583         else
1584                 loc = B53_EG_MIR_CTL;
1585
1586         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1587         reg &= ~MIRROR_MASK;
1588         reg |= BIT(port);
1589         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1590
1591         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1592         reg &= ~CAP_PORT_MASK;
1593         reg |= mirror->to_local_port;
1594         reg |= MIRROR_EN;
1595         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1596
1597         return 0;
1598 }
1599 EXPORT_SYMBOL(b53_mirror_add);
1600
1601 void b53_mirror_del(struct dsa_switch *ds, int port,
1602                     struct dsa_mall_mirror_tc_entry *mirror)
1603 {
1604         struct b53_device *dev = ds->priv;
1605         bool loc_disable = false, other_loc_disable = false;
1606         u16 reg, loc;
1607
1608         if (mirror->ingress)
1609                 loc = B53_IG_MIR_CTL;
1610         else
1611                 loc = B53_EG_MIR_CTL;
1612
1613         /* Update the desired ingress/egress register */
1614         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1615         reg &= ~BIT(port);
1616         if (!(reg & MIRROR_MASK))
1617                 loc_disable = true;
1618         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1619
1620         /* Now look at the other one to know if we can disable mirroring
1621          * entirely
1622          */
1623         if (mirror->ingress)
1624                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1625         else
1626                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1627         if (!(reg & MIRROR_MASK))
1628                 other_loc_disable = true;
1629
1630         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1631         /* Both no longer have ports, let's disable mirroring */
1632         if (loc_disable && other_loc_disable) {
1633                 reg &= ~MIRROR_EN;
1634                 reg &= ~mirror->to_local_port;
1635         }
1636         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1637 }
1638 EXPORT_SYMBOL(b53_mirror_del);
1639
1640 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1641 {
1642         struct b53_device *dev = ds->priv;
1643         u16 reg;
1644
1645         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1646         if (enable)
1647                 reg |= BIT(port);
1648         else
1649                 reg &= ~BIT(port);
1650         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1651 }
1652 EXPORT_SYMBOL(b53_eee_enable_set);
1653
1654
1655 /* Returns 0 if EEE was not enabled, or 1 otherwise
1656  */
1657 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1658 {
1659         int ret;
1660
1661         ret = phy_init_eee(phy, 0);
1662         if (ret)
1663                 return 0;
1664
1665         b53_eee_enable_set(ds, port, true);
1666
1667         return 1;
1668 }
1669 EXPORT_SYMBOL(b53_eee_init);
1670
1671 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1672 {
1673         struct b53_device *dev = ds->priv;
1674         struct ethtool_eee *p = &dev->ports[port].eee;
1675         u16 reg;
1676
1677         if (is5325(dev) || is5365(dev))
1678                 return -EOPNOTSUPP;
1679
1680         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1681         e->eee_enabled = p->eee_enabled;
1682         e->eee_active = !!(reg & BIT(port));
1683
1684         return 0;
1685 }
1686 EXPORT_SYMBOL(b53_get_mac_eee);
1687
1688 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1689 {
1690         struct b53_device *dev = ds->priv;
1691         struct ethtool_eee *p = &dev->ports[port].eee;
1692
1693         if (is5325(dev) || is5365(dev))
1694                 return -EOPNOTSUPP;
1695
1696         p->eee_enabled = e->eee_enabled;
1697         b53_eee_enable_set(ds, port, e->eee_enabled);
1698
1699         return 0;
1700 }
1701 EXPORT_SYMBOL(b53_set_mac_eee);
1702
1703 static const struct dsa_switch_ops b53_switch_ops = {
1704         .get_tag_protocol       = b53_get_tag_protocol,
1705         .setup                  = b53_setup,
1706         .get_strings            = b53_get_strings,
1707         .get_ethtool_stats      = b53_get_ethtool_stats,
1708         .get_sset_count         = b53_get_sset_count,
1709         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
1710         .phy_read               = b53_phy_read16,
1711         .phy_write              = b53_phy_write16,
1712         .adjust_link            = b53_adjust_link,
1713         .port_enable            = b53_enable_port,
1714         .port_disable           = b53_disable_port,
1715         .get_mac_eee            = b53_get_mac_eee,
1716         .set_mac_eee            = b53_set_mac_eee,
1717         .port_bridge_join       = b53_br_join,
1718         .port_bridge_leave      = b53_br_leave,
1719         .port_stp_state_set     = b53_br_set_stp_state,
1720         .port_fast_age          = b53_br_fast_age,
1721         .port_vlan_filtering    = b53_vlan_filtering,
1722         .port_vlan_prepare      = b53_vlan_prepare,
1723         .port_vlan_add          = b53_vlan_add,
1724         .port_vlan_del          = b53_vlan_del,
1725         .port_fdb_dump          = b53_fdb_dump,
1726         .port_fdb_add           = b53_fdb_add,
1727         .port_fdb_del           = b53_fdb_del,
1728         .port_mirror_add        = b53_mirror_add,
1729         .port_mirror_del        = b53_mirror_del,
1730 };
1731
1732 struct b53_chip_data {
1733         u32 chip_id;
1734         const char *dev_name;
1735         u16 vlans;
1736         u16 enabled_ports;
1737         u8 cpu_port;
1738         u8 vta_regs[3];
1739         u8 arl_entries;
1740         u8 duplex_reg;
1741         u8 jumbo_pm_reg;
1742         u8 jumbo_size_reg;
1743 };
1744
1745 #define B53_VTA_REGS    \
1746         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1747 #define B53_VTA_REGS_9798 \
1748         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1749 #define B53_VTA_REGS_63XX \
1750         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1751
1752 static const struct b53_chip_data b53_switch_chips[] = {
1753         {
1754                 .chip_id = BCM5325_DEVICE_ID,
1755                 .dev_name = "BCM5325",
1756                 .vlans = 16,
1757                 .enabled_ports = 0x1f,
1758                 .arl_entries = 2,
1759                 .cpu_port = B53_CPU_PORT_25,
1760                 .duplex_reg = B53_DUPLEX_STAT_FE,
1761         },
1762         {
1763                 .chip_id = BCM5365_DEVICE_ID,
1764                 .dev_name = "BCM5365",
1765                 .vlans = 256,
1766                 .enabled_ports = 0x1f,
1767                 .arl_entries = 2,
1768                 .cpu_port = B53_CPU_PORT_25,
1769                 .duplex_reg = B53_DUPLEX_STAT_FE,
1770         },
1771         {
1772                 .chip_id = BCM5389_DEVICE_ID,
1773                 .dev_name = "BCM5389",
1774                 .vlans = 4096,
1775                 .enabled_ports = 0x1f,
1776                 .arl_entries = 4,
1777                 .cpu_port = B53_CPU_PORT,
1778                 .vta_regs = B53_VTA_REGS,
1779                 .duplex_reg = B53_DUPLEX_STAT_GE,
1780                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1781                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1782         },
1783         {
1784                 .chip_id = BCM5395_DEVICE_ID,
1785                 .dev_name = "BCM5395",
1786                 .vlans = 4096,
1787                 .enabled_ports = 0x1f,
1788                 .arl_entries = 4,
1789                 .cpu_port = B53_CPU_PORT,
1790                 .vta_regs = B53_VTA_REGS,
1791                 .duplex_reg = B53_DUPLEX_STAT_GE,
1792                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1793                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1794         },
1795         {
1796                 .chip_id = BCM5397_DEVICE_ID,
1797                 .dev_name = "BCM5397",
1798                 .vlans = 4096,
1799                 .enabled_ports = 0x1f,
1800                 .arl_entries = 4,
1801                 .cpu_port = B53_CPU_PORT,
1802                 .vta_regs = B53_VTA_REGS_9798,
1803                 .duplex_reg = B53_DUPLEX_STAT_GE,
1804                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1805                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1806         },
1807         {
1808                 .chip_id = BCM5398_DEVICE_ID,
1809                 .dev_name = "BCM5398",
1810                 .vlans = 4096,
1811                 .enabled_ports = 0x7f,
1812                 .arl_entries = 4,
1813                 .cpu_port = B53_CPU_PORT,
1814                 .vta_regs = B53_VTA_REGS_9798,
1815                 .duplex_reg = B53_DUPLEX_STAT_GE,
1816                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1817                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1818         },
1819         {
1820                 .chip_id = BCM53115_DEVICE_ID,
1821                 .dev_name = "BCM53115",
1822                 .vlans = 4096,
1823                 .enabled_ports = 0x1f,
1824                 .arl_entries = 4,
1825                 .vta_regs = B53_VTA_REGS,
1826                 .cpu_port = B53_CPU_PORT,
1827                 .duplex_reg = B53_DUPLEX_STAT_GE,
1828                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1829                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1830         },
1831         {
1832                 .chip_id = BCM53125_DEVICE_ID,
1833                 .dev_name = "BCM53125",
1834                 .vlans = 4096,
1835                 .enabled_ports = 0xff,
1836                 .arl_entries = 4,
1837                 .cpu_port = B53_CPU_PORT,
1838                 .vta_regs = B53_VTA_REGS,
1839                 .duplex_reg = B53_DUPLEX_STAT_GE,
1840                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1841                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1842         },
1843         {
1844                 .chip_id = BCM53128_DEVICE_ID,
1845                 .dev_name = "BCM53128",
1846                 .vlans = 4096,
1847                 .enabled_ports = 0x1ff,
1848                 .arl_entries = 4,
1849                 .cpu_port = B53_CPU_PORT,
1850                 .vta_regs = B53_VTA_REGS,
1851                 .duplex_reg = B53_DUPLEX_STAT_GE,
1852                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1853                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1854         },
1855         {
1856                 .chip_id = BCM63XX_DEVICE_ID,
1857                 .dev_name = "BCM63xx",
1858                 .vlans = 4096,
1859                 .enabled_ports = 0, /* pdata must provide them */
1860                 .arl_entries = 4,
1861                 .cpu_port = B53_CPU_PORT,
1862                 .vta_regs = B53_VTA_REGS_63XX,
1863                 .duplex_reg = B53_DUPLEX_STAT_63XX,
1864                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1865                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1866         },
1867         {
1868                 .chip_id = BCM53010_DEVICE_ID,
1869                 .dev_name = "BCM53010",
1870                 .vlans = 4096,
1871                 .enabled_ports = 0x1f,
1872                 .arl_entries = 4,
1873                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1874                 .vta_regs = B53_VTA_REGS,
1875                 .duplex_reg = B53_DUPLEX_STAT_GE,
1876                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1877                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1878         },
1879         {
1880                 .chip_id = BCM53011_DEVICE_ID,
1881                 .dev_name = "BCM53011",
1882                 .vlans = 4096,
1883                 .enabled_ports = 0x1bf,
1884                 .arl_entries = 4,
1885                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1886                 .vta_regs = B53_VTA_REGS,
1887                 .duplex_reg = B53_DUPLEX_STAT_GE,
1888                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1889                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1890         },
1891         {
1892                 .chip_id = BCM53012_DEVICE_ID,
1893                 .dev_name = "BCM53012",
1894                 .vlans = 4096,
1895                 .enabled_ports = 0x1bf,
1896                 .arl_entries = 4,
1897                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1898                 .vta_regs = B53_VTA_REGS,
1899                 .duplex_reg = B53_DUPLEX_STAT_GE,
1900                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1901                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1902         },
1903         {
1904                 .chip_id = BCM53018_DEVICE_ID,
1905                 .dev_name = "BCM53018",
1906                 .vlans = 4096,
1907                 .enabled_ports = 0x1f,
1908                 .arl_entries = 4,
1909                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1910                 .vta_regs = B53_VTA_REGS,
1911                 .duplex_reg = B53_DUPLEX_STAT_GE,
1912                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1913                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1914         },
1915         {
1916                 .chip_id = BCM53019_DEVICE_ID,
1917                 .dev_name = "BCM53019",
1918                 .vlans = 4096,
1919                 .enabled_ports = 0x1f,
1920                 .arl_entries = 4,
1921                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1922                 .vta_regs = B53_VTA_REGS,
1923                 .duplex_reg = B53_DUPLEX_STAT_GE,
1924                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1925                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1926         },
1927         {
1928                 .chip_id = BCM58XX_DEVICE_ID,
1929                 .dev_name = "BCM585xx/586xx/88312",
1930                 .vlans  = 4096,
1931                 .enabled_ports = 0x1ff,
1932                 .arl_entries = 4,
1933                 .cpu_port = B53_CPU_PORT,
1934                 .vta_regs = B53_VTA_REGS,
1935                 .duplex_reg = B53_DUPLEX_STAT_GE,
1936                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1937                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1938         },
1939         {
1940                 .chip_id = BCM583XX_DEVICE_ID,
1941                 .dev_name = "BCM583xx/11360",
1942                 .vlans = 4096,
1943                 .enabled_ports = 0x103,
1944                 .arl_entries = 4,
1945                 .cpu_port = B53_CPU_PORT,
1946                 .vta_regs = B53_VTA_REGS,
1947                 .duplex_reg = B53_DUPLEX_STAT_GE,
1948                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1949                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1950         },
1951         {
1952                 .chip_id = BCM7445_DEVICE_ID,
1953                 .dev_name = "BCM7445",
1954                 .vlans  = 4096,
1955                 .enabled_ports = 0x1ff,
1956                 .arl_entries = 4,
1957                 .cpu_port = B53_CPU_PORT,
1958                 .vta_regs = B53_VTA_REGS,
1959                 .duplex_reg = B53_DUPLEX_STAT_GE,
1960                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1961                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1962         },
1963         {
1964                 .chip_id = BCM7278_DEVICE_ID,
1965                 .dev_name = "BCM7278",
1966                 .vlans = 4096,
1967                 .enabled_ports = 0x1ff,
1968                 .arl_entries= 4,
1969                 .cpu_port = B53_CPU_PORT,
1970                 .vta_regs = B53_VTA_REGS,
1971                 .duplex_reg = B53_DUPLEX_STAT_GE,
1972                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1973                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1974         },
1975 };
1976
1977 static int b53_switch_init(struct b53_device *dev)
1978 {
1979         unsigned int i;
1980         int ret;
1981
1982         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1983                 const struct b53_chip_data *chip = &b53_switch_chips[i];
1984
1985                 if (chip->chip_id == dev->chip_id) {
1986                         if (!dev->enabled_ports)
1987                                 dev->enabled_ports = chip->enabled_ports;
1988                         dev->name = chip->dev_name;
1989                         dev->duplex_reg = chip->duplex_reg;
1990                         dev->vta_regs[0] = chip->vta_regs[0];
1991                         dev->vta_regs[1] = chip->vta_regs[1];
1992                         dev->vta_regs[2] = chip->vta_regs[2];
1993                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1994                         dev->cpu_port = chip->cpu_port;
1995                         dev->num_vlans = chip->vlans;
1996                         dev->num_arl_entries = chip->arl_entries;
1997                         break;
1998                 }
1999         }
2000
2001         /* check which BCM5325x version we have */
2002         if (is5325(dev)) {
2003                 u8 vc4;
2004
2005                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2006
2007                 /* check reserved bits */
2008                 switch (vc4 & 3) {
2009                 case 1:
2010                         /* BCM5325E */
2011                         break;
2012                 case 3:
2013                         /* BCM5325F - do not use port 4 */
2014                         dev->enabled_ports &= ~BIT(4);
2015                         break;
2016                 default:
2017 /* On the BCM47XX SoCs this is the supported internal switch.*/
2018 #ifndef CONFIG_BCM47XX
2019                         /* BCM5325M */
2020                         return -EINVAL;
2021 #else
2022                         break;
2023 #endif
2024                 }
2025         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2026                 u64 strap_value;
2027
2028                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2029                 /* use second IMP port if GMII is enabled */
2030                 if (strap_value & SV_GMII_CTRL_115)
2031                         dev->cpu_port = 5;
2032         }
2033
2034         /* cpu port is always last */
2035         dev->num_ports = dev->cpu_port + 1;
2036         dev->enabled_ports |= BIT(dev->cpu_port);
2037
2038         /* Include non standard CPU port built-in PHYs to be probed */
2039         if (is539x(dev) || is531x5(dev)) {
2040                 for (i = 0; i < dev->num_ports; i++) {
2041                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2042                             !b53_possible_cpu_port(dev->ds, i))
2043                                 dev->ds->phys_mii_mask |= BIT(i);
2044                 }
2045         }
2046
2047         dev->ports = devm_kcalloc(dev->dev,
2048                                   dev->num_ports, sizeof(struct b53_port),
2049                                   GFP_KERNEL);
2050         if (!dev->ports)
2051                 return -ENOMEM;
2052
2053         dev->vlans = devm_kcalloc(dev->dev,
2054                                   dev->num_vlans, sizeof(struct b53_vlan),
2055                                   GFP_KERNEL);
2056         if (!dev->vlans)
2057                 return -ENOMEM;
2058
2059         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2060         if (dev->reset_gpio >= 0) {
2061                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2062                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2063                 if (ret)
2064                         return ret;
2065         }
2066
2067         return 0;
2068 }
2069
2070 struct b53_device *b53_switch_alloc(struct device *base,
2071                                     const struct b53_io_ops *ops,
2072                                     void *priv)
2073 {
2074         struct dsa_switch *ds;
2075         struct b53_device *dev;
2076
2077         ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2078         if (!ds)
2079                 return NULL;
2080
2081         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2082         if (!dev)
2083                 return NULL;
2084
2085         ds->priv = dev;
2086         dev->dev = base;
2087
2088         dev->ds = ds;
2089         dev->priv = priv;
2090         dev->ops = ops;
2091         ds->ops = &b53_switch_ops;
2092         mutex_init(&dev->reg_mutex);
2093         mutex_init(&dev->stats_mutex);
2094
2095         return dev;
2096 }
2097 EXPORT_SYMBOL(b53_switch_alloc);
2098
2099 int b53_switch_detect(struct b53_device *dev)
2100 {
2101         u32 id32;
2102         u16 tmp;
2103         u8 id8;
2104         int ret;
2105
2106         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2107         if (ret)
2108                 return ret;
2109
2110         switch (id8) {
2111         case 0:
2112                 /* BCM5325 and BCM5365 do not have this register so reads
2113                  * return 0. But the read operation did succeed, so assume this
2114                  * is one of them.
2115                  *
2116                  * Next check if we can write to the 5325's VTA register; for
2117                  * 5365 it is read only.
2118                  */
2119                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2120                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2121
2122                 if (tmp == 0xf)
2123                         dev->chip_id = BCM5325_DEVICE_ID;
2124                 else
2125                         dev->chip_id = BCM5365_DEVICE_ID;
2126                 break;
2127         case BCM5389_DEVICE_ID:
2128         case BCM5395_DEVICE_ID:
2129         case BCM5397_DEVICE_ID:
2130         case BCM5398_DEVICE_ID:
2131                 dev->chip_id = id8;
2132                 break;
2133         default:
2134                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2135                 if (ret)
2136                         return ret;
2137
2138                 switch (id32) {
2139                 case BCM53115_DEVICE_ID:
2140                 case BCM53125_DEVICE_ID:
2141                 case BCM53128_DEVICE_ID:
2142                 case BCM53010_DEVICE_ID:
2143                 case BCM53011_DEVICE_ID:
2144                 case BCM53012_DEVICE_ID:
2145                 case BCM53018_DEVICE_ID:
2146                 case BCM53019_DEVICE_ID:
2147                         dev->chip_id = id32;
2148                         break;
2149                 default:
2150                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2151                                id8, id32);
2152                         return -ENODEV;
2153                 }
2154         }
2155
2156         if (dev->chip_id == BCM5325_DEVICE_ID)
2157                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2158                                  &dev->core_rev);
2159         else
2160                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2161                                  &dev->core_rev);
2162 }
2163 EXPORT_SYMBOL(b53_switch_detect);
2164
2165 int b53_switch_register(struct b53_device *dev)
2166 {
2167         int ret;
2168
2169         if (dev->pdata) {
2170                 dev->chip_id = dev->pdata->chip_id;
2171                 dev->enabled_ports = dev->pdata->enabled_ports;
2172         }
2173
2174         if (!dev->chip_id && b53_switch_detect(dev))
2175                 return -EINVAL;
2176
2177         ret = b53_switch_init(dev);
2178         if (ret)
2179                 return ret;
2180
2181         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2182
2183         return dsa_register_switch(dev->ds);
2184 }
2185 EXPORT_SYMBOL(b53_switch_register);
2186
2187 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2188 MODULE_DESCRIPTION("B53 switch library");
2189 MODULE_LICENSE("Dual BSD/GPL");