1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/crc32.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/circ_buf.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/gpio.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/interrupt.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/macb.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/ip.h>
37 #include <linux/udp.h>
38 #include <linux/tcp.h>
39 #include "macb.h"
41 #define MACB_RX_BUFFER_SIZE 128
42 #define RX_BUFFER_MULTIPLE 64 /* bytes */
44 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
45 #define MIN_RX_RING_SIZE 64
46 #define MAX_RX_RING_SIZE 8192
47 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
48 * (bp)->rx_ring_size)
50 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_TX_RING_SIZE 64
52 #define MAX_TX_RING_SIZE 4096
53 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
54 * (bp)->tx_ring_size)
56 /* level of occupied TX descriptors under which we wake up TX process */
57 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
59 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
60 | MACB_BIT(ISR_ROVR))
61 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
62 | MACB_BIT(ISR_RLE) \
63 | MACB_BIT(TXERR))
64 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
66 /* Max length of transmit frame must be a multiple of 8 bytes */
67 #define MACB_TX_LEN_ALIGN 8
68 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
69 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
71 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
72 #define MACB_NETIF_LSO NETIF_F_TSO
74 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
75 #define MACB_WOL_ENABLED (0x1 << 1)
77 /* Graceful stop timeouts in us. We should allow up to
78 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
79 */
80 #define MACB_HALT_TIMEOUT 1230
82 /* DMA buffer descriptor might be different size
83 * depends on hardware configuration:
84 *
85 * 1. dma address width 32 bits:
86 * word 1: 32 bit address of Data Buffer
87 * word 2: control
88 *
89 * 2. dma address width 64 bits:
90 * word 1: 32 bit address of Data Buffer
91 * word 2: control
92 * word 3: upper 32 bit address of Data Buffer
93 * word 4: unused
94 *
95 * 3. dma address width 32 bits with hardware timestamping:
96 * word 1: 32 bit address of Data Buffer
97 * word 2: control
98 * word 3: timestamp word 1
99 * word 4: timestamp word 2
100 *
101 * 4. dma address width 64 bits with hardware timestamping:
102 * word 1: 32 bit address of Data Buffer
103 * word 2: control
104 * word 3: upper 32 bit address of Data Buffer
105 * word 4: unused
106 * word 5: timestamp word 1
107 * word 6: timestamp word 2
108 */
109 static unsigned int macb_dma_desc_get_size(struct macb *bp)
110 {
111 #ifdef MACB_EXT_DESC
112 unsigned int desc_size;
114 switch (bp->hw_dma_cap) {
115 case HW_DMA_CAP_64B:
116 desc_size = sizeof(struct macb_dma_desc)
117 + sizeof(struct macb_dma_desc_64);
118 break;
119 case HW_DMA_CAP_PTP:
120 desc_size = sizeof(struct macb_dma_desc)
121 + sizeof(struct macb_dma_desc_ptp);
122 break;
123 case HW_DMA_CAP_64B_PTP:
124 desc_size = sizeof(struct macb_dma_desc)
125 + sizeof(struct macb_dma_desc_64)
126 + sizeof(struct macb_dma_desc_ptp);
127 break;
128 default:
129 desc_size = sizeof(struct macb_dma_desc);
130 }
131 return desc_size;
132 #endif
133 return sizeof(struct macb_dma_desc);
134 }
136 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
137 {
138 #ifdef MACB_EXT_DESC
139 switch (bp->hw_dma_cap) {
140 case HW_DMA_CAP_64B:
141 case HW_DMA_CAP_PTP:
142 desc_idx <<= 1;
143 break;
144 case HW_DMA_CAP_64B_PTP:
145 desc_idx *= 3;
146 break;
147 default:
148 break;
149 }
150 #endif
151 return desc_idx;
152 }
154 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
155 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
156 {
157 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
158 return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
159 return NULL;
160 }
161 #endif
163 /* Ring buffer accessors */
164 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
165 {
166 return index & (bp->tx_ring_size - 1);
167 }
169 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
170 unsigned int index)
171 {
172 index = macb_tx_ring_wrap(queue->bp, index);
173 index = macb_adj_dma_desc_idx(queue->bp, index);
174 return &queue->tx_ring[index];
175 }
177 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
178 unsigned int index)
179 {
180 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
181 }
183 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
184 {
185 dma_addr_t offset;
187 offset = macb_tx_ring_wrap(queue->bp, index) *
188 macb_dma_desc_get_size(queue->bp);
190 return queue->tx_ring_dma + offset;
191 }
193 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
194 {
195 return index & (bp->rx_ring_size - 1);
196 }
198 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
199 {
200 index = macb_rx_ring_wrap(queue->bp, index);
201 index = macb_adj_dma_desc_idx(queue->bp, index);
202 return &queue->rx_ring[index];
203 }
205 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
206 {
207 return queue->rx_buffers + queue->bp->rx_buffer_size *
208 macb_rx_ring_wrap(queue->bp, index);
209 }
211 /* I/O accessors */
212 static u32 hw_readl_native(struct macb *bp, int offset)
213 {
214 return __raw_readl(bp->regs + offset);
215 }
217 static void hw_writel_native(struct macb *bp, int offset, u32 value)
218 {
219 __raw_writel(value, bp->regs + offset);
220 }
222 static u32 hw_readl(struct macb *bp, int offset)
223 {
224 return readl_relaxed(bp->regs + offset);
225 }
227 static void hw_writel(struct macb *bp, int offset, u32 value)
228 {
229 writel_relaxed(value, bp->regs + offset);
230 }
232 /* Find the CPU endianness by using the loopback bit of NCR register. When the
233 * CPU is in big endian we need to program swapped mode for management
234 * descriptor access.
235 */
236 static bool hw_is_native_io(void __iomem *addr)
237 {
238 u32 value = MACB_BIT(LLB);
240 __raw_writel(value, addr + MACB_NCR);
241 value = __raw_readl(addr + MACB_NCR);
243 /* Write 0 back to disable everything */
244 __raw_writel(0, addr + MACB_NCR);
246 return value == MACB_BIT(LLB);
247 }
249 static bool hw_is_gem(void __iomem *addr, bool native_io)
250 {
251 u32 id;
253 if (native_io)
254 id = __raw_readl(addr + MACB_MID);
255 else
256 id = readl_relaxed(addr + MACB_MID);
258 return MACB_BFEXT(IDNUM, id) >= 0x2;
259 }
261 static void macb_set_hwaddr(struct macb *bp)
262 {
263 u32 bottom;
264 u16 top;
266 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
267 macb_or_gem_writel(bp, SA1B, bottom);
268 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
269 macb_or_gem_writel(bp, SA1T, top);
271 /* Clear unused address register sets */
272 macb_or_gem_writel(bp, SA2B, 0);
273 macb_or_gem_writel(bp, SA2T, 0);
274 macb_or_gem_writel(bp, SA3B, 0);
275 macb_or_gem_writel(bp, SA3T, 0);
276 macb_or_gem_writel(bp, SA4B, 0);
277 macb_or_gem_writel(bp, SA4T, 0);
278 }
280 static void macb_get_hwaddr(struct macb *bp)
281 {
282 struct macb_platform_data *pdata;
283 u32 bottom;
284 u16 top;
285 u8 addr[6];
286 int i;
288 pdata = dev_get_platdata(&bp->pdev->dev);
290 /* Check all 4 address register for valid address */
291 for (i = 0; i < 4; i++) {
292 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
293 top = macb_or_gem_readl(bp, SA1T + i * 8);
295 if (pdata && pdata->rev_eth_addr) {
296 addr[5] = bottom & 0xff;
297 addr[4] = (bottom >> 8) & 0xff;
298 addr[3] = (bottom >> 16) & 0xff;
299 addr[2] = (bottom >> 24) & 0xff;
300 addr[1] = top & 0xff;
301 addr[0] = (top & 0xff00) >> 8;
302 } else {
303 addr[0] = bottom & 0xff;
304 addr[1] = (bottom >> 8) & 0xff;
305 addr[2] = (bottom >> 16) & 0xff;
306 addr[3] = (bottom >> 24) & 0xff;
307 addr[4] = top & 0xff;
308 addr[5] = (top >> 8) & 0xff;
309 }
311 if (is_valid_ether_addr(addr)) {
312 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
313 return;
314 }
315 }
317 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
318 eth_hw_addr_random(bp->dev);
319 }
321 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
322 {
323 struct macb *bp = bus->priv;
324 int value;
326 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
327 | MACB_BF(RW, MACB_MAN_READ)
328 | MACB_BF(PHYA, mii_id)
329 | MACB_BF(REGA, regnum)
330 | MACB_BF(CODE, MACB_MAN_CODE)));
332 /* wait for end of transfer */
333 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
334 cpu_relax();
336 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
338 return value;
339 }
341 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
342 u16 value)
343 {
344 struct macb *bp = bus->priv;
346 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
347 | MACB_BF(RW, MACB_MAN_WRITE)
348 | MACB_BF(PHYA, mii_id)
349 | MACB_BF(REGA, regnum)
350 | MACB_BF(CODE, MACB_MAN_CODE)
351 | MACB_BF(DATA, value)));
353 /* wait for end of transfer */
354 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
355 cpu_relax();
357 return 0;
358 }
360 /**
361 * macb_set_tx_clk() - Set a clock to a new frequency
362 * @clk Pointer to the clock to change
363 * @rate New frequency in Hz
364 * @dev Pointer to the struct net_device
365 */
366 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
367 {
368 long ferr, rate, rate_rounded;
370 if (!clk)
371 return;
373 switch (speed) {
374 case SPEED_10:
375 rate = 2500000;
376 break;
377 case SPEED_100:
378 rate = 25000000;
379 break;
380 case SPEED_1000:
381 rate = 125000000;
382 break;
383 default:
384 return;
385 }
387 rate_rounded = clk_round_rate(clk, rate);
388 if (rate_rounded < 0)
389 return;
391 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
392 * is not satisfied.
393 */
394 ferr = abs(rate_rounded - rate);
395 ferr = DIV_ROUND_UP(ferr, rate / 100000);
396 if (ferr > 5)
397 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
398 rate);
400 if (clk_set_rate(clk, rate_rounded))
401 netdev_err(dev, "adjusting tx_clk failed.\n");
402 }
404 static void macb_handle_link_change(struct net_device *dev)
405 {
406 struct macb *bp = netdev_priv(dev);
407 struct phy_device *phydev = dev->phydev;
408 unsigned long flags;
409 int status_change = 0;
411 spin_lock_irqsave(&bp->lock, flags);
413 if (phydev->link) {
414 if ((bp->speed != phydev->speed) ||
415 (bp->duplex != phydev->duplex)) {
416 u32 reg;
418 reg = macb_readl(bp, NCFGR);
419 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
420 if (macb_is_gem(bp))
421 reg &= ~GEM_BIT(GBE);
423 if (phydev->duplex)
424 reg |= MACB_BIT(FD);
425 if (phydev->speed == SPEED_100)
426 reg |= MACB_BIT(SPD);
427 if (phydev->speed == SPEED_1000 &&
428 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
429 reg |= GEM_BIT(GBE);
431 macb_or_gem_writel(bp, NCFGR, reg);
433 bp->speed = phydev->speed;
434 bp->duplex = phydev->duplex;
435 status_change = 1;
436 }
437 }
439 if (phydev->link != bp->link) {
440 if (!phydev->link) {
441 bp->speed = 0;
442 bp->duplex = -1;
443 }
444 bp->link = phydev->link;
446 status_change = 1;
447 }
449 spin_unlock_irqrestore(&bp->lock, flags);
451 if (status_change) {
452 if (phydev->link) {
453 /* Update the TX clock rate if and only if the link is
454 * up and there has been a link change.
455 */
456 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
458 netif_carrier_on(dev);
459 netdev_info(dev, "link up (%d/%s)\n",
460 phydev->speed,
461 phydev->duplex == DUPLEX_FULL ?
462 "Full" : "Half");
463 } else {
464 netif_carrier_off(dev);
465 netdev_info(dev, "link down\n");
466 }
467 }
468 }
470 /* based on au1000_eth. c*/
471 static int macb_mii_probe(struct net_device *dev)
472 {
473 struct macb *bp = netdev_priv(dev);
474 struct macb_platform_data *pdata;
475 struct phy_device *phydev;
476 struct device_node *np;
477 int phy_irq, ret, i;
479 pdata = dev_get_platdata(&bp->pdev->dev);
480 np = bp->pdev->dev.of_node;
481 ret = 0;
483 if (np) {
484 if (of_phy_is_fixed_link(np)) {
485 bp->phy_node = of_node_get(np);
486 } else {
487 bp->phy_node = of_parse_phandle(np, "phy-handle", 0);
488 /* fallback to standard phy registration if no
489 * phy-handle was found nor any phy found during
490 * dt phy registration
491 */
492 if (!bp->phy_node && !phy_find_first(bp->mii_bus)) {
493 for (i = 0; i < PHY_MAX_ADDR; i++) {
494 struct phy_device *phydev;
496 phydev = mdiobus_scan(bp->mii_bus, i);
497 if (IS_ERR(phydev) &&
498 PTR_ERR(phydev) != -ENODEV) {
499 ret = PTR_ERR(phydev);
500 break;
501 }
502 }
504 if (ret)
505 return -ENODEV;
506 }
507 }
508 }
510 if (bp->phy_node) {
511 phydev = of_phy_connect(dev, bp->phy_node,
512 &macb_handle_link_change, 0,
513 bp->phy_interface);
514 if (!phydev)
515 return -ENODEV;
516 } else {
517 phydev = phy_find_first(bp->mii_bus);
518 if (!phydev) {
519 netdev_err(dev, "no PHY found\n");
520 return -ENXIO;
521 }
523 if (pdata) {
524 if (gpio_is_valid(pdata->phy_irq_pin)) {
525 ret = devm_gpio_request(&bp->pdev->dev,
526 pdata->phy_irq_pin, "phy int");
527 if (!ret) {
528 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
529 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
530 }
531 } else {
532 phydev->irq = PHY_POLL;
533 }
534 }
536 /* attach the mac to the phy */
537 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
538 bp->phy_interface);
539 if (ret) {
540 netdev_err(dev, "Could not attach to PHY\n");
541 return ret;
542 }
543 }
545 /* mask with MAC supported features */
546 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
547 phydev->supported &= PHY_GBIT_FEATURES;
548 else
549 phydev->supported &= PHY_BASIC_FEATURES;
551 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
552 phydev->supported &= ~SUPPORTED_1000baseT_Half;
554 phydev->advertising = phydev->supported;
556 bp->link = 0;
557 bp->speed = 0;
558 bp->duplex = -1;
560 return 0;
561 }
563 static int macb_mii_init(struct macb *bp)
564 {
565 struct macb_platform_data *pdata;
566 struct device_node *np;
567 int err = -ENXIO;
569 /* Enable management port */
570 macb_writel(bp, NCR, MACB_BIT(MPE));
572 bp->mii_bus = mdiobus_alloc();
573 if (!bp->mii_bus) {
574 err = -ENOMEM;
575 goto err_out;
576 }
578 bp->mii_bus->name = "MACB_mii_bus";
579 bp->mii_bus->read = &macb_mdio_read;
580 bp->mii_bus->write = &macb_mdio_write;
581 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
582 bp->pdev->name, bp->pdev->id);
583 bp->mii_bus->priv = bp;
584 bp->mii_bus->parent = &bp->pdev->dev;
585 pdata = dev_get_platdata(&bp->pdev->dev);
587 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
589 np = bp->pdev->dev.of_node;
590 if (np && of_phy_is_fixed_link(np)) {
591 if (of_phy_register_fixed_link(np) < 0) {
592 dev_err(&bp->pdev->dev,
593 "broken fixed-link specification %pOF\n", np);
594 goto err_out_free_mdiobus;
595 }
597 err = mdiobus_register(bp->mii_bus);
598 } else {
599 if (pdata)
600 bp->mii_bus->phy_mask = pdata->phy_mask;
602 err = of_mdiobus_register(bp->mii_bus, np);
603 }
605 if (err)
606 goto err_out_free_fixed_link;
608 err = macb_mii_probe(bp->dev);
609 if (err)
610 goto err_out_unregister_bus;
612 return 0;
614 err_out_unregister_bus:
615 mdiobus_unregister(bp->mii_bus);
616 err_out_free_fixed_link:
617 if (np && of_phy_is_fixed_link(np))
618 of_phy_deregister_fixed_link(np);
619 err_out_free_mdiobus:
620 of_node_put(bp->phy_node);
621 mdiobus_free(bp->mii_bus);
622 err_out:
623 return err;
624 }
626 static void macb_update_stats(struct macb *bp)
627 {
628 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
629 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
630 int offset = MACB_PFR;
632 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
634 for (; p < end; p++, offset += 4)
635 *p += bp->macb_reg_readl(bp, offset);
636 }
638 static int macb_halt_tx(struct macb *bp)
639 {
640 unsigned long halt_time, timeout;
641 u32 status;
643 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
645 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
646 do {
647 halt_time = jiffies;
648 status = macb_readl(bp, TSR);
649 if (!(status & MACB_BIT(TGO)))
650 return 0;
652 udelay(250);
653 } while (time_before(halt_time, timeout));
655 return -ETIMEDOUT;
656 }
658 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
659 {
660 if (tx_skb->mapping) {
661 if (tx_skb->mapped_as_page)
662 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
663 tx_skb->size, DMA_TO_DEVICE);
664 else
665 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
666 tx_skb->size, DMA_TO_DEVICE);
667 tx_skb->mapping = 0;
668 }
670 if (tx_skb->skb) {
671 dev_kfree_skb_any(tx_skb->skb);
672 tx_skb->skb = NULL;
673 }
674 }
676 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
677 {
678 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
679 struct macb_dma_desc_64 *desc_64;
681 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
682 desc_64 = macb_64b_desc(bp, desc);
683 desc_64->addrh = upper_32_bits(addr);
684 }
685 #endif
686 desc->addr = lower_32_bits(addr);
687 }
689 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
690 {
691 dma_addr_t addr = 0;
692 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
693 struct macb_dma_desc_64 *desc_64;
695 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
696 desc_64 = macb_64b_desc(bp, desc);
697 addr = ((u64)(desc_64->addrh) << 32);
698 }
699 #endif
700 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
701 return addr;
702 }
704 static void macb_tx_error_task(struct work_struct *work)
705 {
706 struct macb_queue *queue = container_of(work, struct macb_queue,
707 tx_error_task);
708 struct macb *bp = queue->bp;
709 struct macb_tx_skb *tx_skb;
710 struct macb_dma_desc *desc;
711 struct sk_buff *skb;
712 unsigned int tail;
713 unsigned long flags;
715 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
716 (unsigned int)(queue - bp->queues),
717 queue->tx_tail, queue->tx_head);
719 /* Prevent the queue IRQ handlers from running: each of them may call
720 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
721 * As explained below, we have to halt the transmission before updating
722 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
723 * network engine about the macb/gem being halted.
724 */
725 spin_lock_irqsave(&bp->lock, flags);
727 /* Make sure nobody is trying to queue up new packets */
728 netif_tx_stop_all_queues(bp->dev);
730 /* Stop transmission now
731 * (in case we have just queued new packets)
732 * macb/gem must be halted to write TBQP register
733 */
734 if (macb_halt_tx(bp))
735 /* Just complain for now, reinitializing TX path can be good */
736 netdev_err(bp->dev, "BUG: halt tx timed out\n");
738 /* Treat frames in TX queue including the ones that caused the error.
739 * Free transmit buffers in upper layer.
740 */
741 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
742 u32 ctrl;
744 desc = macb_tx_desc(queue, tail);
745 ctrl = desc->ctrl;
746 tx_skb = macb_tx_skb(queue, tail);
747 skb = tx_skb->skb;
749 if (ctrl & MACB_BIT(TX_USED)) {
750 /* skb is set for the last buffer of the frame */
751 while (!skb) {
752 macb_tx_unmap(bp, tx_skb);
753 tail++;
754 tx_skb = macb_tx_skb(queue, tail);
755 skb = tx_skb->skb;
756 }
758 /* ctrl still refers to the first buffer descriptor
759 * since it's the only one written back by the hardware
760 */
761 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
762 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
763 macb_tx_ring_wrap(bp, tail),
764 skb->data);
765 bp->dev->stats.tx_packets++;
766 queue->stats.tx_packets++;
767 bp->dev->stats.tx_bytes += skb->len;
768 queue->stats.tx_bytes += skb->len;
769 }
770 } else {
771 /* "Buffers exhausted mid-frame" errors may only happen
772 * if the driver is buggy, so complain loudly about
773 * those. Statistics are updated by hardware.
774 */
775 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
776 netdev_err(bp->dev,
777 "BUG: TX buffers exhausted mid-frame\n");
779 desc->ctrl = ctrl | MACB_BIT(TX_USED);
780 }
782 macb_tx_unmap(bp, tx_skb);
783 }
785 /* Set end of TX queue */
786 desc = macb_tx_desc(queue, 0);
787 macb_set_addr(bp, desc, 0);
788 desc->ctrl = MACB_BIT(TX_USED);
790 /* Make descriptor updates visible to hardware */
791 wmb();
793 /* Reinitialize the TX desc queue */
794 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
795 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
796 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
797 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
798 #endif
799 /* Make TX ring reflect state of hardware */
800 queue->tx_head = 0;
801 queue->tx_tail = 0;
803 /* Housework before enabling TX IRQ */
804 macb_writel(bp, TSR, macb_readl(bp, TSR));
805 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
807 /* Now we are ready to start transmission again */
808 netif_tx_start_all_queues(bp->dev);
809 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
811 spin_unlock_irqrestore(&bp->lock, flags);
812 }
814 static void macb_tx_interrupt(struct macb_queue *queue)
815 {
816 unsigned int tail;
817 unsigned int head;
818 u32 status;
819 struct macb *bp = queue->bp;
820 u16 queue_index = queue - bp->queues;
822 status = macb_readl(bp, TSR);
823 macb_writel(bp, TSR, status);
825 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
826 queue_writel(queue, ISR, MACB_BIT(TCOMP));
828 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
829 (unsigned long)status);
831 head = queue->tx_head;
832 for (tail = queue->tx_tail; tail != head; tail++) {
833 struct macb_tx_skb *tx_skb;
834 struct sk_buff *skb;
835 struct macb_dma_desc *desc;
836 u32 ctrl;
838 desc = macb_tx_desc(queue, tail);
840 /* Make hw descriptor updates visible to CPU */
841 rmb();
843 ctrl = desc->ctrl;
845 /* TX_USED bit is only set by hardware on the very first buffer
846 * descriptor of the transmitted frame.
847 */
848 if (!(ctrl & MACB_BIT(TX_USED)))
849 break;
851 /* Process all buffers of the current transmitted frame */
852 for (;; tail++) {
853 tx_skb = macb_tx_skb(queue, tail);
854 skb = tx_skb->skb;
856 /* First, update TX stats if needed */
857 if (skb) {
858 if (gem_ptp_do_txstamp(queue, skb, desc) == 0) {
859 /* skb now belongs to timestamp buffer
860 * and will be removed later
861 */
862 tx_skb->skb = NULL;
863 }
864 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
865 macb_tx_ring_wrap(bp, tail),
866 skb->data);
867 bp->dev->stats.tx_packets++;
868 queue->stats.tx_packets++;
869 bp->dev->stats.tx_bytes += skb->len;
870 queue->stats.tx_bytes += skb->len;
871 }
873 /* Now we can safely release resources */
874 macb_tx_unmap(bp, tx_skb);
876 /* skb is set only for the last buffer of the frame.
877 * WARNING: at this point skb has been freed by
878 * macb_tx_unmap().
879 */
880 if (skb)
881 break;
882 }
883 }
885 queue->tx_tail = tail;
886 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
887 CIRC_CNT(queue->tx_head, queue->tx_tail,
888 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
889 netif_wake_subqueue(bp->dev, queue_index);
890 }
892 static void gem_rx_refill(struct macb_queue *queue)
893 {
894 unsigned int entry;
895 struct sk_buff *skb;
896 dma_addr_t paddr;
897 struct macb *bp = queue->bp;
898 struct macb_dma_desc *desc;
900 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
901 bp->rx_ring_size) > 0) {
902 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
904 /* Make hw descriptor updates visible to CPU */
905 rmb();
907 queue->rx_prepared_head++;
908 desc = macb_rx_desc(queue, entry);
910 if (!queue->rx_skbuff[entry]) {
911 /* allocate sk_buff for this free entry in ring */
912 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
913 if (unlikely(!skb)) {
914 netdev_err(bp->dev,
915 "Unable to allocate sk_buff\n");
916 break;
917 }
919 /* now fill corresponding descriptor entry */
920 paddr = dma_map_single(&bp->pdev->dev, skb->data,
921 bp->rx_buffer_size,
922 DMA_FROM_DEVICE);
923 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
924 dev_kfree_skb(skb);
925 break;
926 }
928 queue->rx_skbuff[entry] = skb;
930 if (entry == bp->rx_ring_size - 1)
931 paddr |= MACB_BIT(RX_WRAP);
932 macb_set_addr(bp, desc, paddr);
933 desc->ctrl = 0;
935 /* properly align Ethernet header */
936 skb_reserve(skb, NET_IP_ALIGN);
937 } else {
938 desc->addr &= ~MACB_BIT(RX_USED);
939 desc->ctrl = 0;
940 }
941 }
943 /* Make descriptor updates visible to hardware */
944 wmb();
946 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
947 queue, queue->rx_prepared_head, queue->rx_tail);
948 }
950 /* Mark DMA descriptors from begin up to and not including end as unused */
951 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
952 unsigned int end)
953 {
954 unsigned int frag;
956 for (frag = begin; frag != end; frag++) {
957 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
959 desc->addr &= ~MACB_BIT(RX_USED);
960 }
962 /* Make descriptor updates visible to hardware */
963 wmb();
965 /* When this happens, the hardware stats registers for
966 * whatever caused this is updated, so we don't have to record
967 * anything.
968 */
969 }
971 static int gem_rx(struct macb_queue *queue, int budget)
972 {
973 struct macb *bp = queue->bp;
974 unsigned int len;
975 unsigned int entry;
976 struct sk_buff *skb;
977 struct macb_dma_desc *desc;
978 int count = 0;
980 while (count < budget) {
981 u32 ctrl;
982 dma_addr_t addr;
983 bool rxused;
985 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
986 desc = macb_rx_desc(queue, entry);
988 /* Make hw descriptor updates visible to CPU */
989 rmb();
991 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
992 addr = macb_get_addr(bp, desc);
993 ctrl = desc->ctrl;
995 if (!rxused)
996 break;
998 queue->rx_tail++;
999 count++;
1001 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1002 netdev_err(bp->dev,
1003 "not whole frame pointed by descriptor\n");
1004 bp->dev->stats.rx_dropped++;
1005 queue->stats.rx_dropped++;
1006 break;
1007 }
1008 skb = queue->rx_skbuff[entry];
1009 if (unlikely(!skb)) {
1010 netdev_err(bp->dev,
1011 "inconsistent Rx descriptor chain\n");
1012 bp->dev->stats.rx_dropped++;
1013 queue->stats.rx_dropped++;
1014 break;
1015 }
1016 /* now everything is ready for receiving packet */
1017 queue->rx_skbuff[entry] = NULL;
1018 len = ctrl & bp->rx_frm_len_mask;
1020 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1022 skb_put(skb, len);
1023 dma_unmap_single(&bp->pdev->dev, addr,
1024 bp->rx_buffer_size, DMA_FROM_DEVICE);
1026 skb->protocol = eth_type_trans(skb, bp->dev);
1027 skb_checksum_none_assert(skb);
1028 if (bp->dev->features & NETIF_F_RXCSUM &&
1029 !(bp->dev->flags & IFF_PROMISC) &&
1030 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1031 skb->ip_summed = CHECKSUM_UNNECESSARY;
1033 bp->dev->stats.rx_packets++;
1034 queue->stats.rx_packets++;
1035 bp->dev->stats.rx_bytes += skb->len;
1036 queue->stats.rx_bytes += skb->len;
1038 gem_ptp_do_rxstamp(bp, skb, desc);
1040 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1041 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1042 skb->len, skb->csum);
1043 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1044 skb_mac_header(skb), 16, true);
1045 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1046 skb->data, 32, true);
1047 #endif
1049 netif_receive_skb(skb);
1050 }
1052 gem_rx_refill(queue);
1054 return count;
1055 }
1057 static int macb_rx_frame(struct macb_queue *queue, unsigned int first_frag,
1058 unsigned int last_frag)
1059 {
1060 unsigned int len;
1061 unsigned int frag;
1062 unsigned int offset;
1063 struct sk_buff *skb;
1064 struct macb_dma_desc *desc;
1065 struct macb *bp = queue->bp;
1067 desc = macb_rx_desc(queue, last_frag);
1068 len = desc->ctrl & bp->rx_frm_len_mask;
1070 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1071 macb_rx_ring_wrap(bp, first_frag),
1072 macb_rx_ring_wrap(bp, last_frag), len);
1074 /* The ethernet header starts NET_IP_ALIGN bytes into the
1075 * first buffer. Since the header is 14 bytes, this makes the
1076 * payload word-aligned.
1077 *
1078 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1079 * the two padding bytes into the skb so that we avoid hitting
1080 * the slowpath in memcpy(), and pull them off afterwards.
1081 */
1082 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1083 if (!skb) {
1084 bp->dev->stats.rx_dropped++;
1085 for (frag = first_frag; ; frag++) {
1086 desc = macb_rx_desc(queue, frag);
1087 desc->addr &= ~MACB_BIT(RX_USED);
1088 if (frag == last_frag)
1089 break;
1090 }
1092 /* Make descriptor updates visible to hardware */
1093 wmb();
1095 return 1;
1096 }
1098 offset = 0;
1099 len += NET_IP_ALIGN;
1100 skb_checksum_none_assert(skb);
1101 skb_put(skb, len);
1103 for (frag = first_frag; ; frag++) {
1104 unsigned int frag_len = bp->rx_buffer_size;
1106 if (offset + frag_len > len) {
1107 if (unlikely(frag != last_frag)) {
1108 dev_kfree_skb_any(skb);
1109 return -1;
1110 }
1111 frag_len = len - offset;
1112 }
1113 skb_copy_to_linear_data_offset(skb, offset,
1114 macb_rx_buffer(queue, frag),
1115 frag_len);
1116 offset += bp->rx_buffer_size;
1117 desc = macb_rx_desc(queue, frag);
1118 desc->addr &= ~MACB_BIT(RX_USED);
1120 if (frag == last_frag)
1121 break;
1122 }
1124 /* Make descriptor updates visible to hardware */
1125 wmb();
1127 __skb_pull(skb, NET_IP_ALIGN);
1128 skb->protocol = eth_type_trans(skb, bp->dev);
1130 bp->dev->stats.rx_packets++;
1131 bp->dev->stats.rx_bytes += skb->len;
1132 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1133 skb->len, skb->csum);
1134 netif_receive_skb(skb);
1136 return 0;
1137 }
1139 static inline void macb_init_rx_ring(struct macb_queue *queue)
1140 {
1141 struct macb *bp = queue->bp;
1142 dma_addr_t addr;
1143 struct macb_dma_desc *desc = NULL;
1144 int i;
1146 addr = queue->rx_buffers_dma;
1147 for (i = 0; i < bp->rx_ring_size; i++) {
1148 desc = macb_rx_desc(queue, i);
1149 macb_set_addr(bp, desc, addr);
1150 desc->ctrl = 0;
1151 addr += bp->rx_buffer_size;
1152 }
1153 desc->addr |= MACB_BIT(RX_WRAP);
1154 queue->rx_tail = 0;
1155 }
1157 static int macb_rx(struct macb_queue *queue, int budget)
1158 {
1159 struct macb *bp = queue->bp;
1160 bool reset_rx_queue = false;
1161 int received = 0;
1162 unsigned int tail;
1163 int first_frag = -1;
1165 for (tail = queue->rx_tail; budget > 0; tail++) {
1166 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1167 u32 ctrl;
1169 /* Make hw descriptor updates visible to CPU */
1170 rmb();
1172 ctrl = desc->ctrl;
1174 if (!(desc->addr & MACB_BIT(RX_USED)))
1175 break;
1177 if (ctrl & MACB_BIT(RX_SOF)) {
1178 if (first_frag != -1)
1179 discard_partial_frame(queue, first_frag, tail);
1180 first_frag = tail;
1181 }
1183 if (ctrl & MACB_BIT(RX_EOF)) {
1184 int dropped;
1186 if (unlikely(first_frag == -1)) {
1187 reset_rx_queue = true;
1188 continue;
1189 }
1191 dropped = macb_rx_frame(queue, first_frag, tail);
1192 first_frag = -1;
1193 if (unlikely(dropped < 0)) {
1194 reset_rx_queue = true;
1195 continue;
1196 }
1197 if (!dropped) {
1198 received++;
1199 budget--;
1200 }
1201 }
1202 }
1204 if (unlikely(reset_rx_queue)) {
1205 unsigned long flags;
1206 u32 ctrl;
1208 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1210 spin_lock_irqsave(&bp->lock, flags);
1212 ctrl = macb_readl(bp, NCR);
1213 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1215 macb_init_rx_ring(queue);
1216 queue_writel(queue, RBQP, queue->rx_ring_dma);
1218 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1220 spin_unlock_irqrestore(&bp->lock, flags);
1221 return received;
1222 }
1224 if (first_frag != -1)
1225 queue->rx_tail = first_frag;
1226 else
1227 queue->rx_tail = tail;
1229 return received;
1230 }
1232 static int macb_poll(struct napi_struct *napi, int budget)
1233 {
1234 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1235 struct macb *bp = queue->bp;
1236 int work_done;
1237 u32 status;
1239 status = macb_readl(bp, RSR);
1240 macb_writel(bp, RSR, status);
1242 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1243 (unsigned long)status, budget);
1245 work_done = bp->macbgem_ops.mog_rx(queue, budget);
1246 if (work_done < budget) {
1247 napi_complete_done(napi, work_done);
1249 /* Packets received while interrupts were disabled */
1250 status = macb_readl(bp, RSR);
1251 if (status) {
1252 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1253 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1254 napi_reschedule(napi);
1255 } else {
1256 queue_writel(queue, IER, MACB_RX_INT_FLAGS);
1257 }
1258 }
1260 /* TODO: Handle errors */
1262 return work_done;
1263 }
1265 static void macb_hresp_error_task(unsigned long data)
1266 {
1267 struct macb *bp = (struct macb *)data;
1268 struct net_device *dev = bp->dev;
1269 struct macb_queue *queue = bp->queues;
1270 unsigned int q;
1271 u32 ctrl;
1273 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1274 queue_writel(queue, IDR, MACB_RX_INT_FLAGS |
1275 MACB_TX_INT_FLAGS |
1276 MACB_BIT(HRESP));
1277 }
1278 ctrl = macb_readl(bp, NCR);
1279 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1280 macb_writel(bp, NCR, ctrl);
1282 netif_tx_stop_all_queues(dev);
1283 netif_carrier_off(dev);
1285 bp->macbgem_ops.mog_init_rings(bp);
1287 /* Initialize TX and RX buffers */
1288 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1289 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
1290 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1291 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1292 queue_writel(queue, RBQPH,
1293 upper_32_bits(queue->rx_ring_dma));
1294 #endif
1295 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1296 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1297 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1298 queue_writel(queue, TBQPH,
1299 upper_32_bits(queue->tx_ring_dma));
1300 #endif
1302 /* Enable interrupts */
1303 queue_writel(queue, IER,
1304 MACB_RX_INT_FLAGS |
1305 MACB_TX_INT_FLAGS |
1306 MACB_BIT(HRESP));
1307 }
1309 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1310 macb_writel(bp, NCR, ctrl);
1312 netif_carrier_on(dev);
1313 netif_tx_start_all_queues(dev);
1314 }
1316 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1317 {
1318 struct macb_queue *queue = dev_id;
1319 struct macb *bp = queue->bp;
1320 struct net_device *dev = bp->dev;
1321 u32 status, ctrl;
1323 status = queue_readl(queue, ISR);
1325 if (unlikely(!status))
1326 return IRQ_NONE;
1328 spin_lock(&bp->lock);
1330 while (status) {
1331 /* close possible race with dev_close */
1332 if (unlikely(!netif_running(dev))) {
1333 queue_writel(queue, IDR, -1);
1334 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1335 queue_writel(queue, ISR, -1);
1336 break;
1337 }
1339 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1340 (unsigned int)(queue - bp->queues),
1341 (unsigned long)status);
1343 if (status & MACB_RX_INT_FLAGS) {
1344 /* There's no point taking any more interrupts
1345 * until we have processed the buffers. The
1346 * scheduling call may fail if the poll routine
1347 * is already scheduled, so disable interrupts
1348 * now.
1349 */
1350 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1351 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1352 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1354 if (napi_schedule_prep(&queue->napi)) {
1355 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1356 __napi_schedule(&queue->napi);
1357 }
1358 }
1360 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1361 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1362 schedule_work(&queue->tx_error_task);
1364 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1365 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1367 break;
1368 }
1370 if (status & MACB_BIT(TCOMP))
1371 macb_tx_interrupt(queue);
1373 /* Link change detection isn't possible with RMII, so we'll
1374 * add that if/when we get our hands on a full-blown MII PHY.
1375 */
1377 /* There is a hardware issue under heavy load where DMA can
1378 * stop, this causes endless "used buffer descriptor read"
1379 * interrupts but it can be cleared by re-enabling RX. See
1380 * the at91 manual, section 41.3.1 or the Zynq manual
1381 * section 16.7.4 for details.
1382 */
1383 if (status & MACB_BIT(RXUBR)) {
1384 ctrl = macb_readl(bp, NCR);
1385 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1386 wmb();
1387 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1389 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1390 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1391 }
1393 if (status & MACB_BIT(ISR_ROVR)) {
1394 /* We missed at least one packet */
1395 if (macb_is_gem(bp))
1396 bp->hw_stats.gem.rx_overruns++;
1397 else
1398 bp->hw_stats.macb.rx_overruns++;
1400 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1401 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1402 }
1404 if (status & MACB_BIT(HRESP)) {
1405 tasklet_schedule(&bp->hresp_err_tasklet);
1406 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1408 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1409 queue_writel(queue, ISR, MACB_BIT(HRESP));
1410 }
1411 status = queue_readl(queue, ISR);
1412 }
1414 spin_unlock(&bp->lock);
1416 return IRQ_HANDLED;
1417 }
1419 #ifdef CONFIG_NET_POLL_CONTROLLER
1420 /* Polling receive - used by netconsole and other diagnostic tools
1421 * to allow network i/o with interrupts disabled.
1422 */
1423 static void macb_poll_controller(struct net_device *dev)
1424 {
1425 struct macb *bp = netdev_priv(dev);
1426 struct macb_queue *queue;
1427 unsigned long flags;
1428 unsigned int q;
1430 local_irq_save(flags);
1431 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1432 macb_interrupt(dev->irq, queue);
1433 local_irq_restore(flags);
1434 }
1435 #endif
1437 static unsigned int macb_tx_map(struct macb *bp,
1438 struct macb_queue *queue,
1439 struct sk_buff *skb,
1440 unsigned int hdrlen)
1441 {
1442 dma_addr_t mapping;
1443 unsigned int len, entry, i, tx_head = queue->tx_head;
1444 struct macb_tx_skb *tx_skb = NULL;
1445 struct macb_dma_desc *desc;
1446 unsigned int offset, size, count = 0;
1447 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1448 unsigned int eof = 1, mss_mfs = 0;
1449 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1451 /* LSO */
1452 if (skb_shinfo(skb)->gso_size != 0) {
1453 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1454 /* UDP - UFO */
1455 lso_ctrl = MACB_LSO_UFO_ENABLE;
1456 else
1457 /* TCP - TSO */
1458 lso_ctrl = MACB_LSO_TSO_ENABLE;
1459 }
1461 /* First, map non-paged data */
1462 len = skb_headlen(skb);
1464 /* first buffer length */
1465 size = hdrlen;
1467 offset = 0;
1468 while (len) {
1469 entry = macb_tx_ring_wrap(bp, tx_head);
1470 tx_skb = &queue->tx_skb[entry];
1472 mapping = dma_map_single(&bp->pdev->dev,
1473 skb->data + offset,
1474 size, DMA_TO_DEVICE);
1475 if (dma_mapping_error(&bp->pdev->dev, mapping))
1476 goto dma_error;
1478 /* Save info to properly release resources */
1479 tx_skb->skb = NULL;
1480 tx_skb->mapping = mapping;
1481 tx_skb->size = size;
1482 tx_skb->mapped_as_page = false;
1484 len -= size;
1485 offset += size;
1486 count++;
1487 tx_head++;
1489 size = min(len, bp->max_tx_length);
1490 }
1492 /* Then, map paged data from fragments */
1493 for (f = 0; f < nr_frags; f++) {
1494 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1496 len = skb_frag_size(frag);
1497 offset = 0;
1498 while (len) {
1499 size = min(len, bp->max_tx_length);
1500 entry = macb_tx_ring_wrap(bp, tx_head);
1501 tx_skb = &queue->tx_skb[entry];
1503 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1504 offset, size, DMA_TO_DEVICE);
1505 if (dma_mapping_error(&bp->pdev->dev, mapping))
1506 goto dma_error;
1508 /* Save info to properly release resources */
1509 tx_skb->skb = NULL;
1510 tx_skb->mapping = mapping;
1511 tx_skb->size = size;
1512 tx_skb->mapped_as_page = true;
1514 len -= size;
1515 offset += size;
1516 count++;
1517 tx_head++;
1518 }
1519 }
1521 /* Should never happen */
1522 if (unlikely(!tx_skb)) {
1523 netdev_err(bp->dev, "BUG! empty skb!\n");
1524 return 0;
1525 }
1527 /* This is the last buffer of the frame: save socket buffer */
1528 tx_skb->skb = skb;
1530 /* Update TX ring: update buffer descriptors in reverse order
1531 * to avoid race condition
1532 */
1534 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1535 * to set the end of TX queue
1536 */
1537 i = tx_head;
1538 entry = macb_tx_ring_wrap(bp, i);
1539 ctrl = MACB_BIT(TX_USED);
1540 desc = macb_tx_desc(queue, entry);
1541 desc->ctrl = ctrl;
1543 if (lso_ctrl) {
1544 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1545 /* include header and FCS in value given to h/w */
1546 mss_mfs = skb_shinfo(skb)->gso_size +
1547 skb_transport_offset(skb) +
1548 ETH_FCS_LEN;
1549 else /* TSO */ {
1550 mss_mfs = skb_shinfo(skb)->gso_size;
1551 /* TCP Sequence Number Source Select
1552 * can be set only for TSO
1553 */
1554 seq_ctrl = 0;
1555 }
1556 }
1558 do {
1559 i--;
1560 entry = macb_tx_ring_wrap(bp, i);
1561 tx_skb = &queue->tx_skb[entry];
1562 desc = macb_tx_desc(queue, entry);
1564 ctrl = (u32)tx_skb->size;
1565 if (eof) {
1566 ctrl |= MACB_BIT(TX_LAST);
1567 eof = 0;
1568 }
1569 if (unlikely(entry == (bp->tx_ring_size - 1)))
1570 ctrl |= MACB_BIT(TX_WRAP);
1572 /* First descriptor is header descriptor */
1573 if (i == queue->tx_head) {
1574 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1575 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1576 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1577 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1578 ctrl |= MACB_BIT(TX_NOCRC);
1579 } else
1580 /* Only set MSS/MFS on payload descriptors
1581 * (second or later descriptor)
1582 */
1583 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1585 /* Set TX buffer descriptor */
1586 macb_set_addr(bp, desc, tx_skb->mapping);
1587 /* desc->addr must be visible to hardware before clearing
1588 * 'TX_USED' bit in desc->ctrl.
1589 */
1590 wmb();
1591 desc->ctrl = ctrl;
1592 } while (i != queue->tx_head);
1594 queue->tx_head = tx_head;
1596 return count;
1598 dma_error:
1599 netdev_err(bp->dev, "TX DMA map failed\n");
1601 for (i = queue->tx_head; i != tx_head; i++) {
1602 tx_skb = macb_tx_skb(queue, i);
1604 macb_tx_unmap(bp, tx_skb);
1605 }
1607 return 0;
1608 }
1610 static netdev_features_t macb_features_check(struct sk_buff *skb,
1611 struct net_device *dev,
1612 netdev_features_t features)
1613 {
1614 unsigned int nr_frags, f;
1615 unsigned int hdrlen;
1617 /* Validate LSO compatibility */
1619 /* there is only one buffer */
1620 if (!skb_is_nonlinear(skb))
1621 return features;
1623 /* length of header */
1624 hdrlen = skb_transport_offset(skb);
1625 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1626 hdrlen += tcp_hdrlen(skb);
1628 /* For LSO:
1629 * When software supplies two or more payload buffers all payload buffers
1630 * apart from the last must be a multiple of 8 bytes in size.
1631 */
1632 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1633 return features & ~MACB_NETIF_LSO;
1635 nr_frags = skb_shinfo(skb)->nr_frags;
1636 /* No need to check last fragment */
1637 nr_frags--;
1638 for (f = 0; f < nr_frags; f++) {
1639 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1641 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1642 return features & ~MACB_NETIF_LSO;
1643 }
1644 return features;
1645 }
1647 static inline int macb_clear_csum(struct sk_buff *skb)
1648 {
1649 /* no change for packets without checksum offloading */
1650 if (skb->ip_summed != CHECKSUM_PARTIAL)
1651 return 0;
1653 /* make sure we can modify the header */
1654 if (unlikely(skb_cow_head(skb, 0)))
1655 return -1;
1657 /* initialize checksum field
1658 * This is required - at least for Zynq, which otherwise calculates
1659 * wrong UDP header checksums for UDP packets with UDP data len <=2
1660 */
1661 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1662 return 0;
1663 }
1665 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1666 {
1667 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1668 int padlen = ETH_ZLEN - (*skb)->len;
1669 int headroom = skb_headroom(*skb);
1670 int tailroom = skb_tailroom(*skb);
1671 struct sk_buff *nskb;
1672 u32 fcs;
1674 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1675 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1676 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1677 return 0;
1679 if (padlen <= 0) {
1680 /* FCS could be appeded to tailroom. */
1681 if (tailroom >= ETH_FCS_LEN)
1682 goto add_fcs;
1683 /* FCS could be appeded by moving data to headroom. */
1684 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1685 padlen = 0;
1686 /* No room for FCS, need to reallocate skb. */
1687 else
1688 padlen = ETH_FCS_LEN - tailroom;
1689 } else {
1690 /* Add room for FCS. */
1691 padlen += ETH_FCS_LEN;
1692 }
1694 if (!cloned && headroom + tailroom >= padlen) {
1695 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1696 skb_set_tail_pointer(*skb, (*skb)->len);
1697 } else {
1698 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1699 if (!nskb)
1700 return -ENOMEM;
1702 dev_kfree_skb_any(*skb);
1703 *skb = nskb;
1704 }
1706 if (padlen) {
1707 if (padlen >= ETH_FCS_LEN)
1708 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1709 else
1710 skb_trim(*skb, ETH_FCS_LEN - padlen);
1711 }
1713 add_fcs:
1714 /* set FCS to packet */
1715 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1716 fcs = ~fcs;
1718 skb_put_u8(*skb, fcs & 0xff);
1719 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1720 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1721 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1723 return 0;
1724 }
1726 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1727 {
1728 u16 queue_index = skb_get_queue_mapping(skb);
1729 struct macb *bp = netdev_priv(dev);
1730 struct macb_queue *queue = &bp->queues[queue_index];
1731 unsigned long flags;
1732 unsigned int desc_cnt, nr_frags, frag_size, f;
1733 unsigned int hdrlen;
1734 bool is_lso, is_udp = 0;
1735 netdev_tx_t ret = NETDEV_TX_OK;
1737 if (macb_clear_csum(skb)) {
1738 dev_kfree_skb_any(skb);
1739 return ret;
1740 }
1742 if (macb_pad_and_fcs(&skb, dev)) {
1743 dev_kfree_skb_any(skb);
1744 return ret;
1745 }
1747 is_lso = (skb_shinfo(skb)->gso_size != 0);
1749 if (is_lso) {
1750 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1752 /* length of headers */
1753 if (is_udp)
1754 /* only queue eth + ip headers separately for UDP */
1755 hdrlen = skb_transport_offset(skb);
1756 else
1757 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1758 if (skb_headlen(skb) < hdrlen) {
1759 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1760 /* if this is required, would need to copy to single buffer */
1761 return NETDEV_TX_BUSY;
1762 }
1763 } else
1764 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1766 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1767 netdev_vdbg(bp->dev,
1768 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1769 queue_index, skb->len, skb->head, skb->data,
1770 skb_tail_pointer(skb), skb_end_pointer(skb));
1771 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1772 skb->data, 16, true);
1773 #endif
1775 /* Count how many TX buffer descriptors are needed to send this
1776 * socket buffer: skb fragments of jumbo frames may need to be
1777 * split into many buffer descriptors.
1778 */
1779 if (is_lso && (skb_headlen(skb) > hdrlen))
1780 /* extra header descriptor if also payload in first buffer */
1781 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1782 else
1783 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1784 nr_frags = skb_shinfo(skb)->nr_frags;
1785 for (f = 0; f < nr_frags; f++) {
1786 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1787 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1788 }
1790 spin_lock_irqsave(&bp->lock, flags);
1792 /* This is a hard error, log it. */
1793 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1794 bp->tx_ring_size) < desc_cnt) {
1795 netif_stop_subqueue(dev, queue_index);
1796 spin_unlock_irqrestore(&bp->lock, flags);
1797 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1798 queue->tx_head, queue->tx_tail);
1799 return NETDEV_TX_BUSY;
1800 }
1802 /* Map socket buffer for DMA transfer */
1803 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1804 dev_kfree_skb_any(skb);
1805 goto unlock;
1806 }
1808 /* Make newly initialized descriptor visible to hardware */
1809 wmb();
1810 skb_tx_timestamp(skb);
1812 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1814 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1815 netif_stop_subqueue(dev, queue_index);
1817 unlock:
1818 spin_unlock_irqrestore(&bp->lock, flags);
1820 return ret;
1821 }
1823 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1824 {
1825 if (!macb_is_gem(bp)) {
1826 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1827 } else {
1828 bp->rx_buffer_size = size;
1830 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1831 netdev_dbg(bp->dev,
1832 "RX buffer must be multiple of %d bytes, expanding\n",
1833 RX_BUFFER_MULTIPLE);
1834 bp->rx_buffer_size =
1835 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1836 }
1837 }
1839 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1840 bp->dev->mtu, bp->rx_buffer_size);
1841 }
1843 static void gem_free_rx_buffers(struct macb *bp)
1844 {
1845 struct sk_buff *skb;
1846 struct macb_dma_desc *desc;
1847 struct macb_queue *queue;
1848 dma_addr_t addr;
1849 unsigned int q;
1850 int i;
1852 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1853 if (!queue->rx_skbuff)
1854 continue;
1856 for (i = 0; i < bp->rx_ring_size; i++) {
1857 skb = queue->rx_skbuff[i];
1859 if (!skb)
1860 continue;
1862 desc = macb_rx_desc(queue, i);
1863 addr = macb_get_addr(bp, desc);
1865 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1866 DMA_FROM_DEVICE);
1867 dev_kfree_skb_any(skb);
1868 skb = NULL;
1869 }
1871 kfree(queue->rx_skbuff);
1872 queue->rx_skbuff = NULL;
1873 }
1874 }
1876 static void macb_free_rx_buffers(struct macb *bp)
1877 {
1878 struct macb_queue *queue = &bp->queues[0];
1880 if (queue->rx_buffers) {
1881 dma_free_coherent(&bp->pdev->dev,
1882 bp->rx_ring_size * bp->rx_buffer_size,
1883 queue->rx_buffers, queue->rx_buffers_dma);
1884 queue->rx_buffers = NULL;
1885 }
1886 }
1888 static void macb_free_consistent(struct macb *bp)
1889 {
1890 struct macb_queue *queue;
1891 unsigned int q;
1892 int size;
1894 bp->macbgem_ops.mog_free_rx_buffers(bp);
1896 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1897 kfree(queue->tx_skb);
1898 queue->tx_skb = NULL;
1899 if (queue->tx_ring) {
1900 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1901 dma_free_coherent(&bp->pdev->dev, size,
1902 queue->tx_ring, queue->tx_ring_dma);
1903 queue->tx_ring = NULL;
1904 }
1905 if (queue->rx_ring) {
1906 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
1907 dma_free_coherent(&bp->pdev->dev, size,
1908 queue->rx_ring, queue->rx_ring_dma);
1909 queue->rx_ring = NULL;
1910 }
1911 }
1912 }
1914 static int gem_alloc_rx_buffers(struct macb *bp)
1915 {
1916 struct macb_queue *queue;
1917 unsigned int q;
1918 int size;
1920 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1921 size = bp->rx_ring_size * sizeof(struct sk_buff *);
1922 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
1923 if (!queue->rx_skbuff)
1924 return -ENOMEM;
1925 else
1926 netdev_dbg(bp->dev,
1927 "Allocated %d RX struct sk_buff entries at %p\n",
1928 bp->rx_ring_size, queue->rx_skbuff);
1929 }
1930 return 0;
1931 }
1933 static int macb_alloc_rx_buffers(struct macb *bp)
1934 {
1935 struct macb_queue *queue = &bp->queues[0];
1936 int size;
1938 size = bp->rx_ring_size * bp->rx_buffer_size;
1939 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1940 &queue->rx_buffers_dma, GFP_KERNEL);
1941 if (!queue->rx_buffers)
1942 return -ENOMEM;
1944 netdev_dbg(bp->dev,
1945 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1946 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
1947 return 0;
1948 }
1950 static int macb_alloc_consistent(struct macb *bp)
1951 {
1952 struct macb_queue *queue;
1953 unsigned int q;
1954 int size;
1956 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1957 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
1958 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1959 &queue->tx_ring_dma,
1960 GFP_KERNEL);
1961 if (!queue->tx_ring)
1962 goto out_err;
1963 netdev_dbg(bp->dev,
1964 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1965 q, size, (unsigned long)queue->tx_ring_dma,
1966 queue->tx_ring);
1968 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
1969 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1970 if (!queue->tx_skb)
1971 goto out_err;
1973 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
1974 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1975 &queue->rx_ring_dma, GFP_KERNEL);
1976 if (!queue->rx_ring)
1977 goto out_err;
1978 netdev_dbg(bp->dev,
1979 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1980 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
1981 }
1982 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1983 goto out_err;
1985 return 0;
1987 out_err:
1988 macb_free_consistent(bp);
1989 return -ENOMEM;
1990 }
1992 static void gem_init_rings(struct macb *bp)
1993 {
1994 struct macb_queue *queue;
1995 struct macb_dma_desc *desc = NULL;
1996 unsigned int q;
1997 int i;
1999 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2000 for (i = 0; i < bp->tx_ring_size; i++) {
2001 desc = macb_tx_desc(queue, i);
2002 macb_set_addr(bp, desc, 0);
2003 desc->ctrl = MACB_BIT(TX_USED);
2004 }
2005 desc->ctrl |= MACB_BIT(TX_WRAP);
2006 queue->tx_head = 0;
2007 queue->tx_tail = 0;
2009 queue->rx_tail = 0;
2010 queue->rx_prepared_head = 0;
2012 gem_rx_refill(queue);
2013 }
2015 }
2017 static void macb_init_rings(struct macb *bp)
2018 {
2019 int i;
2020 struct macb_dma_desc *desc = NULL;
2022 macb_init_rx_ring(&bp->queues[0]);
2024 for (i = 0; i < bp->tx_ring_size; i++) {
2025 desc = macb_tx_desc(&bp->queues[0], i);
2026 macb_set_addr(bp, desc, 0);
2027 desc->ctrl = MACB_BIT(TX_USED);
2028 }
2029 bp->queues[0].tx_head = 0;
2030 bp->queues[0].tx_tail = 0;
2031 desc->ctrl |= MACB_BIT(TX_WRAP);
2032 }
2034 static void macb_reset_hw(struct macb *bp)
2035 {
2036 struct macb_queue *queue;
2037 unsigned int q;
2038 u32 ctrl = macb_readl(bp, NCR);
2040 /* Disable RX and TX (XXX: Should we halt the transmission
2041 * more gracefully?)
2042 */
2043 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2045 /* Clear the stats registers (XXX: Update stats first?) */
2046 ctrl |= MACB_BIT(CLRSTAT);
2048 macb_writel(bp, NCR, ctrl);
2050 /* Clear all status flags */
2051 macb_writel(bp, TSR, -1);
2052 macb_writel(bp, RSR, -1);
2054 /* Disable all interrupts */
2055 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2056 queue_writel(queue, IDR, -1);
2057 queue_readl(queue, ISR);
2058 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2059 queue_writel(queue, ISR, -1);
2060 }
2061 }
2063 static u32 gem_mdc_clk_div(struct macb *bp)
2064 {
2065 u32 config;
2066 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2068 if (pclk_hz <= 20000000)
2069 config = GEM_BF(CLK, GEM_CLK_DIV8);
2070 else if (pclk_hz <= 40000000)
2071 config = GEM_BF(CLK, GEM_CLK_DIV16);
2072 else if (pclk_hz <= 80000000)
2073 config = GEM_BF(CLK, GEM_CLK_DIV32);
2074 else if (pclk_hz <= 120000000)
2075 config = GEM_BF(CLK, GEM_CLK_DIV48);
2076 else if (pclk_hz <= 160000000)
2077 config = GEM_BF(CLK, GEM_CLK_DIV64);
2078 else
2079 config = GEM_BF(CLK, GEM_CLK_DIV96);
2081 return config;
2082 }
2084 static u32 macb_mdc_clk_div(struct macb *bp)
2085 {
2086 u32 config;
2087 unsigned long pclk_hz;
2089 if (macb_is_gem(bp))
2090 return gem_mdc_clk_div(bp);
2092 pclk_hz = clk_get_rate(bp->pclk);
2093 if (pclk_hz <= 20000000)
2094 config = MACB_BF(CLK, MACB_CLK_DIV8);
2095 else if (pclk_hz <= 40000000)
2096 config = MACB_BF(CLK, MACB_CLK_DIV16);
2097 else if (pclk_hz <= 80000000)
2098 config = MACB_BF(CLK, MACB_CLK_DIV32);
2099 else
2100 config = MACB_BF(CLK, MACB_CLK_DIV64);
2102 return config;
2103 }
2105 /* Get the DMA bus width field of the network configuration register that we
2106 * should program. We find the width from decoding the design configuration
2107 * register to find the maximum supported data bus width.
2108 */
2109 static u32 macb_dbw(struct macb *bp)
2110 {
2111 if (!macb_is_gem(bp))
2112 return 0;
2114 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2115 case 4:
2116 return GEM_BF(DBW, GEM_DBW128);
2117 case 2:
2118 return GEM_BF(DBW, GEM_DBW64);
2119 case 1:
2120 default:
2121 return GEM_BF(DBW, GEM_DBW32);
2122 }
2123 }
2125 /* Configure the receive DMA engine
2126 * - use the correct receive buffer size
2127 * - set best burst length for DMA operations
2128 * (if not supported by FIFO, it will fallback to default)
2129 * - set both rx/tx packet buffers to full memory size
2130 * These are configurable parameters for GEM.
2131 */
2132 static void macb_configure_dma(struct macb *bp)
2133 {
2134 struct macb_queue *queue;
2135 u32 buffer_size;
2136 unsigned int q;
2137 u32 dmacfg;
2139 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2140 if (macb_is_gem(bp)) {
2141 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2142 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2143 if (q)
2144 queue_writel(queue, RBQS, buffer_size);
2145 else
2146 dmacfg |= GEM_BF(RXBS, buffer_size);
2147 }
2148 if (bp->dma_burst_length)
2149 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2150 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2151 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2153 if (bp->native_io)
2154 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2155 else
2156 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2158 if (bp->dev->features & NETIF_F_HW_CSUM)
2159 dmacfg |= GEM_BIT(TXCOEN);
2160 else
2161 dmacfg &= ~GEM_BIT(TXCOEN);
2163 dmacfg &= ~GEM_BIT(ADDR64);
2164 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2165 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2166 dmacfg |= GEM_BIT(ADDR64);
2167 #endif
2168 #ifdef CONFIG_MACB_USE_HWSTAMP
2169 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2170 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2171 #endif
2172 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2173 dmacfg);
2174 gem_writel(bp, DMACFG, dmacfg);
2175 }
2176 }
2178 static void macb_init_hw(struct macb *bp)
2179 {
2180 struct macb_queue *queue;
2181 unsigned int q;
2183 u32 config;
2185 macb_reset_hw(bp);
2186 macb_set_hwaddr(bp);
2188 config = macb_mdc_clk_div(bp);
2189 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2190 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2191 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2192 config |= MACB_BIT(PAE); /* PAuse Enable */
2193 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2194 if (bp->caps & MACB_CAPS_JUMBO)
2195 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2196 else
2197 config |= MACB_BIT(BIG); /* Receive oversized frames */
2198 if (bp->dev->flags & IFF_PROMISC)
2199 config |= MACB_BIT(CAF); /* Copy All Frames */
2200 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2201 config |= GEM_BIT(RXCOEN);
2202 if (!(bp->dev->flags & IFF_BROADCAST))
2203 config |= MACB_BIT(NBC); /* No BroadCast */
2204 config |= macb_dbw(bp);
2205 macb_writel(bp, NCFGR, config);
2206 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2207 gem_writel(bp, JML, bp->jumbo_max_len);
2208 bp->speed = SPEED_10;
2209 bp->duplex = DUPLEX_HALF;
2210 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2211 if (bp->caps & MACB_CAPS_JUMBO)
2212 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2214 macb_configure_dma(bp);
2216 /* Initialize TX and RX buffers */
2217 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2218 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
2219 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2220 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2221 queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma));
2222 #endif
2223 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2224 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2225 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2226 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2227 #endif
2229 /* Enable interrupts */
2230 queue_writel(queue, IER,
2231 MACB_RX_INT_FLAGS |
2232 MACB_TX_INT_FLAGS |
2233 MACB_BIT(HRESP));
2234 }
2236 /* Enable TX and RX */
2237 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
2238 }
2240 /* The hash address register is 64 bits long and takes up two
2241 * locations in the memory map. The least significant bits are stored
2242 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2243 *
2244 * The unicast hash enable and the multicast hash enable bits in the
2245 * network configuration register enable the reception of hash matched
2246 * frames. The destination address is reduced to a 6 bit index into
2247 * the 64 bit hash register using the following hash function. The
2248 * hash function is an exclusive or of every sixth bit of the
2249 * destination address.
2250 *
2251 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2252 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2253 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2254 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2255 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2256 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2257 *
2258 * da[0] represents the least significant bit of the first byte
2259 * received, that is, the multicast/unicast indicator, and da[47]
2260 * represents the most significant bit of the last byte received. If
2261 * the hash index, hi[n], points to a bit that is set in the hash
2262 * register then the frame will be matched according to whether the
2263 * frame is multicast or unicast. A multicast match will be signalled
2264 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2265 * index points to a bit set in the hash register. A unicast match
2266 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2267 * and the hash index points to a bit set in the hash register. To
2268 * receive all multicast frames, the hash register should be set with
2269 * all ones and the multicast hash enable bit should be set in the
2270 * network configuration register.
2271 */
2273 static inline int hash_bit_value(int bitnr, __u8 *addr)
2274 {
2275 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2276 return 1;
2277 return 0;
2278 }
2280 /* Return the hash index value for the specified address. */
2281 static int hash_get_index(__u8 *addr)
2282 {
2283 int i, j, bitval;
2284 int hash_index = 0;
2286 for (j = 0; j < 6; j++) {
2287 for (i = 0, bitval = 0; i < 8; i++)
2288 bitval ^= hash_bit_value(i * 6 + j, addr);
2290 hash_index |= (bitval << j);
2291 }
2293 return hash_index;
2294 }
2296 /* Add multicast addresses to the internal multicast-hash table. */
2297 static void macb_sethashtable(struct net_device *dev)
2298 {
2299 struct netdev_hw_addr *ha;
2300 unsigned long mc_filter[2];
2301 unsigned int bitnr;
2302 struct macb *bp = netdev_priv(dev);
2304 mc_filter[0] = 0;
2305 mc_filter[1] = 0;
2307 netdev_for_each_mc_addr(ha, dev) {
2308 bitnr = hash_get_index(ha->addr);
2309 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2310 }
2312 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2313 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2314 }
2316 /* Enable/Disable promiscuous and multicast modes. */
2317 static void macb_set_rx_mode(struct net_device *dev)
2318 {
2319 unsigned long cfg;
2320 struct macb *bp = netdev_priv(dev);
2322 cfg = macb_readl(bp, NCFGR);
2324 if (dev->flags & IFF_PROMISC) {
2325 /* Enable promiscuous mode */
2326 cfg |= MACB_BIT(CAF);
2328 /* Disable RX checksum offload */
2329 if (macb_is_gem(bp))
2330 cfg &= ~GEM_BIT(RXCOEN);
2331 } else {
2332 /* Disable promiscuous mode */
2333 cfg &= ~MACB_BIT(CAF);
2335 /* Enable RX checksum offload only if requested */
2336 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2337 cfg |= GEM_BIT(RXCOEN);
2338 }
2340 if (dev->flags & IFF_ALLMULTI) {
2341 /* Enable all multicast mode */
2342 macb_or_gem_writel(bp, HRB, -1);
2343 macb_or_gem_writel(bp, HRT, -1);
2344 cfg |= MACB_BIT(NCFGR_MTI);
2345 } else if (!netdev_mc_empty(dev)) {
2346 /* Enable specific multicasts */
2347 macb_sethashtable(dev);
2348 cfg |= MACB_BIT(NCFGR_MTI);
2349 } else if (dev->flags & (~IFF_ALLMULTI)) {
2350 /* Disable all multicast mode */
2351 macb_or_gem_writel(bp, HRB, 0);
2352 macb_or_gem_writel(bp, HRT, 0);
2353 cfg &= ~MACB_BIT(NCFGR_MTI);
2354 }
2356 macb_writel(bp, NCFGR, cfg);
2357 }
2359 static int macb_open(struct net_device *dev)
2360 {
2361 struct macb *bp = netdev_priv(dev);
2362 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2363 struct macb_queue *queue;
2364 unsigned int q;
2365 int err;
2367 netdev_dbg(bp->dev, "open\n");
2369 /* carrier starts down */
2370 netif_carrier_off(dev);
2372 /* if the phy is not yet register, retry later*/
2373 if (!dev->phydev)
2374 return -EAGAIN;
2376 /* RX buffers initialization */
2377 macb_init_rx_buffer_size(bp, bufsz);
2379 err = macb_alloc_consistent(bp);
2380 if (err) {
2381 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2382 err);
2383 return err;
2384 }
2386 bp->macbgem_ops.mog_init_rings(bp);
2387 macb_init_hw(bp);
2389 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2390 napi_enable(&queue->napi);
2392 /* schedule a link state check */
2393 phy_start(dev->phydev);
2395 netif_tx_start_all_queues(dev);
2397 if (bp->ptp_info)
2398 bp->ptp_info->ptp_init(dev);
2400 return 0;
2401 }
2403 static int macb_close(struct net_device *dev)
2404 {
2405 struct macb *bp = netdev_priv(dev);
2406 struct macb_queue *queue;
2407 unsigned long flags;
2408 unsigned int q;
2410 netif_tx_stop_all_queues(dev);
2412 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2413 napi_disable(&queue->napi);
2415 if (dev->phydev)
2416 phy_stop(dev->phydev);
2418 spin_lock_irqsave(&bp->lock, flags);
2419 macb_reset_hw(bp);
2420 netif_carrier_off(dev);
2421 spin_unlock_irqrestore(&bp->lock, flags);
2423 macb_free_consistent(bp);
2425 if (bp->ptp_info)
2426 bp->ptp_info->ptp_remove(dev);
2428 return 0;
2429 }
2431 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2432 {
2433 if (netif_running(dev))
2434 return -EBUSY;
2436 dev->mtu = new_mtu;
2438 return 0;
2439 }
2441 static void gem_update_stats(struct macb *bp)
2442 {
2443 struct macb_queue *queue;
2444 unsigned int i, q, idx;
2445 unsigned long *stat;
2447 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2449 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2450 u32 offset = gem_statistics[i].offset;
2451 u64 val = bp->macb_reg_readl(bp, offset);
2453 bp->ethtool_stats[i] += val;
2454 *p += val;
2456 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2457 /* Add GEM_OCTTXH, GEM_OCTRXH */
2458 val = bp->macb_reg_readl(bp, offset + 4);
2459 bp->ethtool_stats[i] += ((u64)val) << 32;
2460 *(++p) += val;
2461 }
2462 }
2464 idx = GEM_STATS_LEN;
2465 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2466 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2467 bp->ethtool_stats[idx++] = *stat;
2468 }
2470 static struct net_device_stats *gem_get_stats(struct macb *bp)
2471 {
2472 struct gem_stats *hwstat = &bp->hw_stats.gem;
2473 struct net_device_stats *nstat = &bp->dev->stats;
2475 gem_update_stats(bp);
2477 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2478 hwstat->rx_alignment_errors +
2479 hwstat->rx_resource_errors +
2480 hwstat->rx_overruns +
2481 hwstat->rx_oversize_frames +
2482 hwstat->rx_jabbers +
2483 hwstat->rx_undersized_frames +
2484 hwstat->rx_length_field_frame_errors);
2485 nstat->tx_errors = (hwstat->tx_late_collisions +
2486 hwstat->tx_excessive_collisions +
2487 hwstat->tx_underrun +
2488 hwstat->tx_carrier_sense_errors);
2489 nstat->multicast = hwstat->rx_multicast_frames;
2490 nstat->collisions = (hwstat->tx_single_collision_frames +
2491 hwstat->tx_multiple_collision_frames +
2492 hwstat->tx_excessive_collisions);
2493 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2494 hwstat->rx_jabbers +
2495 hwstat->rx_undersized_frames +
2496 hwstat->rx_length_field_frame_errors);
2497 nstat->rx_over_errors = hwstat->rx_resource_errors;
2498 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2499 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2500 nstat->rx_fifo_errors = hwstat->rx_overruns;
2501 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2502 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2503 nstat->tx_fifo_errors = hwstat->tx_underrun;
2505 return nstat;
2506 }
2508 static void gem_get_ethtool_stats(struct net_device *dev,
2509 struct ethtool_stats *stats, u64 *data)
2510 {
2511 struct macb *bp;
2513 bp = netdev_priv(dev);
2514 gem_update_stats(bp);
2515 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2516 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2517 }
2519 static int gem_get_sset_count(struct net_device *dev, int sset)
2520 {
2521 struct macb *bp = netdev_priv(dev);
2523 switch (sset) {
2524 case ETH_SS_STATS:
2525 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2526 default:
2527 return -EOPNOTSUPP;
2528 }
2529 }
2531 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2532 {
2533 char stat_string[ETH_GSTRING_LEN];
2534 struct macb *bp = netdev_priv(dev);
2535 struct macb_queue *queue;
2536 unsigned int i;
2537 unsigned int q;
2539 switch (sset) {
2540 case ETH_SS_STATS:
2541 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2542 memcpy(p, gem_statistics[i].stat_string,
2543 ETH_GSTRING_LEN);
2545 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2546 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2547 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2548 q, queue_statistics[i].stat_string);
2549 memcpy(p, stat_string, ETH_GSTRING_LEN);
2550 }
2551 }
2552 break;
2553 }
2554 }
2556 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2557 {
2558 struct macb *bp = netdev_priv(dev);
2559 struct net_device_stats *nstat = &bp->dev->stats;
2560 struct macb_stats *hwstat = &bp->hw_stats.macb;
2562 if (macb_is_gem(bp))
2563 return gem_get_stats(bp);
2565 /* read stats from hardware */
2566 macb_update_stats(bp);
2568 /* Convert HW stats into netdevice stats */
2569 nstat->rx_errors = (hwstat->rx_fcs_errors +
2570 hwstat->rx_align_errors +
2571 hwstat->rx_resource_errors +
2572 hwstat->rx_overruns +
2573 hwstat->rx_oversize_pkts +
2574 hwstat->rx_jabbers +
2575 hwstat->rx_undersize_pkts +
2576 hwstat->rx_length_mismatch);
2577 nstat->tx_errors = (hwstat->tx_late_cols +
2578 hwstat->tx_excessive_cols +
2579 hwstat->tx_underruns +
2580 hwstat->tx_carrier_errors +
2581 hwstat->sqe_test_errors);
2582 nstat->collisions = (hwstat->tx_single_cols +
2583 hwstat->tx_multiple_cols +
2584 hwstat->tx_excessive_cols);
2585 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2586 hwstat->rx_jabbers +
2587 hwstat->rx_undersize_pkts +
2588 hwstat->rx_length_mismatch);
2589 nstat->rx_over_errors = hwstat->rx_resource_errors +
2590 hwstat->rx_overruns;
2591 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2592 nstat->rx_frame_errors = hwstat->rx_align_errors;
2593 nstat->rx_fifo_errors = hwstat->rx_overruns;
2594 /* XXX: What does "missed" mean? */
2595 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2596 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2597 nstat->tx_fifo_errors = hwstat->tx_underruns;
2598 /* Don't know about heartbeat or window errors... */
2600 return nstat;
2601 }
2603 static int macb_get_regs_len(struct net_device *netdev)
2604 {
2605 return MACB_GREGS_NBR * sizeof(u32);
2606 }
2608 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2609 void *p)
2610 {
2611 struct macb *bp = netdev_priv(dev);
2612 unsigned int tail, head;
2613 u32 *regs_buff = p;
2615 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2616 | MACB_GREGS_VERSION;
2618 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2619 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2621 regs_buff[0] = macb_readl(bp, NCR);
2622 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2623 regs_buff[2] = macb_readl(bp, NSR);
2624 regs_buff[3] = macb_readl(bp, TSR);
2625 regs_buff[4] = macb_readl(bp, RBQP);
2626 regs_buff[5] = macb_readl(bp, TBQP);
2627 regs_buff[6] = macb_readl(bp, RSR);
2628 regs_buff[7] = macb_readl(bp, IMR);
2630 regs_buff[8] = tail;
2631 regs_buff[9] = head;
2632 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2633 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2635 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2636 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2637 if (macb_is_gem(bp))
2638 regs_buff[13] = gem_readl(bp, DMACFG);
2639 }
2641 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2642 {
2643 struct macb *bp = netdev_priv(netdev);
2645 wol->supported = 0;
2646 wol->wolopts = 0;
2648 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2649 wol->supported = WAKE_MAGIC;
2651 if (bp->wol & MACB_WOL_ENABLED)
2652 wol->wolopts |= WAKE_MAGIC;
2653 }
2654 }
2656 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2657 {
2658 struct macb *bp = netdev_priv(netdev);
2660 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2661 (wol->wolopts & ~WAKE_MAGIC))
2662 return -EOPNOTSUPP;
2664 if (wol->wolopts & WAKE_MAGIC)
2665 bp->wol |= MACB_WOL_ENABLED;
2666 else
2667 bp->wol &= ~MACB_WOL_ENABLED;
2669 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2671 return 0;
2672 }
2674 static void macb_get_ringparam(struct net_device *netdev,
2675 struct ethtool_ringparam *ring)
2676 {
2677 struct macb *bp = netdev_priv(netdev);
2679 ring->rx_max_pending = MAX_RX_RING_SIZE;
2680 ring->tx_max_pending = MAX_TX_RING_SIZE;
2682 ring->rx_pending = bp->rx_ring_size;
2683 ring->tx_pending = bp->tx_ring_size;
2684 }
2686 static int macb_set_ringparam(struct net_device *netdev,
2687 struct ethtool_ringparam *ring)
2688 {
2689 struct macb *bp = netdev_priv(netdev);
2690 u32 new_rx_size, new_tx_size;
2691 unsigned int reset = 0;
2693 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2694 return -EINVAL;
2696 new_rx_size = clamp_t(u32, ring->rx_pending,
2697 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2698 new_rx_size = roundup_pow_of_two(new_rx_size);
2700 new_tx_size = clamp_t(u32, ring->tx_pending,
2701 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2702 new_tx_size = roundup_pow_of_two(new_tx_size);
2704 if ((new_tx_size == bp->tx_ring_size) &&
2705 (new_rx_size == bp->rx_ring_size)) {
2706 /* nothing to do */
2707 return 0;
2708 }
2710 if (netif_running(bp->dev)) {
2711 reset = 1;
2712 macb_close(bp->dev);
2713 }
2715 bp->rx_ring_size = new_rx_size;
2716 bp->tx_ring_size = new_tx_size;
2718 if (reset)
2719 macb_open(bp->dev);
2721 return 0;
2722 }
2724 #ifdef CONFIG_MACB_USE_HWSTAMP
2725 static unsigned int gem_get_tsu_rate(struct macb *bp)
2726 {
2727 struct clk *tsu_clk;
2728 unsigned int tsu_rate;
2730 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2731 if (!IS_ERR(tsu_clk))
2732 tsu_rate = clk_get_rate(tsu_clk);
2733 /* try pclk instead */
2734 else if (!IS_ERR(bp->pclk)) {
2735 tsu_clk = bp->pclk;
2736 tsu_rate = clk_get_rate(tsu_clk);
2737 } else
2738 return -ENOTSUPP;
2739 return tsu_rate;
2740 }
2742 static s32 gem_get_ptp_max_adj(void)
2743 {
2744 return 64000000;
2745 }
2747 static int gem_get_ts_info(struct net_device *dev,
2748 struct ethtool_ts_info *info)
2749 {
2750 struct macb *bp = netdev_priv(dev);
2752 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2753 ethtool_op_get_ts_info(dev, info);
2754 return 0;
2755 }
2757 info->so_timestamping =
2758 SOF_TIMESTAMPING_TX_SOFTWARE |
2759 SOF_TIMESTAMPING_RX_SOFTWARE |
2760 SOF_TIMESTAMPING_SOFTWARE |
2761 SOF_TIMESTAMPING_TX_HARDWARE |
2762 SOF_TIMESTAMPING_RX_HARDWARE |
2763 SOF_TIMESTAMPING_RAW_HARDWARE;
2764 info->tx_types =
2765 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2766 (1 << HWTSTAMP_TX_OFF) |
2767 (1 << HWTSTAMP_TX_ON);
2768 info->rx_filters =
2769 (1 << HWTSTAMP_FILTER_NONE) |
2770 (1 << HWTSTAMP_FILTER_ALL);
2772 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2774 return 0;
2775 }
2777 static struct macb_ptp_info gem_ptp_info = {
2778 .ptp_init = gem_ptp_init,
2779 .ptp_remove = gem_ptp_remove,
2780 .get_ptp_max_adj = gem_get_ptp_max_adj,
2781 .get_tsu_rate = gem_get_tsu_rate,
2782 .get_ts_info = gem_get_ts_info,
2783 .get_hwtst = gem_get_hwtst,
2784 .set_hwtst = gem_set_hwtst,
2785 };
2786 #endif
2788 static int macb_get_ts_info(struct net_device *netdev,
2789 struct ethtool_ts_info *info)
2790 {
2791 struct macb *bp = netdev_priv(netdev);
2793 if (bp->ptp_info)
2794 return bp->ptp_info->get_ts_info(netdev, info);
2796 return ethtool_op_get_ts_info(netdev, info);
2797 }
2799 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2800 {
2801 struct ethtool_rx_fs_item *item;
2802 u32 t2_scr;
2803 int num_t2_scr;
2805 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2807 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2808 struct ethtool_rx_flow_spec *fs = &item->fs;
2809 struct ethtool_tcpip4_spec *tp4sp_m;
2811 if (fs->location >= num_t2_scr)
2812 continue;
2814 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2816 /* enable/disable screener regs for the flow entry */
2817 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2819 /* only enable fields with no masking */
2820 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2822 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2823 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2824 else
2825 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2827 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2828 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2829 else
2830 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2832 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2833 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2834 else
2835 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2837 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2838 }
2839 }
2841 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2842 {
2843 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2844 uint16_t index = fs->location;
2845 u32 w0, w1, t2_scr;
2846 bool cmp_a = false;
2847 bool cmp_b = false;
2848 bool cmp_c = false;
2850 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2851 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2853 /* ignore field if any masking set */
2854 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2855 /* 1st compare reg - IP source address */
2856 w0 = 0;
2857 w1 = 0;
2858 w0 = tp4sp_v->ip4src;
2859 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2860 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2861 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2862 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2863 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2864 cmp_a = true;
2865 }
2867 /* ignore field if any masking set */
2868 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2869 /* 2nd compare reg - IP destination address */
2870 w0 = 0;
2871 w1 = 0;
2872 w0 = tp4sp_v->ip4dst;
2873 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2874 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2875 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
2876 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
2877 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
2878 cmp_b = true;
2879 }
2881 /* ignore both port fields if masking set in both */
2882 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
2883 /* 3rd compare reg - source port, destination port */
2884 w0 = 0;
2885 w1 = 0;
2886 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
2887 if (tp4sp_m->psrc == tp4sp_m->pdst) {
2888 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
2889 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2890 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2891 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2892 } else {
2893 /* only one port definition */
2894 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
2895 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
2896 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
2897 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
2898 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
2899 } else { /* dst port */
2900 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
2901 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
2902 }
2903 }
2904 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
2905 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
2906 cmp_c = true;
2907 }
2909 t2_scr = 0;
2910 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
2911 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
2912 if (cmp_a)
2913 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
2914 if (cmp_b)
2915 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
2916 if (cmp_c)
2917 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
2918 gem_writel_n(bp, SCRT2, index, t2_scr);
2919 }
2921 static int gem_add_flow_filter(struct net_device *netdev,
2922 struct ethtool_rxnfc *cmd)
2923 {
2924 struct macb *bp = netdev_priv(netdev);
2925 struct ethtool_rx_flow_spec *fs = &cmd->fs;
2926 struct ethtool_rx_fs_item *item, *newfs;
2927 unsigned long flags;
2928 int ret = -EINVAL;
2929 bool added = false;
2931 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
2932 if (newfs == NULL)
2933 return -ENOMEM;
2934 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
2936 netdev_dbg(netdev,
2937 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
2938 fs->flow_type, (int)fs->ring_cookie, fs->location,
2939 htonl(fs->h_u.tcp_ip4_spec.ip4src),
2940 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
2941 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
2943 spin_lock_irqsave(&bp->rx_fs_lock, flags);
2945 /* find correct place to add in list */
2946 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2947 if (item->fs.location > newfs->fs.location) {
2948 list_add_tail(&newfs->list, &item->list);
2949 added = true;
2950 break;
2951 } else if (item->fs.location == fs->location) {
2952 netdev_err(netdev, "Rule not added: location %d not free!\n",
2953 fs->location);
2954 ret = -EBUSY;
2955 goto err;
2956 }
2957 }
2958 if (!added)
2959 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
2961 gem_prog_cmp_regs(bp, fs);
2962 bp->rx_fs_list.count++;
2963 /* enable filtering if NTUPLE on */
2964 if (netdev->features & NETIF_F_NTUPLE)
2965 gem_enable_flow_filters(bp, 1);
2967 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
2968 return 0;
2970 err:
2971 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
2972 kfree(newfs);
2973 return ret;
2974 }
2976 static int gem_del_flow_filter(struct net_device *netdev,
2977 struct ethtool_rxnfc *cmd)
2978 {
2979 struct macb *bp = netdev_priv(netdev);
2980 struct ethtool_rx_fs_item *item;
2981 struct ethtool_rx_flow_spec *fs;
2982 unsigned long flags;
2984 spin_lock_irqsave(&bp->rx_fs_lock, flags);
2986 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2987 if (item->fs.location == cmd->fs.location) {
2988 /* disable screener regs for the flow entry */
2989 fs = &(item->fs);
2990 netdev_dbg(netdev,
2991 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
2992 fs->flow_type, (int)fs->ring_cookie, fs->location,
2993 htonl(fs->h_u.tcp_ip4_spec.ip4src),
2994 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
2995 htons(fs->h_u.tcp_ip4_spec.psrc),
2996 htons(fs->h_u.tcp_ip4_spec.pdst));
2998 gem_writel_n(bp, SCRT2, fs->location, 0);
3000 list_del(&item->list);
3001 bp->rx_fs_list.count--;
3002 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3003 kfree(item);
3004 return 0;
3005 }
3006 }
3008 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3009 return -EINVAL;
3010 }
3012 static int gem_get_flow_entry(struct net_device *netdev,
3013 struct ethtool_rxnfc *cmd)
3014 {
3015 struct macb *bp = netdev_priv(netdev);
3016 struct ethtool_rx_fs_item *item;
3018 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3019 if (item->fs.location == cmd->fs.location) {
3020 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3021 return 0;
3022 }
3023 }
3024 return -EINVAL;
3025 }
3027 static int gem_get_all_flow_entries(struct net_device *netdev,
3028 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3029 {
3030 struct macb *bp = netdev_priv(netdev);
3031 struct ethtool_rx_fs_item *item;
3032 uint32_t cnt = 0;
3034 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3035 if (cnt == cmd->rule_cnt)
3036 return -EMSGSIZE;
3037 rule_locs[cnt] = item->fs.location;
3038 cnt++;
3039 }
3040 cmd->data = bp->max_tuples;
3041 cmd->rule_cnt = cnt;
3043 return 0;
3044 }
3046 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3047 u32 *rule_locs)
3048 {
3049 struct macb *bp = netdev_priv(netdev);
3050 int ret = 0;
3052 switch (cmd->cmd) {
3053 case ETHTOOL_GRXRINGS:
3054 cmd->data = bp->num_queues;
3055 break;
3056 case ETHTOOL_GRXCLSRLCNT:
3057 cmd->rule_cnt = bp->rx_fs_list.count;
3058 break;
3059 case ETHTOOL_GRXCLSRULE:
3060 ret = gem_get_flow_entry(netdev, cmd);
3061 break;
3062 case ETHTOOL_GRXCLSRLALL:
3063 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3064 break;
3065 default:
3066 netdev_err(netdev,
3067 "Command parameter %d is not supported\n", cmd->cmd);
3068 ret = -EOPNOTSUPP;
3069 }
3071 return ret;
3072 }
3074 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3075 {
3076 struct macb *bp = netdev_priv(netdev);
3077 int ret;
3079 switch (cmd->cmd) {
3080 case ETHTOOL_SRXCLSRLINS:
3081 if ((cmd->fs.location >= bp->max_tuples)
3082 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3083 ret = -EINVAL;
3084 break;
3085 }
3086 ret = gem_add_flow_filter(netdev, cmd);
3087 break;
3088 case ETHTOOL_SRXCLSRLDEL:
3089 ret = gem_del_flow_filter(netdev, cmd);
3090 break;
3091 default:
3092 netdev_err(netdev,
3093 "Command parameter %d is not supported\n", cmd->cmd);
3094 ret = -EOPNOTSUPP;
3095 }
3097 return ret;
3098 }
3100 static const struct ethtool_ops macb_ethtool_ops = {
3101 .get_regs_len = macb_get_regs_len,
3102 .get_regs = macb_get_regs,
3103 .get_link = ethtool_op_get_link,
3104 .get_ts_info = ethtool_op_get_ts_info,
3105 .get_wol = macb_get_wol,
3106 .set_wol = macb_set_wol,
3107 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3108 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3109 .get_ringparam = macb_get_ringparam,
3110 .set_ringparam = macb_set_ringparam,
3111 };
3113 static const struct ethtool_ops gem_ethtool_ops = {
3114 .get_regs_len = macb_get_regs_len,
3115 .get_regs = macb_get_regs,
3116 .get_link = ethtool_op_get_link,
3117 .get_ts_info = macb_get_ts_info,
3118 .get_ethtool_stats = gem_get_ethtool_stats,
3119 .get_strings = gem_get_ethtool_strings,
3120 .get_sset_count = gem_get_sset_count,
3121 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3122 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3123 .get_ringparam = macb_get_ringparam,
3124 .set_ringparam = macb_set_ringparam,
3125 .get_rxnfc = gem_get_rxnfc,
3126 .set_rxnfc = gem_set_rxnfc,
3127 };
3129 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3130 {
3131 struct phy_device *phydev = dev->phydev;
3132 struct macb *bp = netdev_priv(dev);
3134 if (!netif_running(dev))
3135 return -EINVAL;
3137 if (!phydev)
3138 return -ENODEV;
3140 if (!bp->ptp_info)
3141 return phy_mii_ioctl(phydev, rq, cmd);
3143 switch (cmd) {
3144 case SIOCSHWTSTAMP:
3145 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3146 case SIOCGHWTSTAMP:
3147 return bp->ptp_info->get_hwtst(dev, rq);
3148 default:
3149 return phy_mii_ioctl(phydev, rq, cmd);
3150 }
3151 }
3153 static int macb_set_features(struct net_device *netdev,
3154 netdev_features_t features)
3155 {
3156 struct macb *bp = netdev_priv(netdev);
3157 netdev_features_t changed = features ^ netdev->features;
3159 /* TX checksum offload */
3160 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
3161 u32 dmacfg;
3163 dmacfg = gem_readl(bp, DMACFG);
3164 if (features & NETIF_F_HW_CSUM)
3165 dmacfg |= GEM_BIT(TXCOEN);
3166 else
3167 dmacfg &= ~GEM_BIT(TXCOEN);
3168 gem_writel(bp, DMACFG, dmacfg);
3169 }
3171 /* RX checksum offload */
3172 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
3173 u32 netcfg;
3175 netcfg = gem_readl(bp, NCFGR);
3176 if (features & NETIF_F_RXCSUM &&
3177 !(netdev->flags & IFF_PROMISC))
3178 netcfg |= GEM_BIT(RXCOEN);
3179 else
3180 netcfg &= ~GEM_BIT(RXCOEN);
3181 gem_writel(bp, NCFGR, netcfg);
3182 }
3184 /* RX Flow Filters */
3185 if ((changed & NETIF_F_NTUPLE) && macb_is_gem(bp)) {
3186 bool turn_on = features & NETIF_F_NTUPLE;
3188 gem_enable_flow_filters(bp, turn_on);
3189 }
3190 return 0;
3191 }
3193 static const struct net_device_ops macb_netdev_ops = {
3194 .ndo_open = macb_open,
3195 .ndo_stop = macb_close,
3196 .ndo_start_xmit = macb_start_xmit,
3197 .ndo_set_rx_mode = macb_set_rx_mode,
3198 .ndo_get_stats = macb_get_stats,
3199 .ndo_do_ioctl = macb_ioctl,
3200 .ndo_validate_addr = eth_validate_addr,
3201 .ndo_change_mtu = macb_change_mtu,
3202 .ndo_set_mac_address = eth_mac_addr,
3203 #ifdef CONFIG_NET_POLL_CONTROLLER
3204 .ndo_poll_controller = macb_poll_controller,
3205 #endif
3206 .ndo_set_features = macb_set_features,
3207 .ndo_features_check = macb_features_check,
3208 };
3210 /* Configure peripheral capabilities according to device tree
3211 * and integration options used
3212 */
3213 static void macb_configure_caps(struct macb *bp,
3214 const struct macb_config *dt_conf)
3215 {
3216 u32 dcfg;
3218 if (dt_conf)
3219 bp->caps = dt_conf->caps;
3221 if (hw_is_gem(bp->regs, bp->native_io)) {
3222 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3224 dcfg = gem_readl(bp, DCFG1);
3225 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3226 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3227 dcfg = gem_readl(bp, DCFG2);
3228 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3229 bp->caps |= MACB_CAPS_FIFO_MODE;
3230 #ifdef CONFIG_MACB_USE_HWSTAMP
3231 if (gem_has_ptp(bp)) {
3232 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3233 pr_err("GEM doesn't support hardware ptp.\n");
3234 else {
3235 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3236 bp->ptp_info = &gem_ptp_info;
3237 }
3238 }
3239 #endif
3240 }
3242 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3243 }
3245 static void macb_probe_queues(void __iomem *mem,
3246 bool native_io,
3247 unsigned int *queue_mask,
3248 unsigned int *num_queues)
3249 {
3250 unsigned int hw_q;
3252 *queue_mask = 0x1;
3253 *num_queues = 1;
3255 /* is it macb or gem ?
3256 *
3257 * We need to read directly from the hardware here because
3258 * we are early in the probe process and don't have the
3259 * MACB_CAPS_MACB_IS_GEM flag positioned
3260 */
3261 if (!hw_is_gem(mem, native_io))
3262 return;
3264 /* bit 0 is never set but queue 0 always exists */
3265 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3267 *queue_mask |= 0x1;
3269 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3270 if (*queue_mask & (1 << hw_q))
3271 (*num_queues)++;
3272 }
3274 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3275 struct clk **hclk, struct clk **tx_clk,
3276 struct clk **rx_clk)
3277 {
3278 struct macb_platform_data *pdata;
3279 int err;
3281 pdata = dev_get_platdata(&pdev->dev);
3282 if (pdata) {
3283 *pclk = pdata->pclk;
3284 *hclk = pdata->hclk;
3285 } else {
3286 *pclk = devm_clk_get(&pdev->dev, "pclk");
3287 *hclk = devm_clk_get(&pdev->dev, "hclk");
3288 }
3290 if (IS_ERR(*pclk)) {
3291 err = PTR_ERR(*pclk);
3292 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
3293 return err;
3294 }
3296 if (IS_ERR(*hclk)) {
3297 err = PTR_ERR(*hclk);
3298 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
3299 return err;
3300 }
3302 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
3303 if (IS_ERR(*tx_clk))
3304 *tx_clk = NULL;
3306 *rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
3307 if (IS_ERR(*rx_clk))
3308 *rx_clk = NULL;
3310 err = clk_prepare_enable(*pclk);
3311 if (err) {
3312 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3313 return err;
3314 }
3316 err = clk_prepare_enable(*hclk);
3317 if (err) {
3318 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
3319 goto err_disable_pclk;
3320 }
3322 err = clk_prepare_enable(*tx_clk);
3323 if (err) {
3324 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
3325 goto err_disable_hclk;
3326 }
3328 err = clk_prepare_enable(*rx_clk);
3329 if (err) {
3330 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
3331 goto err_disable_txclk;
3332 }
3334 return 0;
3336 err_disable_txclk:
3337 clk_disable_unprepare(*tx_clk);
3339 err_disable_hclk:
3340 clk_disable_unprepare(*hclk);
3342 err_disable_pclk:
3343 clk_disable_unprepare(*pclk);
3345 return err;
3346 }
3348 static int macb_init(struct platform_device *pdev)
3349 {
3350 struct net_device *dev = platform_get_drvdata(pdev);
3351 unsigned int hw_q, q;
3352 struct macb *bp = netdev_priv(dev);
3353 struct macb_queue *queue;
3354 int err;
3355 u32 val, reg;
3357 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3358 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3360 /* set the queue register mapping once for all: queue0 has a special
3361 * register mapping but we don't want to test the queue index then
3362 * compute the corresponding register offset at run time.
3363 */
3364 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3365 if (!(bp->queue_mask & (1 << hw_q)))
3366 continue;
3368 queue = &bp->queues[q];
3369 queue->bp = bp;
3370 netif_napi_add(dev, &queue->napi, macb_poll, 64);
3371 if (hw_q) {
3372 queue->ISR = GEM_ISR(hw_q - 1);
3373 queue->IER = GEM_IER(hw_q - 1);
3374 queue->IDR = GEM_IDR(hw_q - 1);
3375 queue->IMR = GEM_IMR(hw_q - 1);
3376 queue->TBQP = GEM_TBQP(hw_q - 1);
3377 queue->RBQP = GEM_RBQP(hw_q - 1);
3378 queue->RBQS = GEM_RBQS(hw_q - 1);
3379 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3380 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3381 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3382 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3383 }
3384 #endif
3385 } else {
3386 /* queue0 uses legacy registers */
3387 queue->ISR = MACB_ISR;
3388 queue->IER = MACB_IER;
3389 queue->IDR = MACB_IDR;
3390 queue->IMR = MACB_IMR;
3391 queue->TBQP = MACB_TBQP;
3392 queue->RBQP = MACB_RBQP;
3393 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3394 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3395 queue->TBQPH = MACB_TBQPH;
3396 queue->RBQPH = MACB_RBQPH;
3397 }
3398 #endif
3399 }
3401 /* get irq: here we use the linux queue index, not the hardware
3402 * queue index. the queue irq definitions in the device tree
3403 * must remove the optional gaps that could exist in the
3404 * hardware queue mask.
3405 */
3406 queue->irq = platform_get_irq(pdev, q);
3407 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3408 IRQF_SHARED, dev->name, queue);
3409 if (err) {
3410 dev_err(&pdev->dev,
3411 "Unable to request IRQ %d (error %d)\n",
3412 queue->irq, err);
3413 return err;
3414 }
3416 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3417 q++;
3418 }
3420 dev->netdev_ops = &macb_netdev_ops;
3422 /* setup appropriated routines according to adapter type */
3423 if (macb_is_gem(bp)) {
3424 bp->max_tx_length = GEM_MAX_TX_LEN;
3425 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3426 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3427 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3428 bp->macbgem_ops.mog_rx = gem_rx;
3429 dev->ethtool_ops = &gem_ethtool_ops;
3430 } else {
3431 bp->max_tx_length = MACB_MAX_TX_LEN;
3432 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3433 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3434 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3435 bp->macbgem_ops.mog_rx = macb_rx;
3436 dev->ethtool_ops = &macb_ethtool_ops;
3437 }
3439 /* Set features */
3440 dev->hw_features = NETIF_F_SG;
3442 /* Check LSO capability */
3443 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3444 dev->hw_features |= MACB_NETIF_LSO;
3446 /* Checksum offload is only available on gem with packet buffer */
3447 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3448 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3449 if (bp->caps & MACB_CAPS_SG_DISABLED)
3450 dev->hw_features &= ~NETIF_F_SG;
3451 dev->features = dev->hw_features;
3453 /* Check RX Flow Filters support.
3454 * Max Rx flows set by availability of screeners & compare regs:
3455 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3456 */
3457 reg = gem_readl(bp, DCFG8);
3458 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3459 GEM_BFEXT(T2SCR, reg));
3460 if (bp->max_tuples > 0) {
3461 /* also needs one ethtype match to check IPv4 */
3462 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3463 /* program this reg now */
3464 reg = 0;
3465 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3466 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3467 /* Filtering is supported in hw but don't enable it in kernel now */
3468 dev->hw_features |= NETIF_F_NTUPLE;
3469 /* init Rx flow definitions */
3470 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3471 bp->rx_fs_list.count = 0;
3472 spin_lock_init(&bp->rx_fs_lock);
3473 } else
3474 bp->max_tuples = 0;
3475 }
3477 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3478 val = 0;
3479 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3480 val = GEM_BIT(RGMII);
3481 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3482 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3483 val = MACB_BIT(RMII);
3484 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3485 val = MACB_BIT(MII);
3487 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3488 val |= MACB_BIT(CLKEN);
3490 macb_or_gem_writel(bp, USRIO, val);
3491 }
3493 /* Set MII management clock divider */
3494 val = macb_mdc_clk_div(bp);
3495 val |= macb_dbw(bp);
3496 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3497 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3498 macb_writel(bp, NCFGR, val);
3500 return 0;
3501 }
3503 #if defined(CONFIG_OF)
3504 /* 1518 rounded up */
3505 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3506 /* max number of receive buffers */
3507 #define AT91ETHER_MAX_RX_DESCR 9
3509 /* Initialize and start the Receiver and Transmit subsystems */
3510 static int at91ether_start(struct net_device *dev)
3511 {
3512 struct macb *lp = netdev_priv(dev);
3513 struct macb_queue *q = &lp->queues[0];
3514 struct macb_dma_desc *desc;
3515 dma_addr_t addr;
3516 u32 ctl;
3517 int i;
3519 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3520 (AT91ETHER_MAX_RX_DESCR *
3521 macb_dma_desc_get_size(lp)),
3522 &q->rx_ring_dma, GFP_KERNEL);
3523 if (!q->rx_ring)
3524 return -ENOMEM;
3526 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3527 AT91ETHER_MAX_RX_DESCR *
3528 AT91ETHER_MAX_RBUFF_SZ,
3529 &q->rx_buffers_dma, GFP_KERNEL);
3530 if (!q->rx_buffers) {
3531 dma_free_coherent(&lp->pdev->dev,
3532 AT91ETHER_MAX_RX_DESCR *
3533 macb_dma_desc_get_size(lp),
3534 q->rx_ring, q->rx_ring_dma);
3535 q->rx_ring = NULL;
3536 return -ENOMEM;
3537 }
3539 addr = q->rx_buffers_dma;
3540 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3541 desc = macb_rx_desc(q, i);
3542 macb_set_addr(lp, desc, addr);
3543 desc->ctrl = 0;
3544 addr += AT91ETHER_MAX_RBUFF_SZ;
3545 }
3547 /* Set the Wrap bit on the last descriptor */
3548 desc->addr |= MACB_BIT(RX_WRAP);
3550 /* Reset buffer index */
3551 q->rx_tail = 0;
3553 /* Program address of descriptor list in Rx Buffer Queue register */
3554 macb_writel(lp, RBQP, q->rx_ring_dma);
3556 /* Enable Receive and Transmit */
3557 ctl = macb_readl(lp, NCR);
3558 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3560 return 0;
3561 }
3563 /* Open the ethernet interface */
3564 static int at91ether_open(struct net_device *dev)
3565 {
3566 struct macb *lp = netdev_priv(dev);
3567 u32 ctl;
3568 int ret;
3570 /* Clear internal statistics */
3571 ctl = macb_readl(lp, NCR);
3572 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3574 macb_set_hwaddr(lp);
3576 ret = at91ether_start(dev);
3577 if (ret)
3578 return ret;
3580 /* Enable MAC interrupts */
3581 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3582 MACB_BIT(RXUBR) |
3583 MACB_BIT(ISR_TUND) |
3584 MACB_BIT(ISR_RLE) |
3585 MACB_BIT(TCOMP) |
3586 MACB_BIT(ISR_ROVR) |
3587 MACB_BIT(HRESP));
3589 /* schedule a link state check */
3590 phy_start(dev->phydev);
3592 netif_start_queue(dev);
3594 return 0;
3595 }
3597 /* Close the interface */
3598 static int at91ether_close(struct net_device *dev)
3599 {
3600 struct macb *lp = netdev_priv(dev);
3601 struct macb_queue *q = &lp->queues[0];
3602 u32 ctl;
3604 /* Disable Receiver and Transmitter */
3605 ctl = macb_readl(lp, NCR);
3606 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3608 /* Disable MAC interrupts */
3609 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3610 MACB_BIT(RXUBR) |
3611 MACB_BIT(ISR_TUND) |
3612 MACB_BIT(ISR_RLE) |
3613 MACB_BIT(TCOMP) |
3614 MACB_BIT(ISR_ROVR) |
3615 MACB_BIT(HRESP));
3617 netif_stop_queue(dev);
3619 dma_free_coherent(&lp->pdev->dev,
3620 AT91ETHER_MAX_RX_DESCR *
3621 macb_dma_desc_get_size(lp),
3622 q->rx_ring, q->rx_ring_dma);
3623 q->rx_ring = NULL;
3625 dma_free_coherent(&lp->pdev->dev,
3626 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3627 q->rx_buffers, q->rx_buffers_dma);
3628 q->rx_buffers = NULL;
3630 return 0;
3631 }
3633 /* Transmit packet */
3634 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3635 struct net_device *dev)
3636 {
3637 struct macb *lp = netdev_priv(dev);
3639 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3640 netif_stop_queue(dev);
3642 /* Store packet information (to free when Tx completed) */
3643 lp->skb = skb;
3644 lp->skb_length = skb->len;
3645 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3646 DMA_TO_DEVICE);
3647 if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3648 dev_kfree_skb_any(skb);
3649 dev->stats.tx_dropped++;
3650 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3651 return NETDEV_TX_OK;
3652 }
3654 /* Set address of the data in the Transmit Address register */
3655 macb_writel(lp, TAR, lp->skb_physaddr);
3656 /* Set length of the packet in the Transmit Control register */
3657 macb_writel(lp, TCR, skb->len);
3659 } else {
3660 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3661 return NETDEV_TX_BUSY;
3662 }
3664 return NETDEV_TX_OK;
3665 }
3667 /* Extract received frame from buffer descriptors and sent to upper layers.
3668 * (Called from interrupt context)
3669 */
3670 static void at91ether_rx(struct net_device *dev)
3671 {
3672 struct macb *lp = netdev_priv(dev);
3673 struct macb_queue *q = &lp->queues[0];
3674 struct macb_dma_desc *desc;
3675 unsigned char *p_recv;
3676 struct sk_buff *skb;
3677 unsigned int pktlen;
3679 desc = macb_rx_desc(q, q->rx_tail);
3680 while (desc->addr & MACB_BIT(RX_USED)) {
3681 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3682 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3683 skb = netdev_alloc_skb(dev, pktlen + 2);
3684 if (skb) {
3685 skb_reserve(skb, 2);
3686 skb_put_data(skb, p_recv, pktlen);
3688 skb->protocol = eth_type_trans(skb, dev);
3689 dev->stats.rx_packets++;
3690 dev->stats.rx_bytes += pktlen;
3691 netif_rx(skb);
3692 } else {
3693 dev->stats.rx_dropped++;
3694 }
3696 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3697 dev->stats.multicast++;
3699 /* reset ownership bit */
3700 desc->addr &= ~MACB_BIT(RX_USED);
3702 /* wrap after last buffer */
3703 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3704 q->rx_tail = 0;
3705 else
3706 q->rx_tail++;
3708 desc = macb_rx_desc(q, q->rx_tail);
3709 }
3710 }
3712 /* MAC interrupt handler */
3713 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3714 {
3715 struct net_device *dev = dev_id;
3716 struct macb *lp = netdev_priv(dev);
3717 u32 intstatus, ctl;
3719 /* MAC Interrupt Status register indicates what interrupts are pending.
3720 * It is automatically cleared once read.
3721 */
3722 intstatus = macb_readl(lp, ISR);
3724 /* Receive complete */
3725 if (intstatus & MACB_BIT(RCOMP))
3726 at91ether_rx(dev);
3728 /* Transmit complete */
3729 if (intstatus & MACB_BIT(TCOMP)) {
3730 /* The TCOM bit is set even if the transmission failed */
3731 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3732 dev->stats.tx_errors++;
3734 if (lp->skb) {
3735 dev_kfree_skb_irq(lp->skb);
3736 lp->skb = NULL;
3737 dma_unmap_single(NULL, lp->skb_physaddr,
3738 lp->skb_length, DMA_TO_DEVICE);
3739 dev->stats.tx_packets++;
3740 dev->stats.tx_bytes += lp->skb_length;
3741 }
3742 netif_wake_queue(dev);
3743 }
3745 /* Work-around for EMAC Errata section 41.3.1 */
3746 if (intstatus & MACB_BIT(RXUBR)) {
3747 ctl = macb_readl(lp, NCR);
3748 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3749 wmb();
3750 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3751 }
3753 if (intstatus & MACB_BIT(ISR_ROVR))
3754 netdev_err(dev, "ROVR error\n");
3756 return IRQ_HANDLED;
3757 }
3759 #ifdef CONFIG_NET_POLL_CONTROLLER
3760 static void at91ether_poll_controller(struct net_device *dev)
3761 {
3762 unsigned long flags;
3764 local_irq_save(flags);
3765 at91ether_interrupt(dev->irq, dev);
3766 local_irq_restore(flags);
3767 }
3768 #endif
3770 static const struct net_device_ops at91ether_netdev_ops = {
3771 .ndo_open = at91ether_open,
3772 .ndo_stop = at91ether_close,
3773 .ndo_start_xmit = at91ether_start_xmit,
3774 .ndo_get_stats = macb_get_stats,
3775 .ndo_set_rx_mode = macb_set_rx_mode,
3776 .ndo_set_mac_address = eth_mac_addr,
3777 .ndo_do_ioctl = macb_ioctl,
3778 .ndo_validate_addr = eth_validate_addr,
3779 #ifdef CONFIG_NET_POLL_CONTROLLER
3780 .ndo_poll_controller = at91ether_poll_controller,
3781 #endif
3782 };
3784 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3785 struct clk **hclk, struct clk **tx_clk,
3786 struct clk **rx_clk)
3787 {
3788 int err;
3790 *hclk = NULL;
3791 *tx_clk = NULL;
3792 *rx_clk = NULL;
3794 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3795 if (IS_ERR(*pclk))
3796 return PTR_ERR(*pclk);
3798 err = clk_prepare_enable(*pclk);
3799 if (err) {
3800 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3801 return err;
3802 }
3804 return 0;
3805 }
3807 static int at91ether_init(struct platform_device *pdev)
3808 {
3809 struct net_device *dev = platform_get_drvdata(pdev);
3810 struct macb *bp = netdev_priv(dev);
3811 int err;
3812 u32 reg;
3814 bp->queues[0].bp = bp;
3816 dev->netdev_ops = &at91ether_netdev_ops;
3817 dev->ethtool_ops = &macb_ethtool_ops;
3819 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3820 0, dev->name, dev);
3821 if (err)
3822 return err;
3824 macb_writel(bp, NCR, 0);
3826 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3827 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3828 reg |= MACB_BIT(RM9200_RMII);
3830 macb_writel(bp, NCFGR, reg);
3832 return 0;
3833 }
3835 static const struct macb_config at91sam9260_config = {
3836 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3837 .clk_init = macb_clk_init,
3838 .init = macb_init,
3839 };
3841 static const struct macb_config sama5d3macb_config = {
3842 .caps = MACB_CAPS_SG_DISABLED
3843 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3844 .clk_init = macb_clk_init,
3845 .init = macb_init,
3846 };
3848 static const struct macb_config pc302gem_config = {
3849 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3850 .dma_burst_length = 16,
3851 .clk_init = macb_clk_init,
3852 .init = macb_init,
3853 };
3855 static const struct macb_config sama5d2_config = {
3856 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3857 .dma_burst_length = 16,
3858 .clk_init = macb_clk_init,
3859 .init = macb_init,
3860 };
3862 static const struct macb_config sama5d3_config = {
3863 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3864 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3865 .dma_burst_length = 16,
3866 .clk_init = macb_clk_init,
3867 .init = macb_init,
3868 .jumbo_max_len = 10240,
3869 };
3871 static const struct macb_config sama5d4_config = {
3872 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3873 .dma_burst_length = 4,
3874 .clk_init = macb_clk_init,
3875 .init = macb_init,
3876 };
3878 static const struct macb_config emac_config = {
3879 .clk_init = at91ether_clk_init,
3880 .init = at91ether_init,
3881 };
3883 static const struct macb_config np4_config = {
3884 .caps = MACB_CAPS_USRIO_DISABLED,
3885 .clk_init = macb_clk_init,
3886 .init = macb_init,
3887 };
3889 static const struct macb_config zynqmp_config = {
3890 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3891 MACB_CAPS_JUMBO |
3892 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
3893 .dma_burst_length = 16,
3894 .clk_init = macb_clk_init,
3895 .init = macb_init,
3896 .jumbo_max_len = 10240,
3897 };
3899 static const struct macb_config zynq_config = {
3900 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
3901 .dma_burst_length = 16,
3902 .clk_init = macb_clk_init,
3903 .init = macb_init,
3904 };
3906 static const struct of_device_id macb_dt_ids[] = {
3907 { .compatible = "cdns,at32ap7000-macb" },
3908 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3909 { .compatible = "cdns,macb" },
3910 { .compatible = "cdns,np4-macb", .data = &np4_config },
3911 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3912 { .compatible = "cdns,gem", .data = &pc302gem_config },
3913 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3914 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3915 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
3916 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3917 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3918 { .compatible = "cdns,emac", .data = &emac_config },
3919 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3920 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
3921 { /* sentinel */ }
3922 };
3923 MODULE_DEVICE_TABLE(of, macb_dt_ids);
3924 #endif /* CONFIG_OF */
3926 static const struct macb_config default_gem_config = {
3927 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3928 MACB_CAPS_JUMBO |
3929 MACB_CAPS_GEM_HAS_PTP,
3930 .dma_burst_length = 16,
3931 .clk_init = macb_clk_init,
3932 .init = macb_init,
3933 .jumbo_max_len = 10240,
3934 };
3936 static int macb_probe(struct platform_device *pdev)
3937 {
3938 const struct macb_config *macb_config = &default_gem_config;
3939 int (*clk_init)(struct platform_device *, struct clk **,
3940 struct clk **, struct clk **, struct clk **)
3941 = macb_config->clk_init;
3942 int (*init)(struct platform_device *) = macb_config->init;
3943 struct device_node *np = pdev->dev.of_node;
3944 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3945 unsigned int queue_mask, num_queues;
3946 struct macb_platform_data *pdata;
3947 bool native_io;
3948 struct phy_device *phydev;
3949 struct net_device *dev;
3950 struct resource *regs;
3951 void __iomem *mem;
3952 const char *mac;
3953 struct macb *bp;
3954 int err, val;
3956 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3957 mem = devm_ioremap_resource(&pdev->dev, regs);
3958 if (IS_ERR(mem))
3959 return PTR_ERR(mem);
3961 if (np) {
3962 const struct of_device_id *match;
3964 match = of_match_node(macb_dt_ids, np);
3965 if (match && match->data) {
3966 macb_config = match->data;
3967 clk_init = macb_config->clk_init;
3968 init = macb_config->init;
3969 }
3970 }
3972 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
3973 if (err)
3974 return err;
3976 native_io = hw_is_native_io(mem);
3978 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
3979 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
3980 if (!dev) {
3981 err = -ENOMEM;
3982 goto err_disable_clocks;
3983 }
3985 dev->base_addr = regs->start;
3987 SET_NETDEV_DEV(dev, &pdev->dev);
3989 bp = netdev_priv(dev);
3990 bp->pdev = pdev;
3991 bp->dev = dev;
3992 bp->regs = mem;
3993 bp->native_io = native_io;
3994 if (native_io) {
3995 bp->macb_reg_readl = hw_readl_native;
3996 bp->macb_reg_writel = hw_writel_native;
3997 } else {
3998 bp->macb_reg_readl = hw_readl;
3999 bp->macb_reg_writel = hw_writel;
4000 }
4001 bp->num_queues = num_queues;
4002 bp->queue_mask = queue_mask;
4003 if (macb_config)
4004 bp->dma_burst_length = macb_config->dma_burst_length;
4005 bp->pclk = pclk;
4006 bp->hclk = hclk;
4007 bp->tx_clk = tx_clk;
4008 bp->rx_clk = rx_clk;
4009 if (macb_config)
4010 bp->jumbo_max_len = macb_config->jumbo_max_len;
4012 bp->wol = 0;
4013 if (of_get_property(np, "magic-packet", NULL))
4014 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4015 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4017 spin_lock_init(&bp->lock);
4019 /* setup capabilities */
4020 macb_configure_caps(bp, macb_config);
4022 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4023 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4024 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4025 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4026 }
4027 #endif
4028 platform_set_drvdata(pdev, dev);
4030 dev->irq = platform_get_irq(pdev, 0);
4031 if (dev->irq < 0) {
4032 err = dev->irq;
4033 goto err_out_free_netdev;
4034 }
4036 /* MTU range: 68 - 1500 or 10240 */
4037 dev->min_mtu = GEM_MTU_MIN_SIZE;
4038 if (bp->caps & MACB_CAPS_JUMBO)
4039 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4040 else
4041 dev->max_mtu = ETH_DATA_LEN;
4043 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4044 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4045 if (val)
4046 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4047 macb_dma_desc_get_size(bp);
4049 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4050 if (val)
4051 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4052 macb_dma_desc_get_size(bp);
4053 }
4055 mac = of_get_mac_address(np);
4056 if (mac) {
4057 ether_addr_copy(bp->dev->dev_addr, mac);
4058 } else {
4059 err = of_get_nvmem_mac_address(np, bp->dev->dev_addr);
4060 if (err) {
4061 if (err == -EPROBE_DEFER)
4062 goto err_out_free_netdev;
4063 macb_get_hwaddr(bp);
4064 }
4065 }
4067 err = of_get_phy_mode(np);
4068 if (err < 0) {
4069 pdata = dev_get_platdata(&pdev->dev);
4070 if (pdata && pdata->is_rmii)
4071 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
4072 else
4073 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4074 } else {
4075 bp->phy_interface = err;
4076 }
4078 /* IP specific init */
4079 err = init(pdev);
4080 if (err)
4081 goto err_out_free_netdev;
4083 err = macb_mii_init(bp);
4084 if (err)
4085 goto err_out_free_netdev;
4087 phydev = dev->phydev;
4089 netif_carrier_off(dev);
4091 err = register_netdev(dev);
4092 if (err) {
4093 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4094 goto err_out_unregister_mdio;
4095 }
4097 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4098 (unsigned long)bp);
4100 phy_attached_info(phydev);
4102 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4103 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4104 dev->base_addr, dev->irq, dev->dev_addr);
4106 return 0;
4108 err_out_unregister_mdio:
4109 phy_disconnect(dev->phydev);
4110 mdiobus_unregister(bp->mii_bus);
4111 of_node_put(bp->phy_node);
4112 if (np && of_phy_is_fixed_link(np))
4113 of_phy_deregister_fixed_link(np);
4114 mdiobus_free(bp->mii_bus);
4116 err_out_free_netdev:
4117 free_netdev(dev);
4119 err_disable_clocks:
4120 clk_disable_unprepare(tx_clk);
4121 clk_disable_unprepare(hclk);
4122 clk_disable_unprepare(pclk);
4123 clk_disable_unprepare(rx_clk);
4125 return err;
4126 }
4128 static int macb_remove(struct platform_device *pdev)
4129 {
4130 struct net_device *dev;
4131 struct macb *bp;
4132 struct device_node *np = pdev->dev.of_node;
4134 dev = platform_get_drvdata(pdev);
4136 if (dev) {
4137 bp = netdev_priv(dev);
4138 if (dev->phydev)
4139 phy_disconnect(dev->phydev);
4140 mdiobus_unregister(bp->mii_bus);
4141 if (np && of_phy_is_fixed_link(np))
4142 of_phy_deregister_fixed_link(np);
4143 dev->phydev = NULL;
4144 mdiobus_free(bp->mii_bus);
4146 unregister_netdev(dev);
4147 clk_disable_unprepare(bp->tx_clk);
4148 clk_disable_unprepare(bp->hclk);
4149 clk_disable_unprepare(bp->pclk);
4150 clk_disable_unprepare(bp->rx_clk);
4151 of_node_put(bp->phy_node);
4152 free_netdev(dev);
4153 }
4155 return 0;
4156 }
4158 static int __maybe_unused macb_suspend(struct device *dev)
4159 {
4160 struct platform_device *pdev = to_platform_device(dev);
4161 struct net_device *netdev = platform_get_drvdata(pdev);
4162 struct macb *bp = netdev_priv(netdev);
4164 netif_carrier_off(netdev);
4165 netif_device_detach(netdev);
4167 if (bp->wol & MACB_WOL_ENABLED) {
4168 macb_writel(bp, IER, MACB_BIT(WOL));
4169 macb_writel(bp, WOL, MACB_BIT(MAG));
4170 enable_irq_wake(bp->queues[0].irq);
4171 } else {
4172 clk_disable_unprepare(bp->tx_clk);
4173 clk_disable_unprepare(bp->hclk);
4174 clk_disable_unprepare(bp->pclk);
4175 clk_disable_unprepare(bp->rx_clk);
4176 }
4178 return 0;
4179 }
4181 static int __maybe_unused macb_resume(struct device *dev)
4182 {
4183 struct platform_device *pdev = to_platform_device(dev);
4184 struct net_device *netdev = platform_get_drvdata(pdev);
4185 struct macb *bp = netdev_priv(netdev);
4187 if (bp->wol & MACB_WOL_ENABLED) {
4188 macb_writel(bp, IDR, MACB_BIT(WOL));
4189 macb_writel(bp, WOL, 0);
4190 disable_irq_wake(bp->queues[0].irq);
4191 } else {
4192 clk_prepare_enable(bp->pclk);
4193 clk_prepare_enable(bp->hclk);
4194 clk_prepare_enable(bp->tx_clk);
4195 clk_prepare_enable(bp->rx_clk);
4196 }
4198 netif_device_attach(netdev);
4200 return 0;
4201 }
4203 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
4205 static struct platform_driver macb_driver = {
4206 .probe = macb_probe,
4207 .remove = macb_remove,
4208 .driver = {
4209 .name = "macb",
4210 .of_match_table = of_match_ptr(macb_dt_ids),
4211 .pm = &macb_pm_ops,
4212 },
4213 };
4215 module_platform_driver(macb_driver);
4217 MODULE_LICENSE("GPL");
4218 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4219 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4220 MODULE_ALIAS("platform:macb");