drivers/net/ethernet/mellanox/mlxsw/pci.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/export.h>
   7 #include <linux/err.h>
   8 #include <linux/device.h>
   9 #include <linux/pci.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/wait.h>
  12 #include <linux/types.h>
  13 #include <linux/skbuff.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/log2.h>
  16 #include <linux/string.h>
  17
  18 #include "pci_hw.h"
  19 #include "pci.h"
  20 #include "core.h"
  21 #include "cmd.h"
  22 #include "port.h"
  23 #include "resources.h"
  24
  25 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
  26         iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  27 #define mlxsw_pci_read32(mlxsw_pci, reg) \
  28         ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  29
  30 enum mlxsw_pci_queue_type {
  31         MLXSW_PCI_QUEUE_TYPE_SDQ,
  32         MLXSW_PCI_QUEUE_TYPE_RDQ,
  33         MLXSW_PCI_QUEUE_TYPE_CQ,
  34         MLXSW_PCI_QUEUE_TYPE_EQ,
  35 };
  36
  37 #define MLXSW_PCI_QUEUE_TYPE_COUNT      4
  38
  39 static const u16 mlxsw_pci_doorbell_type_offset[] = {
  40         MLXSW_PCI_DOORBELL_SDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
  41         MLXSW_PCI_DOORBELL_RDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
  42         MLXSW_PCI_DOORBELL_CQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
  43         MLXSW_PCI_DOORBELL_EQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
  44 };
  45
  46 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
  47         0, /* unused */
  48         0, /* unused */
  49         MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
  50         MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
  51 };
  52
  53 struct mlxsw_pci_mem_item {
  54         char *buf;
  55         dma_addr_t mapaddr;
  56         size_t size;
  57 };
  58
  59 struct mlxsw_pci_queue_elem_info {
  60         char *elem; /* pointer to actual dma mapped element mem chunk */
  61         union {
  62                 struct {
  63                         struct sk_buff *skb;
  64                 } sdq;
  65                 struct {
  66                         struct sk_buff *skb;
  67                 } rdq;
  68         } u;
  69 };
  70
  71 struct mlxsw_pci_queue {
  72         spinlock_t lock; /* for queue accesses */
  73         struct mlxsw_pci_mem_item mem_item;
  74         struct mlxsw_pci_queue_elem_info *elem_info;
  75         u16 producer_counter;
  76         u16 consumer_counter;
  77         u16 count; /* number of elements in queue */
  78         u8 num; /* queue number */
  79         u8 elem_size; /* size of one element */
  80         enum mlxsw_pci_queue_type type;
  81         struct tasklet_struct tasklet; /* queue processing tasklet */
  82         struct mlxsw_pci *pci;
  83         union {
  84                 struct {
  85                         u32 comp_sdq_count;
  86                         u32 comp_rdq_count;
  87                         enum mlxsw_pci_cqe_v v;
  88                 } cq;
  89                 struct {
  90                         u32 ev_cmd_count;
  91                         u32 ev_comp_count;
  92                         u32 ev_other_count;
  93                 } eq;
  94         } u;
  95 };
  96
  97 struct mlxsw_pci_queue_type_group {
  98         struct mlxsw_pci_queue *q;
  99         u8 count; /* number of queues in group */
 100 };
 101
 102 struct mlxsw_pci {
 103         struct pci_dev *pdev;
 104         u8 __iomem *hw_addr;
 105         struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
 106         u32 doorbell_offset;
 107         struct mlxsw_core *core;
 108         struct {
 109                 struct mlxsw_pci_mem_item *items;
 110                 unsigned int count;
 111         } fw_area;
 112         struct {
 113                 struct mlxsw_pci_mem_item out_mbox;
 114                 struct mlxsw_pci_mem_item in_mbox;
 115                 struct mutex lock; /* Lock access to command registers */
 116                 bool nopoll;
 117                 wait_queue_head_t wait;
 118                 bool wait_done;
 119                 struct {
 120                         u8 status;
 121                         u64 out_param;
 122                 } comp;
 123         } cmd;
 124         struct mlxsw_bus_info bus_info;
 125         const struct pci_device_id *id;
 126         enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */
 127         u8 num_sdq_cqs; /* Number of CQs used for SDQs */
 128 };
 129
 130 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
 131 {
 132         tasklet_schedule(&q->tasklet);
 133 }
 134
 135 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
 136                                         size_t elem_size, int elem_index)
 137 {
 138         return q->mem_item.buf + (elem_size * elem_index);
 139 }
 140
 141 static struct mlxsw_pci_queue_elem_info *
 142 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
 143 {
 144         return &q->elem_info[elem_index];
 145 }
 146
 147 static struct mlxsw_pci_queue_elem_info *
 148 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
 149 {
 150         int index = q->producer_counter & (q->count - 1);
 151
 152         if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
 153                 return NULL;
 154         return mlxsw_pci_queue_elem_info_get(q, index);
 155 }
 156
 157 static struct mlxsw_pci_queue_elem_info *
 158 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
 159 {
 160         int index = q->consumer_counter & (q->count - 1);
 161
 162         return mlxsw_pci_queue_elem_info_get(q, index);
 163 }
 164
 165 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
 166 {
 167         return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
 168 }
 169
 170 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
 171 {
 172         return owner_bit != !!(q->consumer_counter & q->count);
 173 }
 174
 175 static struct mlxsw_pci_queue_type_group *
 176 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
 177                                enum mlxsw_pci_queue_type q_type)
 178 {
 179         return &mlxsw_pci->queues[q_type];
 180 }
 181
 182 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
 183                                   enum mlxsw_pci_queue_type q_type)
 184 {
 185         struct mlxsw_pci_queue_type_group *queue_group;
 186
 187         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
 188         return queue_group->count;
 189 }
 190
 191 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
 192 {
 193         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
 194 }
 195
 196 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
 197 {
 198         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
 199 }
 200
 201 static struct mlxsw_pci_queue *
 202 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
 203                       enum mlxsw_pci_queue_type q_type, u8 q_num)
 204 {
 205         return &mlxsw_pci->queues[q_type].q[q_num];
 206 }
 207
 208 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
 209                                                  u8 q_num)
 210 {
 211         return __mlxsw_pci_queue_get(mlxsw_pci,
 212                                      MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
 213 }
 214
 215 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
 216                                                  u8 q_num)
 217 {
 218         return __mlxsw_pci_queue_get(mlxsw_pci,
 219                                      MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
 220 }
 221
 222 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
 223                                                 u8 q_num)
 224 {
 225         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
 226 }
 227
 228 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
 229                                                 u8 q_num)
 230 {
 231         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
 232 }
 233
 234 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
 235                                            struct mlxsw_pci_queue *q,
 236                                            u16 val)
 237 {
 238         mlxsw_pci_write32(mlxsw_pci,
 239                           DOORBELL(mlxsw_pci->doorbell_offset,
 240                                    mlxsw_pci_doorbell_type_offset[q->type],
 241                                    q->num), val);
 242 }
 243
 244 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
 245                                                struct mlxsw_pci_queue *q,
 246                                                u16 val)
 247 {
 248         mlxsw_pci_write32(mlxsw_pci,
 249                           DOORBELL(mlxsw_pci->doorbell_offset,
 250                                    mlxsw_pci_doorbell_arm_type_offset[q->type],
 251                                    q->num), val);
 252 }
 253
 254 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
 255                                                    struct mlxsw_pci_queue *q)
 256 {
 257         wmb(); /* ensure all writes are done before we ring a bell */
 258         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
 259 }
 260
 261 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 262                                                    struct mlxsw_pci_queue *q)
 263 {
 264         wmb(); /* ensure all writes are done before we ring a bell */
 265         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
 266                                        q->consumer_counter + q->count);
 267 }
 268
 269 static void
 270 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 271                                            struct mlxsw_pci_queue *q)
 272 {
 273         wmb(); /* ensure all writes are done before we ring a bell */
 274         __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
 275 }
 276
 277 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
 278                                              int page_index)
 279 {
 280         return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
 281 }
 282
 283 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 284                               struct mlxsw_pci_queue *q)
 285 {
 286         int i;
 287         int err;
 288
 289         q->producer_counter = 0;
 290         q->consumer_counter = 0;
 291
 292         /* Set CQ of same number of this SDQ. */
 293         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
 294         mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3);
 295         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 296         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 297                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 298
 299                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 300         }
 301
 302         err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
 303         if (err)
 304                 return err;
 305         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 306         return 0;
 307 }
 308
 309 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
 310                                struct mlxsw_pci_queue *q)
 311 {
 312         mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
 313 }
 314
 315 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
 316                                   int index, char *frag_data, size_t frag_len,
 317                                   int direction)
 318 {
 319         struct pci_dev *pdev = mlxsw_pci->pdev;
 320         dma_addr_t mapaddr;
 321
 322         mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
 323         if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
 324                 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
 325                 return -EIO;
 326         }
 327         mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
 328         mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
 329         return 0;
 330 }
 331
 332 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
 333                                      int index, int direction)
 334 {
 335         struct pci_dev *pdev = mlxsw_pci->pdev;
 336         size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
 337         dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
 338
 339         if (!frag_len)
 340                 return;
 341         pci_unmap_single(pdev, mapaddr, frag_len, direction);
 342 }
 343
 344 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
 345                                    struct mlxsw_pci_queue_elem_info *elem_info)
 346 {
 347         size_t buf_len = MLXSW_PORT_MAX_MTU;
 348         char *wqe = elem_info->elem;
 349         struct sk_buff *skb;
 350         int err;
 351
 352         elem_info->u.rdq.skb = NULL;
 353         skb = netdev_alloc_skb_ip_align(NULL, buf_len);
 354         if (!skb)
 355                 return -ENOMEM;
 356
 357         /* Assume that wqe was previously zeroed. */
 358
 359         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
 360                                      buf_len, DMA_FROM_DEVICE);
 361         if (err)
 362                 goto err_frag_map;
 363
 364         elem_info->u.rdq.skb = skb;
 365         return 0;
 366
 367 err_frag_map:
 368         dev_kfree_skb_any(skb);
 369         return err;
 370 }
 371
 372 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
 373                                    struct mlxsw_pci_queue_elem_info *elem_info)
 374 {
 375         struct sk_buff *skb;
 376         char *wqe;
 377
 378         skb = elem_info->u.rdq.skb;
 379         wqe = elem_info->elem;
 380
 381         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 382         dev_kfree_skb_any(skb);
 383 }
 384
 385 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 386                               struct mlxsw_pci_queue *q)
 387 {
 388         struct mlxsw_pci_queue_elem_info *elem_info;
 389         u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
 390         int i;
 391         int err;
 392
 393         q->producer_counter = 0;
 394         q->consumer_counter = 0;
 395
 396         /* Set CQ of same number of this RDQ with base
 397          * above SDQ count as the lower ones are assigned to SDQs.
 398          */
 399         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
 400         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 401         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 402                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 403
 404                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 405         }
 406
 407         err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
 408         if (err)
 409                 return err;
 410
 411         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 412
 413         for (i = 0; i < q->count; i++) {
 414                 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
 415                 BUG_ON(!elem_info);
 416                 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 417                 if (err)
 418                         goto rollback;
 419                 /* Everything is set up, ring doorbell to pass elem to HW */
 420                 q->producer_counter++;
 421                 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 422         }
 423
 424         return 0;
 425
 426 rollback:
 427         for (i--; i >= 0; i--) {
 428                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 429                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 430         }
 431         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 432
 433         return err;
 434 }
 435
 436 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
 437                                struct mlxsw_pci_queue *q)
 438 {
 439         struct mlxsw_pci_queue_elem_info *elem_info;
 440         int i;
 441
 442         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 443         for (i = 0; i < q->count; i++) {
 444                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 445                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 446         }
 447 }
 448
 449 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci,
 450                                   struct mlxsw_pci_queue *q)
 451 {
 452         q->u.cq.v = mlxsw_pci->max_cqe_ver;
 453
 454         /* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */
 455         if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
 456             q->num < mlxsw_pci->num_sdq_cqs)
 457                 q->u.cq.v = MLXSW_PCI_CQE_V1;
 458 }
 459
 460 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 461                              struct mlxsw_pci_queue *q)
 462 {
 463         int i;
 464         int err;
 465
 466         q->consumer_counter = 0;
 467
 468         for (i = 0; i < q->count; i++) {
 469                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 470
 471                 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
 472         }
 473
 474         if (q->u.cq.v == MLXSW_PCI_CQE_V1)
 475                 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
 476                                 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1);
 477         else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
 478                 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
 479                                 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2);
 480
 481         mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
 482         mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
 483         mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
 484         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 485                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 486
 487                 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
 488         }
 489         err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
 490         if (err)
 491                 return err;
 492         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 493         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 494         return 0;
 495 }
 496
 497 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
 498                               struct mlxsw_pci_queue *q)
 499 {
 500         mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 501 }
 502
 503 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
 504                                      struct mlxsw_pci_queue *q,
 505                                      u16 consumer_counter_limit,
 506                                      char *cqe)
 507 {
 508         struct pci_dev *pdev = mlxsw_pci->pdev;
 509         struct mlxsw_pci_queue_elem_info *elem_info;
 510         char *wqe;
 511         struct sk_buff *skb;
 512         int i;
 513
 514         spin_lock(&q->lock);
 515         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 516         skb = elem_info->u.sdq.skb;
 517         wqe = elem_info->elem;
 518         for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
 519                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
 520         dev_kfree_skb_any(skb);
 521         elem_info->u.sdq.skb = NULL;
 522
 523         if (q->consumer_counter++ != consumer_counter_limit)
 524                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
 525         spin_unlock(&q->lock);
 526 }
 527
 528 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
 529                                      struct mlxsw_pci_queue *q,
 530                                      u16 consumer_counter_limit,
 531                                      enum mlxsw_pci_cqe_v cqe_v, char *cqe)
 532 {
 533         struct pci_dev *pdev = mlxsw_pci->pdev;
 534         struct mlxsw_pci_queue_elem_info *elem_info;
 535         char *wqe;
 536         struct sk_buff *skb;
 537         struct mlxsw_rx_info rx_info;
 538         u16 byte_count;
 539         int err;
 540
 541         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 542         skb = elem_info->u.sdq.skb;
 543         if (!skb)
 544                 return;
 545         wqe = elem_info->elem;
 546         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 547
 548         if (q->consumer_counter++ != consumer_counter_limit)
 549                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
 550
 551         if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) {
 552                 rx_info.is_lag = true;
 553                 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe);
 554                 rx_info.lag_port_index =
 555                         mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe);
 556         } else {
 557                 rx_info.is_lag = false;
 558                 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
 559         }
 560
 561         rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
 562
 563         byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
 564         if (mlxsw_pci_cqe_crc_get(cqe_v, cqe))
 565                 byte_count -= ETH_FCS_LEN;
 566         skb_put(skb, byte_count);
 567         mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
 568
 569         memset(wqe, 0, q->elem_size);
 570         err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 571         if (err)
 572                 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
 573         /* Everything is set up, ring doorbell to pass elem to HW */
 574         q->producer_counter++;
 575         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 576         return;
 577 }
 578
 579 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
 580 {
 581         struct mlxsw_pci_queue_elem_info *elem_info;
 582         char *elem;
 583         bool owner_bit;
 584
 585         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 586         elem = elem_info->elem;
 587         owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem);
 588         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 589                 return NULL;
 590         q->consumer_counter++;
 591         rmb(); /* make sure we read owned bit before the rest of elem */
 592         return elem;
 593 }
 594
 595 static void mlxsw_pci_cq_tasklet(unsigned long data)
 596 {
 597         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 598         struct mlxsw_pci *mlxsw_pci = q->pci;
 599         char *cqe;
 600         int items = 0;
 601         int credits = q->count >> 1;
 602
 603         while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
 604                 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
 605                 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
 606                 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
 607
 608                 if (sendq) {
 609                         struct mlxsw_pci_queue *sdq;
 610
 611                         sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
 612                         mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
 613                                                  wqe_counter, cqe);
 614                         q->u.cq.comp_sdq_count++;
 615                 } else {
 616                         struct mlxsw_pci_queue *rdq;
 617
 618                         rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
 619                         mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
 620                                                  wqe_counter, q->u.cq.v, cqe);
 621                         q->u.cq.comp_rdq_count++;
 622                 }
 623                 if (++items == credits)
 624                         break;
 625         }
 626         if (items) {
 627                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 628                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 629         }
 630 }
 631
 632 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q)
 633 {
 634         return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
 635                                                MLXSW_PCI_CQE01_COUNT;
 636 }
 637
 638 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q)
 639 {
 640         return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
 641                                                MLXSW_PCI_CQE01_SIZE;
 642 }
 643
 644 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 645                              struct mlxsw_pci_queue *q)
 646 {
 647         int i;
 648         int err;
 649
 650         q->consumer_counter = 0;
 651
 652         for (i = 0; i < q->count; i++) {
 653                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 654
 655                 mlxsw_pci_eqe_owner_set(elem, 1);
 656         }
 657
 658         mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
 659         mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
 660         mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
 661         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 662                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 663
 664                 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
 665         }
 666         err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
 667         if (err)
 668                 return err;
 669         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 670         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 671         return 0;
 672 }
 673
 674 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
 675                               struct mlxsw_pci_queue *q)
 676 {
 677         mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
 678 }
 679
 680 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
 681 {
 682         mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
 683         mlxsw_pci->cmd.comp.out_param =
 684                 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
 685                 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
 686         mlxsw_pci->cmd.wait_done = true;
 687         wake_up(&mlxsw_pci->cmd.wait);
 688 }
 689
 690 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
 691 {
 692         struct mlxsw_pci_queue_elem_info *elem_info;
 693         char *elem;
 694         bool owner_bit;
 695
 696         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 697         elem = elem_info->elem;
 698         owner_bit = mlxsw_pci_eqe_owner_get(elem);
 699         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 700                 return NULL;
 701         q->consumer_counter++;
 702         rmb(); /* make sure we read owned bit before the rest of elem */
 703         return elem;
 704 }
 705
 706 static void mlxsw_pci_eq_tasklet(unsigned long data)
 707 {
 708         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 709         struct mlxsw_pci *mlxsw_pci = q->pci;
 710         u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
 711         unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
 712         char *eqe;
 713         u8 cqn;
 714         bool cq_handle = false;
 715         int items = 0;
 716         int credits = q->count >> 1;
 717
 718         memset(&active_cqns, 0, sizeof(active_cqns));
 719
 720         while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
 721
 722                 /* Command interface completion events are always received on
 723                  * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events
 724                  * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1).
 725                  */
 726                 switch (q->num) {
 727                 case MLXSW_PCI_EQ_ASYNC_NUM:
 728                         mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
 729                         q->u.eq.ev_cmd_count++;
 730                         break;
 731                 case MLXSW_PCI_EQ_COMP_NUM:
 732                         cqn = mlxsw_pci_eqe_cqn_get(eqe);
 733                         set_bit(cqn, active_cqns);
 734                         cq_handle = true;
 735                         q->u.eq.ev_comp_count++;
 736                         break;
 737                 default:
 738                         q->u.eq.ev_other_count++;
 739                 }
 740                 if (++items == credits)
 741                         break;
 742         }
 743         if (items) {
 744                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 745                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 746         }
 747
 748         if (!cq_handle)
 749                 return;
 750         for_each_set_bit(cqn, active_cqns, cq_count) {
 751                 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
 752                 mlxsw_pci_queue_tasklet_schedule(q);
 753         }
 754 }
 755
 756 struct mlxsw_pci_queue_ops {
 757         const char *name;
 758         enum mlxsw_pci_queue_type type;
 759         void (*pre_init)(struct mlxsw_pci *mlxsw_pci,
 760                          struct mlxsw_pci_queue *q);
 761         int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
 762                     struct mlxsw_pci_queue *q);
 763         void (*fini)(struct mlxsw_pci *mlxsw_pci,
 764                      struct mlxsw_pci_queue *q);
 765         void (*tasklet)(unsigned long data);
 766         u16 (*elem_count_f)(const struct mlxsw_pci_queue *q);
 767         u8 (*elem_size_f)(const struct mlxsw_pci_queue *q);
 768         u16 elem_count;
 769         u8 elem_size;
 770 };
 771
 772 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
 773         .type           = MLXSW_PCI_QUEUE_TYPE_SDQ,
 774         .init           = mlxsw_pci_sdq_init,
 775         .fini           = mlxsw_pci_sdq_fini,
 776         .elem_count     = MLXSW_PCI_WQE_COUNT,
 777         .elem_size      = MLXSW_PCI_WQE_SIZE,
 778 };
 779
 780 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
 781         .type           = MLXSW_PCI_QUEUE_TYPE_RDQ,
 782         .init           = mlxsw_pci_rdq_init,
 783         .fini           = mlxsw_pci_rdq_fini,
 784         .elem_count     = MLXSW_PCI_WQE_COUNT,
 785         .elem_size      = MLXSW_PCI_WQE_SIZE
 786 };
 787
 788 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
 789         .type           = MLXSW_PCI_QUEUE_TYPE_CQ,
 790         .pre_init       = mlxsw_pci_cq_pre_init,
 791         .init           = mlxsw_pci_cq_init,
 792         .fini           = mlxsw_pci_cq_fini,
 793         .tasklet        = mlxsw_pci_cq_tasklet,
 794         .elem_count_f   = mlxsw_pci_cq_elem_count,
 795         .elem_size_f    = mlxsw_pci_cq_elem_size
 796 };
 797
 798 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
 799         .type           = MLXSW_PCI_QUEUE_TYPE_EQ,
 800         .init           = mlxsw_pci_eq_init,
 801         .fini           = mlxsw_pci_eq_fini,
 802         .tasklet        = mlxsw_pci_eq_tasklet,
 803         .elem_count     = MLXSW_PCI_EQE_COUNT,
 804         .elem_size      = MLXSW_PCI_EQE_SIZE
 805 };
 806
 807 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 808                                 const struct mlxsw_pci_queue_ops *q_ops,
 809                                 struct mlxsw_pci_queue *q, u8 q_num)
 810 {
 811         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 812         int i;
 813         int err;
 814
 815         q->num = q_num;
 816         if (q_ops->pre_init)
 817                 q_ops->pre_init(mlxsw_pci, q);
 818
 819         spin_lock_init(&q->lock);
 820         q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) :
 821                                          q_ops->elem_count;
 822         q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) :
 823                                             q_ops->elem_size;
 824         q->type = q_ops->type;
 825         q->pci = mlxsw_pci;
 826
 827         if (q_ops->tasklet)
 828                 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
 829
 830         mem_item->size = MLXSW_PCI_AQ_SIZE;
 831         mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
 832                                              mem_item->size,
 833                                              &mem_item->mapaddr);
 834         if (!mem_item->buf)
 835                 return -ENOMEM;
 836         memset(mem_item->buf, 0, mem_item->size);
 837
 838         q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
 839         if (!q->elem_info) {
 840                 err = -ENOMEM;
 841                 goto err_elem_info_alloc;
 842         }
 843
 844         /* Initialize dma mapped elements info elem_info for
 845          * future easy access.
 846          */
 847         for (i = 0; i < q->count; i++) {
 848                 struct mlxsw_pci_queue_elem_info *elem_info;
 849
 850                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 851                 elem_info->elem =
 852                         __mlxsw_pci_queue_elem_get(q, q->elem_size, i);
 853         }
 854
 855         mlxsw_cmd_mbox_zero(mbox);
 856         err = q_ops->init(mlxsw_pci, mbox, q);
 857         if (err)
 858                 goto err_q_ops_init;
 859         return 0;
 860
 861 err_q_ops_init:
 862         kfree(q->elem_info);
 863 err_elem_info_alloc:
 864         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 865                             mem_item->buf, mem_item->mapaddr);
 866         return err;
 867 }
 868
 869 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
 870                                  const struct mlxsw_pci_queue_ops *q_ops,
 871                                  struct mlxsw_pci_queue *q)
 872 {
 873         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 874
 875         q_ops->fini(mlxsw_pci, q);
 876         kfree(q->elem_info);
 877         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 878                             mem_item->buf, mem_item->mapaddr);
 879 }
 880
 881 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 882                                       const struct mlxsw_pci_queue_ops *q_ops,
 883                                       u8 num_qs)
 884 {
 885         struct mlxsw_pci_queue_type_group *queue_group;
 886         int i;
 887         int err;
 888
 889         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
 890         queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
 891         if (!queue_group->q)
 892                 return -ENOMEM;
 893
 894         for (i = 0; i < num_qs; i++) {
 895                 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
 896                                            &queue_group->q[i], i);
 897                 if (err)
 898                         goto err_queue_init;
 899         }
 900         queue_group->count = num_qs;
 901
 902         return 0;
 903
 904 err_queue_init:
 905         for (i--; i >= 0; i--)
 906                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
 907         kfree(queue_group->q);
 908         return err;
 909 }
 910
 911 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
 912                                        const struct mlxsw_pci_queue_ops *q_ops)
 913 {
 914         struct mlxsw_pci_queue_type_group *queue_group;
 915         int i;
 916
 917         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
 918         for (i = 0; i < queue_group->count; i++)
 919                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
 920         kfree(queue_group->q);
 921 }
 922
 923 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
 924 {
 925         struct pci_dev *pdev = mlxsw_pci->pdev;
 926         u8 num_sdqs;
 927         u8 sdq_log2sz;
 928         u8 num_rdqs;
 929         u8 rdq_log2sz;
 930         u8 num_cqs;
 931         u8 cq_log2sz;
 932         u8 cqv2_log2sz;
 933         u8 num_eqs;
 934         u8 eq_log2sz;
 935         int err;
 936
 937         mlxsw_cmd_mbox_zero(mbox);
 938         err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
 939         if (err)
 940                 return err;
 941
 942         num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
 943         sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
 944         num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
 945         rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
 946         num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
 947         cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
 948         cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
 949         num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
 950         eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
 951
 952         if (num_sdqs + num_rdqs > num_cqs ||
 953             num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
 954                 dev_err(&pdev->dev, "Unsupported number of queues\n");
 955                 return -EINVAL;
 956         }
 957
 958         if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
 959             (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
 960             (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) ||
 961             (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 &&
 962              (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) ||
 963             (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
 964                 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
 965                 return -EINVAL;
 966         }
 967
 968         mlxsw_pci->num_sdq_cqs = num_sdqs;
 969
 970         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
 971                                          num_eqs);
 972         if (err) {
 973                 dev_err(&pdev->dev, "Failed to initialize event queues\n");
 974                 return err;
 975         }
 976
 977         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
 978                                          num_cqs);
 979         if (err) {
 980                 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
 981                 goto err_cqs_init;
 982         }
 983
 984         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
 985                                          num_sdqs);
 986         if (err) {
 987                 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
 988                 goto err_sdqs_init;
 989         }
 990
 991         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
 992                                          num_rdqs);
 993         if (err) {
 994                 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
 995                 goto err_rdqs_init;
 996         }
 997
 998         /* We have to poll in command interface until queues are initialized */
 999         mlxsw_pci->cmd.nopoll = true;
1000         return 0;
1001
1002 err_rdqs_init:
1003         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1004 err_sdqs_init:
1005         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1006 err_cqs_init:
1007         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1008         return err;
1009 }
1010
1011 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1012 {
1013         mlxsw_pci->cmd.nopoll = false;
1014         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1015         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1016         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1017         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1018 }
1019
1020 static void
1021 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1022                                      char *mbox, int index,
1023                                      const struct mlxsw_swid_config *swid)
1024 {
1025         u8 mask = 0;
1026
1027         if (swid->used_type) {
1028                 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1029                         mbox, index, swid->type);
1030                 mask |= 1;
1031         }
1032         if (swid->used_properties) {
1033                 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1034                         mbox, index, swid->properties);
1035                 mask |= 2;
1036         }
1037         mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1038 }
1039
1040 static int mlxsw_pci_resources_query(struct mlxsw_pci *mlxsw_pci, char *mbox,
1041                                      struct mlxsw_res *res)
1042 {
1043         int index, i;
1044         u64 data;
1045         u16 id;
1046         int err;
1047
1048         if (!res)
1049                 return 0;
1050
1051         mlxsw_cmd_mbox_zero(mbox);
1052
1053         for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES;
1054              index++) {
1055                 err = mlxsw_cmd_query_resources(mlxsw_pci->core, mbox, index);
1056                 if (err)
1057                         return err;
1058
1059                 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) {
1060                         id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i);
1061                         data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i);
1062
1063                         if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID)
1064                                 return 0;
1065
1066                         mlxsw_res_parse(res, id, data);
1067                 }
1068         }
1069
1070         /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get
1071          * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW.
1072          */
1073         return -EIO;
1074 }
1075
1076 static int
1077 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
1078                                 const struct mlxsw_config_profile *profile,
1079                                 struct mlxsw_res *res)
1080 {
1081         u64 single_size, double_size, linear_size;
1082         int err;
1083
1084         err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
1085                                        &single_size, &double_size,
1086                                        &linear_size);
1087         if (err)
1088                 return err;
1089
1090         MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1091         MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1092         MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1093
1094         return 0;
1095 }
1096
1097 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1098                                     const struct mlxsw_config_profile *profile,
1099                                     struct mlxsw_res *res)
1100 {
1101         int i;
1102         int err;
1103
1104         mlxsw_cmd_mbox_zero(mbox);
1105
1106         if (profile->used_max_vepa_channels) {
1107                 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1108                         mbox, 1);
1109                 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1110                         mbox, profile->max_vepa_channels);
1111         }
1112         if (profile->used_max_mid) {
1113                 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1114                         mbox, 1);
1115                 mlxsw_cmd_mbox_config_profile_max_mid_set(
1116                         mbox, profile->max_mid);
1117         }
1118         if (profile->used_max_pgt) {
1119                 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1120                         mbox, 1);
1121                 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1122                         mbox, profile->max_pgt);
1123         }
1124         if (profile->used_max_system_port) {
1125                 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1126                         mbox, 1);
1127                 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1128                         mbox, profile->max_system_port);
1129         }
1130         if (profile->used_max_vlan_groups) {
1131                 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1132                         mbox, 1);
1133                 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1134                         mbox, profile->max_vlan_groups);
1135         }
1136         if (profile->used_max_regions) {
1137                 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1138                         mbox, 1);
1139                 mlxsw_cmd_mbox_config_profile_max_regions_set(
1140                         mbox, profile->max_regions);
1141         }
1142         if (profile->used_flood_tables) {
1143                 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1144                         mbox, 1);
1145                 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1146                         mbox, profile->max_flood_tables);
1147                 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1148                         mbox, profile->max_vid_flood_tables);
1149                 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1150                         mbox, profile->max_fid_offset_flood_tables);
1151                 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1152                         mbox, profile->fid_offset_flood_table_size);
1153                 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1154                         mbox, profile->max_fid_flood_tables);
1155                 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1156                         mbox, profile->fid_flood_table_size);
1157         }
1158         if (profile->used_flood_mode) {
1159                 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1160                         mbox, 1);
1161                 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1162                         mbox, profile->flood_mode);
1163         }
1164         if (profile->used_max_ib_mc) {
1165                 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1166                         mbox, 1);
1167                 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1168                         mbox, profile->max_ib_mc);
1169         }
1170         if (profile->used_max_pkey) {
1171                 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1172                         mbox, 1);
1173                 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1174                         mbox, profile->max_pkey);
1175         }
1176         if (profile->used_ar_sec) {
1177                 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1178                         mbox, 1);
1179                 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1180                         mbox, profile->ar_sec);
1181         }
1182         if (profile->used_adaptive_routing_group_cap) {
1183                 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1184                         mbox, 1);
1185                 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1186                         mbox, profile->adaptive_routing_group_cap);
1187         }
1188         if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) {
1189                 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);
1190                 if (err)
1191                         return err;
1192
1193                 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1194                 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1195                                         MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1196                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1197                                                                            1);
1198                 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1199                                         MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1200                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1201                                                                 mbox, 1);
1202                 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1203                                         MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1204         }
1205
1206         for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1207                 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1208                                                      &profile->swid_config[i]);
1209
1210         if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) {
1211                 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1212                 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1213         }
1214
1215         return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1216 }
1217
1218 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1219 {
1220         struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1221         int err;
1222
1223         mlxsw_cmd_mbox_zero(mbox);
1224         err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1225         if (err)
1226                 return err;
1227         mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1228         mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1229         return 0;
1230 }
1231
1232 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1233                                   u16 num_pages)
1234 {
1235         struct mlxsw_pci_mem_item *mem_item;
1236         int nent = 0;
1237         int i;
1238         int err;
1239
1240         mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1241                                            GFP_KERNEL);
1242         if (!mlxsw_pci->fw_area.items)
1243                 return -ENOMEM;
1244         mlxsw_pci->fw_area.count = num_pages;
1245
1246         mlxsw_cmd_mbox_zero(mbox);
1247         for (i = 0; i < num_pages; i++) {
1248                 mem_item = &mlxsw_pci->fw_area.items[i];
1249
1250                 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1251                 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1252                                                      mem_item->size,
1253                                                      &mem_item->mapaddr);
1254                 if (!mem_item->buf) {
1255                         err = -ENOMEM;
1256                         goto err_alloc;
1257                 }
1258                 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1259                 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1260                 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1261                         err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1262                         if (err)
1263                                 goto err_cmd_map_fa;
1264                         nent = 0;
1265                         mlxsw_cmd_mbox_zero(mbox);
1266                 }
1267         }
1268
1269         if (nent) {
1270                 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1271                 if (err)
1272                         goto err_cmd_map_fa;
1273         }
1274
1275         return 0;
1276
1277 err_cmd_map_fa:
1278 err_alloc:
1279         for (i--; i >= 0; i--) {
1280                 mem_item = &mlxsw_pci->fw_area.items[i];
1281
1282                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1283                                     mem_item->buf, mem_item->mapaddr);
1284         }
1285         kfree(mlxsw_pci->fw_area.items);
1286         return err;
1287 }
1288
1289 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1290 {
1291         struct mlxsw_pci_mem_item *mem_item;
1292         int i;
1293
1294         mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1295
1296         for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1297                 mem_item = &mlxsw_pci->fw_area.items[i];
1298
1299                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1300                                     mem_item->buf, mem_item->mapaddr);
1301         }
1302         kfree(mlxsw_pci->fw_area.items);
1303 }
1304
1305 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1306 {
1307         struct mlxsw_pci *mlxsw_pci = dev_id;
1308         struct mlxsw_pci_queue *q;
1309         int i;
1310
1311         for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1312                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1313                 mlxsw_pci_queue_tasklet_schedule(q);
1314         }
1315         return IRQ_HANDLED;
1316 }
1317
1318 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1319                                 struct mlxsw_pci_mem_item *mbox)
1320 {
1321         struct pci_dev *pdev = mlxsw_pci->pdev;
1322         int err = 0;
1323
1324         mbox->size = MLXSW_CMD_MBOX_SIZE;
1325         mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1326                                          &mbox->mapaddr);
1327         if (!mbox->buf) {
1328                 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1329                 err = -ENOMEM;
1330         }
1331
1332         return err;
1333 }
1334
1335 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1336                                 struct mlxsw_pci_mem_item *mbox)
1337 {
1338         struct pci_dev *pdev = mlxsw_pci->pdev;
1339
1340         pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1341                             mbox->mapaddr);
1342 }
1343
1344 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1345                               const struct pci_device_id *id)
1346 {
1347         unsigned long end;
1348         char mrsr_pl[MLXSW_REG_MRSR_LEN];
1349         int err;
1350
1351         mlxsw_reg_mrsr_pack(mrsr_pl);
1352         err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl);
1353         if (err)
1354                 return err;
1355         if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) {
1356                 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1357                 return 0;
1358         }
1359
1360         /* We must wait for the HW to become responsive once again. */
1361         msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS);
1362
1363         end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1364         do {
1365                 u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1366
1367                 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1368                         break;
1369                 cond_resched();
1370         } while (time_before(jiffies, end));
1371         return 0;
1372 }
1373
1374 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1375 {
1376         int err;
1377
1378         err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX);
1379         if (err < 0)
1380                 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n");
1381         return err;
1382 }
1383
1384 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1385 {
1386         pci_free_irq_vectors(mlxsw_pci->pdev);
1387 }
1388
1389 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1390                           const struct mlxsw_config_profile *profile,
1391                           struct mlxsw_res *res)
1392 {
1393         struct mlxsw_pci *mlxsw_pci = bus_priv;
1394         struct pci_dev *pdev = mlxsw_pci->pdev;
1395         char *mbox;
1396         u16 num_pages;
1397         int err;
1398
1399         mutex_init(&mlxsw_pci->cmd.lock);
1400         init_waitqueue_head(&mlxsw_pci->cmd.wait);
1401
1402         mlxsw_pci->core = mlxsw_core;
1403
1404         mbox = mlxsw_cmd_mbox_alloc();
1405         if (!mbox)
1406                 return -ENOMEM;
1407
1408         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1409         if (err)
1410                 goto mbox_put;
1411
1412         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1413         if (err)
1414                 goto err_out_mbox_alloc;
1415
1416         err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id);
1417         if (err)
1418                 goto err_sw_reset;
1419
1420         err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1421         if (err < 0) {
1422                 dev_err(&pdev->dev, "MSI-X init failed\n");
1423                 goto err_alloc_irq;
1424         }
1425
1426         err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1427         if (err)
1428                 goto err_query_fw;
1429
1430         mlxsw_pci->bus_info.fw_rev.major =
1431                 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1432         mlxsw_pci->bus_info.fw_rev.minor =
1433                 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1434         mlxsw_pci->bus_info.fw_rev.subminor =
1435                 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1436
1437         if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1438                 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1439                 err = -EINVAL;
1440                 goto err_iface_rev;
1441         }
1442         if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1443                 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1444                 err = -EINVAL;
1445                 goto err_doorbell_page_bar;
1446         }
1447
1448         mlxsw_pci->doorbell_offset =
1449                 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1450
1451         num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1452         err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1453         if (err)
1454                 goto err_fw_area_init;
1455
1456         err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1457         if (err)
1458                 goto err_boardinfo;
1459
1460         err = mlxsw_pci_resources_query(mlxsw_pci, mbox, res);
1461         if (err)
1462                 goto err_query_resources;
1463
1464         if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) &&
1465             MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2))
1466                 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2;
1467         else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) &&
1468                  MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1))
1469                 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1;
1470         else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) &&
1471                   MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) ||
1472                  !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) {
1473                 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0;
1474         } else {
1475                 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
1476                 goto err_cqe_v_check;
1477         }
1478
1479         err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1480         if (err)
1481                 goto err_config_profile;
1482
1483         err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1484         if (err)
1485                 goto err_aqs_init;
1486
1487         err = request_irq(pci_irq_vector(pdev, 0),
1488                           mlxsw_pci_eq_irq_handler, 0,
1489                           mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1490         if (err) {
1491                 dev_err(&pdev->dev, "IRQ request failed\n");
1492                 goto err_request_eq_irq;
1493         }
1494
1495         goto mbox_put;
1496
1497 err_request_eq_irq:
1498         mlxsw_pci_aqs_fini(mlxsw_pci);
1499 err_aqs_init:
1500 err_config_profile:
1501 err_cqe_v_check:
1502 err_query_resources:
1503 err_boardinfo:
1504         mlxsw_pci_fw_area_fini(mlxsw_pci);
1505 err_fw_area_init:
1506 err_doorbell_page_bar:
1507 err_iface_rev:
1508 err_query_fw:
1509         mlxsw_pci_free_irq_vectors(mlxsw_pci);
1510 err_alloc_irq:
1511 err_sw_reset:
1512         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1513 err_out_mbox_alloc:
1514         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1515 mbox_put:
1516         mlxsw_cmd_mbox_free(mbox);
1517         return err;
1518 }
1519
1520 static void mlxsw_pci_fini(void *bus_priv)
1521 {
1522         struct mlxsw_pci *mlxsw_pci = bus_priv;
1523
1524         free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
1525         mlxsw_pci_aqs_fini(mlxsw_pci);
1526         mlxsw_pci_fw_area_fini(mlxsw_pci);
1527         mlxsw_pci_free_irq_vectors(mlxsw_pci);
1528         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1529         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1530 }
1531
1532 static struct mlxsw_pci_queue *
1533 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1534                    const struct mlxsw_tx_info *tx_info)
1535 {
1536         u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1537
1538         return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1539 }
1540
1541 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1542                                         const struct mlxsw_tx_info *tx_info)
1543 {
1544         struct mlxsw_pci *mlxsw_pci = bus_priv;
1545         struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1546
1547         return !mlxsw_pci_queue_elem_info_producer_get(q);
1548 }
1549
1550 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1551                                   const struct mlxsw_tx_info *tx_info)
1552 {
1553         struct mlxsw_pci *mlxsw_pci = bus_priv;
1554         struct mlxsw_pci_queue *q;
1555         struct mlxsw_pci_queue_elem_info *elem_info;
1556         char *wqe;
1557         int i;
1558         int err;
1559
1560         if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1561                 err = skb_linearize(skb);
1562                 if (err)
1563                         return err;
1564         }
1565
1566         q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1567         spin_lock_bh(&q->lock);
1568         elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1569         if (!elem_info) {
1570                 /* queue is full */
1571                 err = -EAGAIN;
1572                 goto unlock;
1573         }
1574         elem_info->u.sdq.skb = skb;
1575
1576         wqe = elem_info->elem;
1577         mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1578         mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1579         mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1580
1581         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1582                                      skb_headlen(skb), DMA_TO_DEVICE);
1583         if (err)
1584                 goto unlock;
1585
1586         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1587                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1588
1589                 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1590                                              skb_frag_address(frag),
1591                                              skb_frag_size(frag),
1592                                              DMA_TO_DEVICE);
1593                 if (err)
1594                         goto unmap_frags;
1595         }
1596
1597         /* Set unused sq entries byte count to zero. */
1598         for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1599                 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1600
1601         /* Everything is set up, ring producer doorbell to get HW going */
1602         q->producer_counter++;
1603         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1604
1605         goto unlock;
1606
1607 unmap_frags:
1608         for (; i >= 0; i--)
1609                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1610 unlock:
1611         spin_unlock_bh(&q->lock);
1612         return err;
1613 }
1614
1615 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1616                               u32 in_mod, bool out_mbox_direct,
1617                               char *in_mbox, size_t in_mbox_size,
1618                               char *out_mbox, size_t out_mbox_size,
1619                               u8 *p_status)
1620 {
1621         struct mlxsw_pci *mlxsw_pci = bus_priv;
1622         dma_addr_t in_mapaddr = 0, out_mapaddr = 0;
1623         bool evreq = mlxsw_pci->cmd.nopoll;
1624         unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1625         bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1626         int err;
1627
1628         *p_status = MLXSW_CMD_STATUS_OK;
1629
1630         err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1631         if (err)
1632                 return err;
1633
1634         if (in_mbox) {
1635                 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1636                 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1637         }
1638         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1639         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1640
1641         if (out_mbox)
1642                 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1643         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1644         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1645
1646         mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1647         mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1648
1649         *p_wait_done = false;
1650
1651         wmb(); /* all needs to be written before we write control register */
1652         mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1653                           MLXSW_PCI_CIR_CTRL_GO_BIT |
1654                           (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1655                           (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1656                           opcode);
1657
1658         if (!evreq) {
1659                 unsigned long end;
1660
1661                 end = jiffies + timeout;
1662                 do {
1663                         u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1664
1665                         if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1666                                 *p_wait_done = true;
1667                                 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1668                                 break;
1669                         }
1670                         cond_resched();
1671                 } while (time_before(jiffies, end));
1672         } else {
1673                 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1674                 *p_status = mlxsw_pci->cmd.comp.status;
1675         }
1676
1677         err = 0;
1678         if (*p_wait_done) {
1679                 if (*p_status)
1680                         err = -EIO;
1681         } else {
1682                 err = -ETIMEDOUT;
1683         }
1684
1685         if (!err && out_mbox && out_mbox_direct) {
1686                 /* Some commands don't use output param as address to mailbox
1687                  * but they store output directly into registers. In that case,
1688                  * copy registers into mbox buffer.
1689                  */
1690                 __be32 tmp;
1691
1692                 if (!evreq) {
1693                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1694                                                            CIR_OUT_PARAM_HI));
1695                         memcpy(out_mbox, &tmp, sizeof(tmp));
1696                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1697                                                            CIR_OUT_PARAM_LO));
1698                         memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1699                 }
1700         } else if (!err && out_mbox) {
1701                 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1702         }
1703
1704         mutex_unlock(&mlxsw_pci->cmd.lock);
1705
1706         return err;
1707 }
1708
1709 static const struct mlxsw_bus mlxsw_pci_bus = {
1710         .kind                   = "pci",
1711         .init                   = mlxsw_pci_init,
1712         .fini                   = mlxsw_pci_fini,
1713         .skb_transmit_busy      = mlxsw_pci_skb_transmit_busy,
1714         .skb_transmit           = mlxsw_pci_skb_transmit,
1715         .cmd_exec               = mlxsw_pci_cmd_exec,
1716         .features               = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
1717 };
1718
1719 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1720 {
1721         const char *driver_name = pdev->driver->name;
1722         struct mlxsw_pci *mlxsw_pci;
1723         bool called_again = false;
1724         int err;
1725
1726         mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1727         if (!mlxsw_pci)
1728                 return -ENOMEM;
1729
1730         err = pci_enable_device(pdev);
1731         if (err) {
1732                 dev_err(&pdev->dev, "pci_enable_device failed\n");
1733                 goto err_pci_enable_device;
1734         }
1735
1736         err = pci_request_regions(pdev, driver_name);
1737         if (err) {
1738                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1739                 goto err_pci_request_regions;
1740         }
1741
1742         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1743         if (!err) {
1744                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1745                 if (err) {
1746                         dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1747                         goto err_pci_set_dma_mask;
1748                 }
1749         } else {
1750                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1751                 if (err) {
1752                         dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1753                         goto err_pci_set_dma_mask;
1754                 }
1755         }
1756
1757         if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1758                 dev_err(&pdev->dev, "invalid PCI region size\n");
1759                 err = -EINVAL;
1760                 goto err_pci_resource_len_check;
1761         }
1762
1763         mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1764                                      pci_resource_len(pdev, 0));
1765         if (!mlxsw_pci->hw_addr) {
1766                 dev_err(&pdev->dev, "ioremap failed\n");
1767                 err = -EIO;
1768                 goto err_ioremap;
1769         }
1770         pci_set_master(pdev);
1771
1772         mlxsw_pci->pdev = pdev;
1773         pci_set_drvdata(pdev, mlxsw_pci);
1774
1775         mlxsw_pci->bus_info.device_kind = driver_name;
1776         mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1777         mlxsw_pci->bus_info.dev = &pdev->dev;
1778         mlxsw_pci->id = id;
1779
1780 again:
1781         err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1782                                              &mlxsw_pci_bus, mlxsw_pci, false,
1783                                              NULL);
1784         /* -EAGAIN is returned in case the FW was updated. FW needs
1785          * a reset, so lets try to call mlxsw_core_bus_device_register()
1786          * again.
1787          */
1788         if (err == -EAGAIN && !called_again) {
1789                 called_again = true;
1790                 goto again;
1791         } else if (err) {
1792                 dev_err(&pdev->dev, "cannot register bus device\n");
1793                 goto err_bus_device_register;
1794         }
1795
1796         return 0;
1797
1798 err_bus_device_register:
1799         iounmap(mlxsw_pci->hw_addr);
1800 err_ioremap:
1801 err_pci_resource_len_check:
1802 err_pci_set_dma_mask:
1803         pci_release_regions(pdev);
1804 err_pci_request_regions:
1805         pci_disable_device(pdev);
1806 err_pci_enable_device:
1807         kfree(mlxsw_pci);
1808         return err;
1809 }
1810
1811 static void mlxsw_pci_remove(struct pci_dev *pdev)
1812 {
1813         struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1814
1815         mlxsw_core_bus_device_unregister(mlxsw_pci->core, false);
1816         iounmap(mlxsw_pci->hw_addr);
1817         pci_release_regions(mlxsw_pci->pdev);
1818         pci_disable_device(mlxsw_pci->pdev);
1819         kfree(mlxsw_pci);
1820 }
1821
1822 int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
1823 {
1824         pci_driver->probe = mlxsw_pci_probe;
1825         pci_driver->remove = mlxsw_pci_remove;
1826         return pci_register_driver(pci_driver);
1827 }
1828 EXPORT_SYMBOL(mlxsw_pci_driver_register);
1829
1830 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
1831 {
1832         pci_unregister_driver(pci_driver);
1833 }
1834 EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
1835
1836 static int __init mlxsw_pci_module_init(void)
1837 {
1838         return 0;
1839 }
1840
1841 static void __exit mlxsw_pci_module_exit(void)
1842 {
1843 }
1844
1845 module_init(mlxsw_pci_module_init);
1846 module_exit(mlxsw_pci_module_exit);
1847
1848 MODULE_LICENSE("Dual BSD/GPL");
1849 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1850 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");