1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
35 #include <linux/io.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
40 #include <linux/mutex.h>
41 #include <linux/pci.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/vmalloc.h>
45 #include <linux/etherdevice.h>
46 #include <linux/qed/qed_chain.h>
47 #include <linux/qed/qed_if.h>
48 #include "qed.h"
49 #include "qed_cxt.h"
50 #include "qed_dcbx.h"
51 #include "qed_dev_api.h"
52 #include "qed_fcoe.h"
53 #include "qed_hsi.h"
54 #include "qed_hw.h"
55 #include "qed_init_ops.h"
56 #include "qed_int.h"
57 #include "qed_iscsi.h"
58 #include "qed_ll2.h"
59 #include "qed_mcp.h"
60 #include "qed_ooo.h"
61 #include "qed_reg_addr.h"
62 #include "qed_sp.h"
63 #include "qed_sriov.h"
64 #include "qed_vf.h"
65 #include "qed_rdma.h"
67 static DEFINE_SPINLOCK(qm_lock);
69 #define QED_MIN_DPIS (4)
70 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
73 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
74 {
75 u32 bar_reg = (bar_id == BAR_ID_0 ?
76 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
77 u32 val;
79 if (IS_VF(p_hwfn->cdev))
80 return qed_vf_hw_bar_size(p_hwfn, bar_id);
82 val = qed_rd(p_hwfn, p_ptt, bar_reg);
83 if (val)
84 return 1 << (val + 15);
86 /* Old MFW initialized above registered only conditionally */
87 if (p_hwfn->cdev->num_hwfns > 1) {
88 DP_INFO(p_hwfn,
89 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
90 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
91 } else {
92 DP_INFO(p_hwfn,
93 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
94 return 512 * 1024;
95 }
96 }
98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
99 {
100 u32 i;
102 cdev->dp_level = dp_level;
103 cdev->dp_module = dp_module;
104 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
105 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
107 p_hwfn->dp_level = dp_level;
108 p_hwfn->dp_module = dp_module;
109 }
110 }
112 void qed_init_struct(struct qed_dev *cdev)
113 {
114 u8 i;
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
119 p_hwfn->cdev = cdev;
120 p_hwfn->my_id = i;
121 p_hwfn->b_active = false;
123 mutex_init(&p_hwfn->dmae_info.mutex);
124 }
126 /* hwfn 0 is always active */
127 cdev->hwfns[0].b_active = true;
129 /* set the default cache alignment to 128 */
130 cdev->cache_shift = 7;
131 }
133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
134 {
135 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
137 kfree(qm_info->qm_pq_params);
138 qm_info->qm_pq_params = NULL;
139 kfree(qm_info->qm_vport_params);
140 qm_info->qm_vport_params = NULL;
141 kfree(qm_info->qm_port_params);
142 qm_info->qm_port_params = NULL;
143 kfree(qm_info->wfq_data);
144 qm_info->wfq_data = NULL;
145 }
147 void qed_resc_free(struct qed_dev *cdev)
148 {
149 int i;
151 if (IS_VF(cdev)) {
152 for_each_hwfn(cdev, i)
153 qed_l2_free(&cdev->hwfns[i]);
154 return;
155 }
157 kfree(cdev->fw_data);
158 cdev->fw_data = NULL;
160 kfree(cdev->reset_stats);
161 cdev->reset_stats = NULL;
163 for_each_hwfn(cdev, i) {
164 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
166 qed_cxt_mngr_free(p_hwfn);
167 qed_qm_info_free(p_hwfn);
168 qed_spq_free(p_hwfn);
169 qed_eq_free(p_hwfn);
170 qed_consq_free(p_hwfn);
171 qed_int_free(p_hwfn);
172 #ifdef CONFIG_QED_LL2
173 qed_ll2_free(p_hwfn);
174 #endif
175 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
176 qed_fcoe_free(p_hwfn);
178 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
179 qed_iscsi_free(p_hwfn);
180 qed_ooo_free(p_hwfn);
181 }
182 qed_iov_free(p_hwfn);
183 qed_l2_free(p_hwfn);
184 qed_dmae_info_free(p_hwfn);
185 qed_dcbx_info_free(p_hwfn);
186 }
187 }
189 /******************** QM initialization *******************/
190 #define ACTIVE_TCS_BMAP 0x9f
191 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
193 /* determines the physical queue flags for a given PF. */
194 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
195 {
196 u32 flags;
198 /* common flags */
199 flags = PQ_FLAGS_LB;
201 /* feature flags */
202 if (IS_QED_SRIOV(p_hwfn->cdev))
203 flags |= PQ_FLAGS_VFS;
205 /* protocol flags */
206 switch (p_hwfn->hw_info.personality) {
207 case QED_PCI_ETH:
208 flags |= PQ_FLAGS_MCOS;
209 break;
210 case QED_PCI_FCOE:
211 flags |= PQ_FLAGS_OFLD;
212 break;
213 case QED_PCI_ISCSI:
214 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
215 break;
216 case QED_PCI_ETH_ROCE:
217 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
218 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
219 flags |= PQ_FLAGS_MTC;
220 break;
221 case QED_PCI_ETH_IWARP:
222 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
223 PQ_FLAGS_OFLD;
224 break;
225 default:
226 DP_ERR(p_hwfn,
227 "unknown personality %d\n", p_hwfn->hw_info.personality);
228 return 0;
229 }
231 return flags;
232 }
234 /* Getters for resource amounts necessary for qm initialization */
235 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
236 {
237 return p_hwfn->hw_info.num_hw_tc;
238 }
240 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
241 {
242 return IS_QED_SRIOV(p_hwfn->cdev) ?
243 p_hwfn->cdev->p_iov_info->total_vfs : 0;
244 }
246 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
247 {
248 u32 pq_flags = qed_get_pq_flags(p_hwfn);
250 if (!(PQ_FLAGS_MTC & pq_flags))
251 return 1;
253 return qed_init_qm_get_num_tcs(p_hwfn);
254 }
256 #define NUM_DEFAULT_RLS 1
258 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
259 {
260 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
262 /* num RLs can't exceed resource amount of rls or vports */
263 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
264 RESC_NUM(p_hwfn, QED_VPORT));
266 /* Make sure after we reserve there's something left */
267 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
268 return 0;
270 /* subtract rls necessary for VFs and one default one for the PF */
271 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
273 return num_pf_rls;
274 }
276 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
277 {
278 u32 pq_flags = qed_get_pq_flags(p_hwfn);
280 /* all pqs share the same vport, except for vfs and pf_rl pqs */
281 return (!!(PQ_FLAGS_RLS & pq_flags)) *
282 qed_init_qm_get_num_pf_rls(p_hwfn) +
283 (!!(PQ_FLAGS_VFS & pq_flags)) *
284 qed_init_qm_get_num_vfs(p_hwfn) + 1;
285 }
287 /* calc amount of PQs according to the requested flags */
288 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
289 {
290 u32 pq_flags = qed_get_pq_flags(p_hwfn);
292 return (!!(PQ_FLAGS_RLS & pq_flags)) *
293 qed_init_qm_get_num_pf_rls(p_hwfn) +
294 (!!(PQ_FLAGS_MCOS & pq_flags)) *
295 qed_init_qm_get_num_tcs(p_hwfn) +
296 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
297 (!!(PQ_FLAGS_ACK & pq_flags)) +
298 (!!(PQ_FLAGS_OFLD & pq_flags)) *
299 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
300 (!!(PQ_FLAGS_LLT & pq_flags)) *
301 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
302 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
303 }
305 /* initialize the top level QM params */
306 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
307 {
308 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
309 bool four_port;
311 /* pq and vport bases for this PF */
312 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
313 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
315 /* rate limiting and weighted fair queueing are always enabled */
316 qm_info->vport_rl_en = true;
317 qm_info->vport_wfq_en = true;
319 /* TC config is different for AH 4 port */
320 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
322 /* in AH 4 port we have fewer TCs per port */
323 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
324 NUM_OF_PHYS_TCS;
326 /* unless MFW indicated otherwise, ooo_tc == 3 for
327 * AH 4-port and 4 otherwise.
328 */
329 if (!qm_info->ooo_tc)
330 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
331 DCBX_TCP_OOO_TC;
332 }
334 /* initialize qm vport params */
335 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
336 {
337 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
338 u8 i;
340 /* all vports participate in weighted fair queueing */
341 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
342 qm_info->qm_vport_params[i].vport_wfq = 1;
343 }
345 /* initialize qm port params */
346 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
347 {
348 /* Initialize qm port parameters */
349 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
351 /* indicate how ooo and high pri traffic is dealt with */
352 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
353 ACTIVE_TCS_BMAP_4PORT_K2 :
354 ACTIVE_TCS_BMAP;
356 for (i = 0; i < num_ports; i++) {
357 struct init_qm_port_params *p_qm_port =
358 &p_hwfn->qm_info.qm_port_params[i];
360 p_qm_port->active = 1;
361 p_qm_port->active_phys_tcs = active_phys_tcs;
362 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
363 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
364 }
365 }
367 /* Reset the params which must be reset for qm init. QM init may be called as
368 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
369 * params may be affected by the init but would simply recalculate to the same
370 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
371 * affected as these amounts stay the same.
372 */
373 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
374 {
375 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
377 qm_info->num_pqs = 0;
378 qm_info->num_vports = 0;
379 qm_info->num_pf_rls = 0;
380 qm_info->num_vf_pqs = 0;
381 qm_info->first_vf_pq = 0;
382 qm_info->first_mcos_pq = 0;
383 qm_info->first_rl_pq = 0;
384 }
386 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
387 {
388 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
390 qm_info->num_vports++;
392 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
393 DP_ERR(p_hwfn,
394 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
395 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
396 }
398 /* initialize a single pq and manage qm_info resources accounting.
399 * The pq_init_flags param determines whether the PQ is rate limited
400 * (for VF or PF) and whether a new vport is allocated to the pq or not
401 * (i.e. vport will be shared).
402 */
404 /* flags for pq init */
405 #define PQ_INIT_SHARE_VPORT (1 << 0)
406 #define PQ_INIT_PF_RL (1 << 1)
407 #define PQ_INIT_VF_RL (1 << 2)
409 /* defines for pq init */
410 #define PQ_INIT_DEFAULT_WRR_GROUP 1
411 #define PQ_INIT_DEFAULT_TC 0
413 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
414 {
415 p_info->offload_tc = tc;
416 p_info->offload_tc_set = true;
417 }
419 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
420 {
421 return p_hwfn->hw_info.offload_tc_set;
422 }
424 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
425 {
426 if (qed_is_offload_tc_set(p_hwfn))
427 return p_hwfn->hw_info.offload_tc;
429 return PQ_INIT_DEFAULT_TC;
430 }
432 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
433 struct qed_qm_info *qm_info,
434 u8 tc, u32 pq_init_flags)
435 {
436 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
438 if (pq_idx > max_pq)
439 DP_ERR(p_hwfn,
440 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
442 /* init pq params */
443 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
444 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
445 qm_info->num_vports;
446 qm_info->qm_pq_params[pq_idx].tc_id = tc;
447 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
448 qm_info->qm_pq_params[pq_idx].rl_valid =
449 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
451 /* qm params accounting */
452 qm_info->num_pqs++;
453 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
454 qm_info->num_vports++;
456 if (pq_init_flags & PQ_INIT_PF_RL)
457 qm_info->num_pf_rls++;
459 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
460 DP_ERR(p_hwfn,
461 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
462 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
464 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
465 DP_ERR(p_hwfn,
466 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
467 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
468 }
470 /* get pq index according to PQ_FLAGS */
471 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
472 u32 pq_flags)
473 {
474 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
476 /* Can't have multiple flags set here */
477 if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
478 goto err;
480 switch (pq_flags) {
481 case PQ_FLAGS_RLS:
482 return &qm_info->first_rl_pq;
483 case PQ_FLAGS_MCOS:
484 return &qm_info->first_mcos_pq;
485 case PQ_FLAGS_LB:
486 return &qm_info->pure_lb_pq;
487 case PQ_FLAGS_OOO:
488 return &qm_info->ooo_pq;
489 case PQ_FLAGS_ACK:
490 return &qm_info->pure_ack_pq;
491 case PQ_FLAGS_OFLD:
492 return &qm_info->first_ofld_pq;
493 case PQ_FLAGS_LLT:
494 return &qm_info->first_llt_pq;
495 case PQ_FLAGS_VFS:
496 return &qm_info->first_vf_pq;
497 default:
498 goto err;
499 }
501 err:
502 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
503 return NULL;
504 }
506 /* save pq index in qm info */
507 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
508 u32 pq_flags, u16 pq_val)
509 {
510 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
512 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
513 }
515 /* get tx pq index, with the PQ TX base already set (ready for context init) */
516 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
517 {
518 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
520 return *base_pq_idx + CM_TX_PQ_BASE;
521 }
523 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
524 {
525 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
527 if (tc > max_tc)
528 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
530 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
531 }
533 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
534 {
535 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
537 if (vf > max_vf)
538 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
540 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
541 }
543 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
544 {
545 u16 first_ofld_pq, pq_offset;
547 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
548 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
549 tc : PQ_INIT_DEFAULT_TC;
551 return first_ofld_pq + pq_offset;
552 }
554 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
555 {
556 u16 first_llt_pq, pq_offset;
558 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
559 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
560 tc : PQ_INIT_DEFAULT_TC;
562 return first_llt_pq + pq_offset;
563 }
565 /* Functions for creating specific types of pqs */
566 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
567 {
568 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
570 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
571 return;
573 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
574 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
575 }
577 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
578 {
579 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
581 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
582 return;
584 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
585 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
586 }
588 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
589 {
590 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
592 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
593 return;
595 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
596 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
597 PQ_INIT_SHARE_VPORT);
598 }
600 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
601 {
602 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
603 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
604 u8 tc;
606 /* override pq's TC if offload TC is set */
607 for (tc = 0; tc < num_tcs; tc++)
608 qed_init_qm_pq(p_hwfn, qm_info,
609 qed_is_offload_tc_set(p_hwfn) ?
610 p_hwfn->hw_info.offload_tc : tc,
611 PQ_INIT_SHARE_VPORT);
612 }
614 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
615 {
616 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
618 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
619 return;
621 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
622 qed_init_qm_mtc_pqs(p_hwfn);
623 }
625 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
626 {
627 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
629 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
630 return;
632 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
633 qed_init_qm_mtc_pqs(p_hwfn);
634 }
636 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
637 {
638 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
639 u8 tc_idx;
641 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
642 return;
644 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
645 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
646 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
647 }
649 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
650 {
651 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
652 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
654 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
655 return;
657 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
658 qm_info->num_vf_pqs = num_vfs;
659 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
660 qed_init_qm_pq(p_hwfn,
661 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
662 }
664 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
665 {
666 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
667 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
669 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
670 return;
672 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
673 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
674 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
675 PQ_INIT_PF_RL);
676 }
678 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
679 {
680 /* rate limited pqs, must come first (FW assumption) */
681 qed_init_qm_rl_pqs(p_hwfn);
683 /* pqs for multi cos */
684 qed_init_qm_mcos_pqs(p_hwfn);
686 /* pure loopback pq */
687 qed_init_qm_lb_pq(p_hwfn);
689 /* out of order pq */
690 qed_init_qm_ooo_pq(p_hwfn);
692 /* pure ack pq */
693 qed_init_qm_pure_ack_pq(p_hwfn);
695 /* pq for offloaded protocol */
696 qed_init_qm_offload_pq(p_hwfn);
698 /* low latency pq */
699 qed_init_qm_low_latency_pq(p_hwfn);
701 /* done sharing vports */
702 qed_init_qm_advance_vport(p_hwfn);
704 /* pqs for vfs */
705 qed_init_qm_vf_pqs(p_hwfn);
706 }
708 /* compare values of getters against resources amounts */
709 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
710 {
711 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
712 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
713 return -EINVAL;
714 }
716 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
717 return 0;
719 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
720 p_hwfn->hw_info.multi_tc_roce_en = 0;
721 DP_NOTICE(p_hwfn,
722 "multi-tc roce was disabled to reduce requested amount of pqs\n");
723 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
724 return 0;
725 }
727 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
728 return -EINVAL;
729 }
731 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
732 {
733 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
734 struct init_qm_vport_params *vport;
735 struct init_qm_port_params *port;
736 struct init_qm_pq_params *pq;
737 int i, tc;
739 /* top level params */
740 DP_VERBOSE(p_hwfn,
741 NETIF_MSG_HW,
742 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
743 qm_info->start_pq,
744 qm_info->start_vport,
745 qm_info->pure_lb_pq,
746 qm_info->first_ofld_pq,
747 qm_info->first_llt_pq,
748 qm_info->pure_ack_pq);
749 DP_VERBOSE(p_hwfn,
750 NETIF_MSG_HW,
751 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
752 qm_info->ooo_pq,
753 qm_info->first_vf_pq,
754 qm_info->num_pqs,
755 qm_info->num_vf_pqs,
756 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
757 DP_VERBOSE(p_hwfn,
758 NETIF_MSG_HW,
759 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
760 qm_info->pf_rl_en,
761 qm_info->pf_wfq_en,
762 qm_info->vport_rl_en,
763 qm_info->vport_wfq_en,
764 qm_info->pf_wfq,
765 qm_info->pf_rl,
766 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
768 /* port table */
769 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
770 port = &(qm_info->qm_port_params[i]);
771 DP_VERBOSE(p_hwfn,
772 NETIF_MSG_HW,
773 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
774 i,
775 port->active,
776 port->active_phys_tcs,
777 port->num_pbf_cmd_lines,
778 port->num_btb_blocks, port->reserved);
779 }
781 /* vport table */
782 for (i = 0; i < qm_info->num_vports; i++) {
783 vport = &(qm_info->qm_vport_params[i]);
784 DP_VERBOSE(p_hwfn,
785 NETIF_MSG_HW,
786 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
787 qm_info->start_vport + i,
788 vport->vport_rl, vport->vport_wfq);
789 for (tc = 0; tc < NUM_OF_TCS; tc++)
790 DP_VERBOSE(p_hwfn,
791 NETIF_MSG_HW,
792 "%d ", vport->first_tx_pq_id[tc]);
793 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
794 }
796 /* pq table */
797 for (i = 0; i < qm_info->num_pqs; i++) {
798 pq = &(qm_info->qm_pq_params[i]);
799 DP_VERBOSE(p_hwfn,
800 NETIF_MSG_HW,
801 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
802 qm_info->start_pq + i,
803 pq->port_id,
804 pq->vport_id,
805 pq->tc_id, pq->wrr_group, pq->rl_valid);
806 }
807 }
809 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
810 {
811 /* reset params required for init run */
812 qed_init_qm_reset_params(p_hwfn);
814 /* init QM top level params */
815 qed_init_qm_params(p_hwfn);
817 /* init QM port params */
818 qed_init_qm_port_params(p_hwfn);
820 /* init QM vport params */
821 qed_init_qm_vport_params(p_hwfn);
823 /* init QM physical queue params */
824 qed_init_qm_pq_params(p_hwfn);
826 /* display all that init */
827 qed_dp_init_qm_params(p_hwfn);
828 }
830 /* This function reconfigures the QM pf on the fly.
831 * For this purpose we:
832 * 1. reconfigure the QM database
833 * 2. set new values to runtime array
834 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
835 * 4. activate init tool in QM_PF stage
836 * 5. send an sdm_qm_cmd through rbc interface to release the QM
837 */
838 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
839 {
840 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
841 bool b_rc;
842 int rc;
844 /* initialize qed's qm data structure */
845 qed_init_qm_info(p_hwfn);
847 /* stop PF's qm queues */
848 spin_lock_bh(&qm_lock);
849 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
850 qm_info->start_pq, qm_info->num_pqs);
851 spin_unlock_bh(&qm_lock);
852 if (!b_rc)
853 return -EINVAL;
855 /* clear the QM_PF runtime phase leftovers from previous init */
856 qed_init_clear_rt_data(p_hwfn);
858 /* prepare QM portion of runtime array */
859 qed_qm_init_pf(p_hwfn, p_ptt, false);
861 /* activate init tool on runtime array */
862 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
863 p_hwfn->hw_info.hw_mode);
864 if (rc)
865 return rc;
867 /* start PF's qm queues */
868 spin_lock_bh(&qm_lock);
869 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
870 qm_info->start_pq, qm_info->num_pqs);
871 spin_unlock_bh(&qm_lock);
872 if (!b_rc)
873 return -EINVAL;
875 return 0;
876 }
878 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
879 {
880 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
881 int rc;
883 rc = qed_init_qm_sanity(p_hwfn);
884 if (rc)
885 goto alloc_err;
887 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
888 sizeof(*qm_info->qm_pq_params),
889 GFP_KERNEL);
890 if (!qm_info->qm_pq_params)
891 goto alloc_err;
893 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
894 sizeof(*qm_info->qm_vport_params),
895 GFP_KERNEL);
896 if (!qm_info->qm_vport_params)
897 goto alloc_err;
899 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
900 sizeof(*qm_info->qm_port_params),
901 GFP_KERNEL);
902 if (!qm_info->qm_port_params)
903 goto alloc_err;
905 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
906 sizeof(*qm_info->wfq_data),
907 GFP_KERNEL);
908 if (!qm_info->wfq_data)
909 goto alloc_err;
911 return 0;
913 alloc_err:
914 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
915 qed_qm_info_free(p_hwfn);
916 return -ENOMEM;
917 }
919 int qed_resc_alloc(struct qed_dev *cdev)
920 {
921 u32 rdma_tasks, excess_tasks;
922 u32 line_count;
923 int i, rc = 0;
925 if (IS_VF(cdev)) {
926 for_each_hwfn(cdev, i) {
927 rc = qed_l2_alloc(&cdev->hwfns[i]);
928 if (rc)
929 return rc;
930 }
931 return rc;
932 }
934 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
935 if (!cdev->fw_data)
936 return -ENOMEM;
938 for_each_hwfn(cdev, i) {
939 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
940 u32 n_eqes, num_cons;
942 /* First allocate the context manager structure */
943 rc = qed_cxt_mngr_alloc(p_hwfn);
944 if (rc)
945 goto alloc_err;
947 /* Set the HW cid/tid numbers (in the contest manager)
948 * Must be done prior to any further computations.
949 */
950 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
951 if (rc)
952 goto alloc_err;
954 rc = qed_alloc_qm_data(p_hwfn);
955 if (rc)
956 goto alloc_err;
958 /* init qm info */
959 qed_init_qm_info(p_hwfn);
961 /* Compute the ILT client partition */
962 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
963 if (rc) {
964 DP_NOTICE(p_hwfn,
965 "too many ILT lines; re-computing with less lines\n");
966 /* In case there are not enough ILT lines we reduce the
967 * number of RDMA tasks and re-compute.
968 */
969 excess_tasks =
970 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
971 if (!excess_tasks)
972 goto alloc_err;
974 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
975 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
976 if (rc)
977 goto alloc_err;
979 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
980 if (rc) {
981 DP_ERR(p_hwfn,
982 "failed ILT compute. Requested too many lines: %u\n",
983 line_count);
985 goto alloc_err;
986 }
987 }
989 /* CID map / ILT shadow table / T2
990 * The talbes sizes are determined by the computations above
991 */
992 rc = qed_cxt_tables_alloc(p_hwfn);
993 if (rc)
994 goto alloc_err;
996 /* SPQ, must follow ILT because initializes SPQ context */
997 rc = qed_spq_alloc(p_hwfn);
998 if (rc)
999 goto alloc_err;
1001 /* SP status block allocation */
1002 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
1003 RESERVED_PTT_DPC);
1005 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1006 if (rc)
1007 goto alloc_err;
1009 rc = qed_iov_alloc(p_hwfn);
1010 if (rc)
1011 goto alloc_err;
1013 /* EQ */
1014 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
1015 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1016 enum protocol_type rdma_proto;
1018 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
1019 rdma_proto = PROTOCOLID_ROCE;
1020 else
1021 rdma_proto = PROTOCOLID_IWARP;
1023 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
1024 rdma_proto,
1025 NULL) * 2;
1026 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1027 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1028 num_cons =
1029 qed_cxt_get_proto_cid_count(p_hwfn,
1030 PROTOCOLID_ISCSI,
1031 NULL);
1032 n_eqes += 2 * num_cons;
1033 }
1035 if (n_eqes > 0xFFFF) {
1036 DP_ERR(p_hwfn,
1037 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
1038 n_eqes, 0xFFFF);
1039 goto alloc_no_mem;
1040 }
1042 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
1043 if (rc)
1044 goto alloc_err;
1046 rc = qed_consq_alloc(p_hwfn);
1047 if (rc)
1048 goto alloc_err;
1050 rc = qed_l2_alloc(p_hwfn);
1051 if (rc)
1052 goto alloc_err;
1054 #ifdef CONFIG_QED_LL2
1055 if (p_hwfn->using_ll2) {
1056 rc = qed_ll2_alloc(p_hwfn);
1057 if (rc)
1058 goto alloc_err;
1059 }
1060 #endif
1062 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1063 rc = qed_fcoe_alloc(p_hwfn);
1064 if (rc)
1065 goto alloc_err;
1066 }
1068 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1069 rc = qed_iscsi_alloc(p_hwfn);
1070 if (rc)
1071 goto alloc_err;
1072 rc = qed_ooo_alloc(p_hwfn);
1073 if (rc)
1074 goto alloc_err;
1075 }
1077 /* DMA info initialization */
1078 rc = qed_dmae_info_alloc(p_hwfn);
1079 if (rc)
1080 goto alloc_err;
1082 /* DCBX initialization */
1083 rc = qed_dcbx_info_alloc(p_hwfn);
1084 if (rc)
1085 goto alloc_err;
1086 }
1088 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1089 if (!cdev->reset_stats)
1090 goto alloc_no_mem;
1092 return 0;
1094 alloc_no_mem:
1095 rc = -ENOMEM;
1096 alloc_err:
1097 qed_resc_free(cdev);
1098 return rc;
1099 }
1101 void qed_resc_setup(struct qed_dev *cdev)
1102 {
1103 int i;
1105 if (IS_VF(cdev)) {
1106 for_each_hwfn(cdev, i)
1107 qed_l2_setup(&cdev->hwfns[i]);
1108 return;
1109 }
1111 for_each_hwfn(cdev, i) {
1112 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1114 qed_cxt_mngr_setup(p_hwfn);
1115 qed_spq_setup(p_hwfn);
1116 qed_eq_setup(p_hwfn);
1117 qed_consq_setup(p_hwfn);
1119 /* Read shadow of current MFW mailbox */
1120 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1121 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1122 p_hwfn->mcp_info->mfw_mb_cur,
1123 p_hwfn->mcp_info->mfw_mb_length);
1125 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1127 qed_l2_setup(p_hwfn);
1128 qed_iov_setup(p_hwfn);
1129 #ifdef CONFIG_QED_LL2
1130 if (p_hwfn->using_ll2)
1131 qed_ll2_setup(p_hwfn);
1132 #endif
1133 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1134 qed_fcoe_setup(p_hwfn);
1136 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1137 qed_iscsi_setup(p_hwfn);
1138 qed_ooo_setup(p_hwfn);
1139 }
1140 }
1141 }
1143 #define FINAL_CLEANUP_POLL_CNT (100)
1144 #define FINAL_CLEANUP_POLL_TIME (10)
1145 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1146 struct qed_ptt *p_ptt, u16 id, bool is_vf)
1147 {
1148 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1149 int rc = -EBUSY;
1151 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1152 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1154 if (is_vf)
1155 id += 0x10;
1157 command |= X_FINAL_CLEANUP_AGG_INT <<
1158 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1159 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1160 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1161 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1163 /* Make sure notification is not set before initiating final cleanup */
1164 if (REG_RD(p_hwfn, addr)) {
1165 DP_NOTICE(p_hwfn,
1166 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1167 REG_WR(p_hwfn, addr, 0);
1168 }
1170 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1171 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1172 id, command);
1174 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1176 /* Poll until completion */
1177 while (!REG_RD(p_hwfn, addr) && count--)
1178 msleep(FINAL_CLEANUP_POLL_TIME);
1180 if (REG_RD(p_hwfn, addr))
1181 rc = 0;
1182 else
1183 DP_NOTICE(p_hwfn,
1184 "Failed to receive FW final cleanup notification\n");
1186 /* Cleanup afterwards */
1187 REG_WR(p_hwfn, addr, 0);
1189 return rc;
1190 }
1192 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1193 {
1194 int hw_mode = 0;
1196 if (QED_IS_BB_B0(p_hwfn->cdev)) {
1197 hw_mode |= 1 << MODE_BB;
1198 } else if (QED_IS_AH(p_hwfn->cdev)) {
1199 hw_mode |= 1 << MODE_K2;
1200 } else {
1201 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1202 p_hwfn->cdev->type);
1203 return -EINVAL;
1204 }
1206 switch (p_hwfn->cdev->num_ports_in_engine) {
1207 case 1:
1208 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1209 break;
1210 case 2:
1211 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1212 break;
1213 case 4:
1214 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1215 break;
1216 default:
1217 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1218 p_hwfn->cdev->num_ports_in_engine);
1219 return -EINVAL;
1220 }
1222 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1223 hw_mode |= 1 << MODE_MF_SD;
1224 else
1225 hw_mode |= 1 << MODE_MF_SI;
1227 hw_mode |= 1 << MODE_ASIC;
1229 if (p_hwfn->cdev->num_hwfns > 1)
1230 hw_mode |= 1 << MODE_100G;
1232 p_hwfn->hw_info.hw_mode = hw_mode;
1234 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1235 "Configuring function for hw_mode: 0x%08x\n",
1236 p_hwfn->hw_info.hw_mode);
1238 return 0;
1239 }
1241 /* Init run time data for all PFs on an engine. */
1242 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1243 {
1244 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1245 int i, igu_sb_id;
1247 for_each_hwfn(cdev, i) {
1248 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1249 struct qed_igu_info *p_igu_info;
1250 struct qed_igu_block *p_block;
1251 struct cau_sb_entry sb_entry;
1253 p_igu_info = p_hwfn->hw_info.p_igu_info;
1255 for (igu_sb_id = 0;
1256 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1257 p_block = &p_igu_info->entry[igu_sb_id];
1259 if (!p_block->is_pf)
1260 continue;
1262 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1263 p_block->function_id, 0, 0);
1264 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1265 sb_entry);
1266 }
1267 }
1268 }
1270 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1271 struct qed_ptt *p_ptt)
1272 {
1273 u32 val, wr_mbs, cache_line_size;
1275 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1276 switch (val) {
1277 case 0:
1278 wr_mbs = 128;
1279 break;
1280 case 1:
1281 wr_mbs = 256;
1282 break;
1283 case 2:
1284 wr_mbs = 512;
1285 break;
1286 default:
1287 DP_INFO(p_hwfn,
1288 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1289 val);
1290 return;
1291 }
1293 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1294 switch (cache_line_size) {
1295 case 32:
1296 val = 0;
1297 break;
1298 case 64:
1299 val = 1;
1300 break;
1301 case 128:
1302 val = 2;
1303 break;
1304 case 256:
1305 val = 3;
1306 break;
1307 default:
1308 DP_INFO(p_hwfn,
1309 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1310 cache_line_size);
1311 }
1313 if (L1_CACHE_BYTES > wr_mbs)
1314 DP_INFO(p_hwfn,
1315 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1316 L1_CACHE_BYTES, wr_mbs);
1318 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1319 if (val > 0) {
1320 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1321 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1322 }
1323 }
1325 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1326 struct qed_ptt *p_ptt, int hw_mode)
1327 {
1328 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1329 struct qed_qm_common_rt_init_params params;
1330 struct qed_dev *cdev = p_hwfn->cdev;
1331 u8 vf_id, max_num_vfs;
1332 u16 num_pfs, pf_id;
1333 u32 concrete_fid;
1334 int rc = 0;
1336 qed_init_cau_rt_data(cdev);
1338 /* Program GTT windows */
1339 qed_gtt_init(p_hwfn);
1341 if (p_hwfn->mcp_info) {
1342 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1343 qm_info->pf_rl_en = true;
1344 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1345 qm_info->pf_wfq_en = true;
1346 }
1348 memset(¶ms, 0, sizeof(params));
1349 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1350 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1351 params.pf_rl_en = qm_info->pf_rl_en;
1352 params.pf_wfq_en = qm_info->pf_wfq_en;
1353 params.vport_rl_en = qm_info->vport_rl_en;
1354 params.vport_wfq_en = qm_info->vport_wfq_en;
1355 params.port_params = qm_info->qm_port_params;
1357 qed_qm_common_rt_init(p_hwfn, ¶ms);
1359 qed_cxt_hw_init_common(p_hwfn);
1361 qed_init_cache_line_size(p_hwfn, p_ptt);
1363 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1364 if (rc)
1365 return rc;
1367 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1368 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1370 if (QED_IS_BB(p_hwfn->cdev)) {
1371 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1372 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1373 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1374 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1375 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1376 }
1377 /* pretend to original PF */
1378 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1379 }
1381 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1382 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1383 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1384 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1385 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1386 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1387 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1388 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1389 }
1390 /* pretend to original PF */
1391 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1393 return rc;
1394 }
1396 static int
1397 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1398 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1399 {
1400 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1401 u32 min_dpis;
1402 u32 n_wids;
1404 /* Calculate DPI size */
1405 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1406 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1407 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1408 dpi_bit_shift = ilog2(dpi_page_size / 4096);
1409 dpi_count = pwm_region_size / dpi_page_size;
1411 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1412 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1414 p_hwfn->dpi_size = dpi_page_size;
1415 p_hwfn->dpi_count = dpi_count;
1417 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1419 if (dpi_count < min_dpis)
1420 return -EINVAL;
1422 return 0;
1423 }
1425 enum QED_ROCE_EDPM_MODE {
1426 QED_ROCE_EDPM_MODE_ENABLE = 0,
1427 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1428 QED_ROCE_EDPM_MODE_DISABLE = 2,
1429 };
1431 static int
1432 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1433 {
1434 u32 pwm_regsize, norm_regsize;
1435 u32 non_pwm_conn, min_addr_reg1;
1436 u32 db_bar_size, n_cpus = 1;
1437 u32 roce_edpm_mode;
1438 u32 pf_dems_shift;
1439 int rc = 0;
1440 u8 cond;
1442 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1443 if (p_hwfn->cdev->num_hwfns > 1)
1444 db_bar_size /= 2;
1446 /* Calculate doorbell regions */
1447 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1448 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1449 NULL) +
1450 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1451 NULL);
1452 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1453 min_addr_reg1 = norm_regsize / 4096;
1454 pwm_regsize = db_bar_size - norm_regsize;
1456 /* Check that the normal and PWM sizes are valid */
1457 if (db_bar_size < norm_regsize) {
1458 DP_ERR(p_hwfn->cdev,
1459 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1460 db_bar_size, norm_regsize);
1461 return -EINVAL;
1462 }
1464 if (pwm_regsize < QED_MIN_PWM_REGION) {
1465 DP_ERR(p_hwfn->cdev,
1466 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1467 pwm_regsize,
1468 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1469 return -EINVAL;
1470 }
1472 /* Calculate number of DPIs */
1473 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1474 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1475 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1476 /* Either EDPM is mandatory, or we are attempting to allocate a
1477 * WID per CPU.
1478 */
1479 n_cpus = num_present_cpus();
1480 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1481 }
1483 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1484 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1485 if (cond || p_hwfn->dcbx_no_edpm) {
1486 /* Either EDPM is disabled from user configuration, or it is
1487 * disabled via DCBx, or it is not mandatory and we failed to
1488 * allocated a WID per CPU.
1489 */
1490 n_cpus = 1;
1491 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1493 if (cond)
1494 qed_rdma_dpm_bar(p_hwfn, p_ptt);
1495 }
1497 p_hwfn->wid_count = (u16) n_cpus;
1499 DP_INFO(p_hwfn,
1500 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1501 norm_regsize,
1502 pwm_regsize,
1503 p_hwfn->dpi_size,
1504 p_hwfn->dpi_count,
1505 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1506 "disabled" : "enabled");
1508 if (rc) {
1509 DP_ERR(p_hwfn,
1510 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1511 p_hwfn->dpi_count,
1512 p_hwfn->pf_params.rdma_pf_params.min_dpis);
1513 return -EINVAL;
1514 }
1516 p_hwfn->dpi_start_offset = norm_regsize;
1518 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1519 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1520 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1521 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1523 return 0;
1524 }
1526 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1527 struct qed_ptt *p_ptt, int hw_mode)
1528 {
1529 int rc = 0;
1531 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1532 if (rc)
1533 return rc;
1535 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1537 return 0;
1538 }
1540 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1541 struct qed_ptt *p_ptt,
1542 struct qed_tunnel_info *p_tunn,
1543 int hw_mode,
1544 bool b_hw_start,
1545 enum qed_int_mode int_mode,
1546 bool allow_npar_tx_switch)
1547 {
1548 u8 rel_pf_id = p_hwfn->rel_pf_id;
1549 int rc = 0;
1551 if (p_hwfn->mcp_info) {
1552 struct qed_mcp_function_info *p_info;
1554 p_info = &p_hwfn->mcp_info->func_info;
1555 if (p_info->bandwidth_min)
1556 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1558 /* Update rate limit once we'll actually have a link */
1559 p_hwfn->qm_info.pf_rl = 100000;
1560 }
1562 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1564 qed_int_igu_init_rt(p_hwfn);
1566 /* Set VLAN in NIG if needed */
1567 if (hw_mode & BIT(MODE_MF_SD)) {
1568 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1569 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1570 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1571 p_hwfn->hw_info.ovlan);
1573 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1574 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1575 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1576 1);
1577 }
1579 /* Enable classification by MAC if needed */
1580 if (hw_mode & BIT(MODE_MF_SI)) {
1581 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1582 "Configuring TAGMAC_CLS_TYPE\n");
1583 STORE_RT_REG(p_hwfn,
1584 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1585 }
1587 /* Protocol Configuration */
1588 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1589 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1590 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1591 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1592 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1594 /* Cleanup chip from previous driver if such remains exist */
1595 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1596 if (rc)
1597 return rc;
1599 /* Sanity check before the PF init sequence that uses DMAE */
1600 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1601 if (rc)
1602 return rc;
1604 /* PF Init sequence */
1605 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1606 if (rc)
1607 return rc;
1609 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1610 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1611 if (rc)
1612 return rc;
1614 /* Pure runtime initializations - directly to the HW */
1615 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1617 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1618 if (rc)
1619 return rc;
1621 if (b_hw_start) {
1622 /* enable interrupts */
1623 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1625 /* send function start command */
1626 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1627 allow_npar_tx_switch);
1628 if (rc) {
1629 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1630 return rc;
1631 }
1632 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1633 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1634 qed_wr(p_hwfn, p_ptt,
1635 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1636 0x100);
1637 }
1638 }
1639 return rc;
1640 }
1642 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1643 struct qed_ptt *p_ptt,
1644 u8 enable)
1645 {
1646 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1648 /* Change PF in PXP */
1649 qed_wr(p_hwfn, p_ptt,
1650 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1652 /* wait until value is set - try for 1 second every 50us */
1653 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1654 val = qed_rd(p_hwfn, p_ptt,
1655 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1656 if (val == set_val)
1657 break;
1659 usleep_range(50, 60);
1660 }
1662 if (val != set_val) {
1663 DP_NOTICE(p_hwfn,
1664 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1665 return -EAGAIN;
1666 }
1668 return 0;
1669 }
1671 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1672 struct qed_ptt *p_main_ptt)
1673 {
1674 /* Read shadow of current MFW mailbox */
1675 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1676 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1677 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1678 }
1680 static void
1681 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1682 struct qed_drv_load_params *p_drv_load)
1683 {
1684 memset(p_load_req, 0, sizeof(*p_load_req));
1686 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1687 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1688 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1689 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1690 p_load_req->override_force_load = p_drv_load->override_force_load;
1691 }
1693 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1694 struct qed_hw_init_params *p_params)
1695 {
1696 if (p_params->p_tunn) {
1697 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1698 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1699 }
1701 p_hwfn->b_int_enabled = true;
1703 return 0;
1704 }
1706 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1707 {
1708 struct qed_load_req_params load_req_params;
1709 u32 load_code, resp, param, drv_mb_param;
1710 bool b_default_mtu = true;
1711 struct qed_hwfn *p_hwfn;
1712 int rc = 0, mfw_rc, i;
1713 u16 ether_type;
1715 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1716 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1717 return -EINVAL;
1718 }
1720 if (IS_PF(cdev)) {
1721 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1722 if (rc)
1723 return rc;
1724 }
1726 for_each_hwfn(cdev, i) {
1727 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1729 /* If management didn't provide a default, set one of our own */
1730 if (!p_hwfn->hw_info.mtu) {
1731 p_hwfn->hw_info.mtu = 1500;
1732 b_default_mtu = false;
1733 }
1735 if (IS_VF(cdev)) {
1736 qed_vf_start(p_hwfn, p_params);
1737 continue;
1738 }
1740 /* Enable DMAE in PXP */
1741 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1743 rc = qed_calc_hw_mode(p_hwfn);
1744 if (rc)
1745 return rc;
1747 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
1748 &cdev->mf_bits) ||
1749 test_bit(QED_MF_8021AD_TAGGING,
1750 &cdev->mf_bits))) {
1751 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
1752 ether_type = ETH_P_8021Q;
1753 else
1754 ether_type = ETH_P_8021AD;
1755 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1756 ether_type);
1757 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1758 ether_type);
1759 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1760 ether_type);
1761 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
1762 ether_type);
1763 }
1765 qed_fill_load_req_params(&load_req_params,
1766 p_params->p_drv_load_params);
1767 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1768 &load_req_params);
1769 if (rc) {
1770 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1771 return rc;
1772 }
1774 load_code = load_req_params.load_code;
1775 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1776 "Load request was sent. Load code: 0x%x\n",
1777 load_code);
1779 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1781 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1783 p_hwfn->first_on_engine = (load_code ==
1784 FW_MSG_CODE_DRV_LOAD_ENGINE);
1786 switch (load_code) {
1787 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1788 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1789 p_hwfn->hw_info.hw_mode);
1790 if (rc)
1791 break;
1792 /* Fall through */
1793 case FW_MSG_CODE_DRV_LOAD_PORT:
1794 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1795 p_hwfn->hw_info.hw_mode);
1796 if (rc)
1797 break;
1799 /* Fall through */
1800 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1801 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1802 p_params->p_tunn,
1803 p_hwfn->hw_info.hw_mode,
1804 p_params->b_hw_start,
1805 p_params->int_mode,
1806 p_params->allow_npar_tx_switch);
1807 break;
1808 default:
1809 DP_NOTICE(p_hwfn,
1810 "Unexpected load code [0x%08x]", load_code);
1811 rc = -EINVAL;
1812 break;
1813 }
1815 if (rc)
1816 DP_NOTICE(p_hwfn,
1817 "init phase failed for loadcode 0x%x (rc %d)\n",
1818 load_code, rc);
1820 /* ACK mfw regardless of success or failure of initialization */
1821 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1822 DRV_MSG_CODE_LOAD_DONE,
1823 0, &load_code, ¶m);
1824 if (rc)
1825 return rc;
1826 if (mfw_rc) {
1827 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1828 return mfw_rc;
1829 }
1831 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1832 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1833 DP_NOTICE(p_hwfn,
1834 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1836 /* send DCBX attention request command */
1837 DP_VERBOSE(p_hwfn,
1838 QED_MSG_DCB,
1839 "sending phony dcbx set command to trigger DCBx attention handling\n");
1840 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1841 DRV_MSG_CODE_SET_DCBX,
1842 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1843 &load_code, ¶m);
1844 if (mfw_rc) {
1845 DP_NOTICE(p_hwfn,
1846 "Failed to send DCBX attention request\n");
1847 return mfw_rc;
1848 }
1850 p_hwfn->hw_init_done = true;
1851 }
1853 if (IS_PF(cdev)) {
1854 p_hwfn = QED_LEADING_HWFN(cdev);
1856 /* Get pre-negotiated values for stag, bandwidth etc. */
1857 DP_VERBOSE(p_hwfn,
1858 QED_MSG_SPQ,
1859 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
1860 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
1861 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1862 DRV_MSG_CODE_GET_OEM_UPDATES,
1863 drv_mb_param, &resp, ¶m);
1864 if (rc)
1865 DP_NOTICE(p_hwfn,
1866 "Failed to send GET_OEM_UPDATES attention request\n");
1868 drv_mb_param = STORM_FW_VERSION;
1869 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1870 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1871 drv_mb_param, &load_code, ¶m);
1872 if (rc)
1873 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1875 if (!b_default_mtu) {
1876 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1877 p_hwfn->hw_info.mtu);
1878 if (rc)
1879 DP_INFO(p_hwfn,
1880 "Failed to update default mtu\n");
1881 }
1883 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1884 p_hwfn->p_main_ptt,
1885 QED_OV_DRIVER_STATE_DISABLED);
1886 if (rc)
1887 DP_INFO(p_hwfn, "Failed to update driver state\n");
1889 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1890 QED_OV_ESWITCH_NONE);
1891 if (rc)
1892 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1893 }
1895 return 0;
1896 }
1898 #define QED_HW_STOP_RETRY_LIMIT (10)
1899 static void qed_hw_timers_stop(struct qed_dev *cdev,
1900 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1901 {
1902 int i;
1904 /* close timers */
1905 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1906 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1908 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1909 if ((!qed_rd(p_hwfn, p_ptt,
1910 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1911 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1912 break;
1914 /* Dependent on number of connection/tasks, possibly
1915 * 1ms sleep is required between polls
1916 */
1917 usleep_range(1000, 2000);
1918 }
1920 if (i < QED_HW_STOP_RETRY_LIMIT)
1921 return;
1923 DP_NOTICE(p_hwfn,
1924 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1925 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1926 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1927 }
1929 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1930 {
1931 int j;
1933 for_each_hwfn(cdev, j) {
1934 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1935 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1937 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1938 }
1939 }
1941 int qed_hw_stop(struct qed_dev *cdev)
1942 {
1943 struct qed_hwfn *p_hwfn;
1944 struct qed_ptt *p_ptt;
1945 int rc, rc2 = 0;
1946 int j;
1948 for_each_hwfn(cdev, j) {
1949 p_hwfn = &cdev->hwfns[j];
1950 p_ptt = p_hwfn->p_main_ptt;
1952 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1954 if (IS_VF(cdev)) {
1955 qed_vf_pf_int_cleanup(p_hwfn);
1956 rc = qed_vf_pf_reset(p_hwfn);
1957 if (rc) {
1958 DP_NOTICE(p_hwfn,
1959 "qed_vf_pf_reset failed. rc = %d.\n",
1960 rc);
1961 rc2 = -EINVAL;
1962 }
1963 continue;
1964 }
1966 /* mark the hw as uninitialized... */
1967 p_hwfn->hw_init_done = false;
1969 /* Send unload command to MCP */
1970 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1971 if (rc) {
1972 DP_NOTICE(p_hwfn,
1973 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1974 rc);
1975 rc2 = -EINVAL;
1976 }
1978 qed_slowpath_irq_sync(p_hwfn);
1980 /* After this point no MFW attentions are expected, e.g. prevent
1981 * race between pf stop and dcbx pf update.
1982 */
1983 rc = qed_sp_pf_stop(p_hwfn);
1984 if (rc) {
1985 DP_NOTICE(p_hwfn,
1986 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1987 rc);
1988 rc2 = -EINVAL;
1989 }
1991 qed_wr(p_hwfn, p_ptt,
1992 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1994 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1995 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1996 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1997 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1998 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2000 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2002 /* Disable Attention Generation */
2003 qed_int_igu_disable_int(p_hwfn, p_ptt);
2005 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2006 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2008 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2010 /* Need to wait 1ms to guarantee SBs are cleared */
2011 usleep_range(1000, 2000);
2013 /* Disable PF in HW blocks */
2014 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2015 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2017 qed_mcp_unload_done(p_hwfn, p_ptt);
2018 if (rc) {
2019 DP_NOTICE(p_hwfn,
2020 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2021 rc);
2022 rc2 = -EINVAL;
2023 }
2024 }
2026 if (IS_PF(cdev)) {
2027 p_hwfn = QED_LEADING_HWFN(cdev);
2028 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
2030 /* Disable DMAE in PXP - in CMT, this should only be done for
2031 * first hw-function, and only after all transactions have
2032 * stopped for all active hw-functions.
2033 */
2034 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
2035 if (rc) {
2036 DP_NOTICE(p_hwfn,
2037 "qed_change_pci_hwfn failed. rc = %d.\n", rc);
2038 rc2 = -EINVAL;
2039 }
2040 }
2042 return rc2;
2043 }
2045 int qed_hw_stop_fastpath(struct qed_dev *cdev)
2046 {
2047 int j;
2049 for_each_hwfn(cdev, j) {
2050 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2051 struct qed_ptt *p_ptt;
2053 if (IS_VF(cdev)) {
2054 qed_vf_pf_int_cleanup(p_hwfn);
2055 continue;
2056 }
2057 p_ptt = qed_ptt_acquire(p_hwfn);
2058 if (!p_ptt)
2059 return -EAGAIN;
2061 DP_VERBOSE(p_hwfn,
2062 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
2064 qed_wr(p_hwfn, p_ptt,
2065 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2067 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2068 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2069 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2070 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2071 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2073 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2075 /* Need to wait 1ms to guarantee SBs are cleared */
2076 usleep_range(1000, 2000);
2077 qed_ptt_release(p_hwfn, p_ptt);
2078 }
2080 return 0;
2081 }
2083 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2084 {
2085 struct qed_ptt *p_ptt;
2087 if (IS_VF(p_hwfn->cdev))
2088 return 0;
2090 p_ptt = qed_ptt_acquire(p_hwfn);
2091 if (!p_ptt)
2092 return -EAGAIN;
2094 /* If roce info is allocated it means roce is initialized and should
2095 * be enabled in searcher.
2096 */
2097 if (p_hwfn->p_rdma_info &&
2098 p_hwfn->b_rdma_enabled_in_prs)
2099 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2101 /* Re-open incoming traffic */
2102 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2103 qed_ptt_release(p_hwfn, p_ptt);
2105 return 0;
2106 }
2108 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2109 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2110 {
2111 qed_ptt_pool_free(p_hwfn);
2112 kfree(p_hwfn->hw_info.p_igu_info);
2113 p_hwfn->hw_info.p_igu_info = NULL;
2114 }
2116 /* Setup bar access */
2117 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2118 {
2119 /* clear indirect access */
2120 if (QED_IS_AH(p_hwfn->cdev)) {
2121 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2122 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2123 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2124 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2125 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2126 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2127 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2128 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2129 } else {
2130 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2131 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2132 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2133 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2134 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2135 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2136 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2137 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2138 }
2140 /* Clean Previous errors if such exist */
2141 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2142 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2144 /* enable internal target-read */
2145 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2146 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2147 }
2149 static void get_function_id(struct qed_hwfn *p_hwfn)
2150 {
2151 /* ME Register */
2152 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2153 PXP_PF_ME_OPAQUE_ADDR);
2155 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2157 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2158 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2159 PXP_CONCRETE_FID_PFID);
2160 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2161 PXP_CONCRETE_FID_PORT);
2163 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2164 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2165 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2166 }
2168 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2169 {
2170 u32 *feat_num = p_hwfn->hw_info.feat_num;
2171 struct qed_sb_cnt_info sb_cnt;
2172 u32 non_l2_sbs = 0;
2174 memset(&sb_cnt, 0, sizeof(sb_cnt));
2175 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2177 if (IS_ENABLED(CONFIG_QED_RDMA) &&
2178 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2179 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2180 * the status blocks equally between L2 / RoCE but with
2181 * consideration as to how many l2 queues / cnqs we have.
2182 */
2183 feat_num[QED_RDMA_CNQ] =
2184 min_t(u32, sb_cnt.cnt / 2,
2185 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2187 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2188 }
2189 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2190 /* Start by allocating VF queues, then PF's */
2191 feat_num[QED_VF_L2_QUE] = min_t(u32,
2192 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2193 sb_cnt.iov_cnt);
2194 feat_num[QED_PF_L2_QUE] = min_t(u32,
2195 sb_cnt.cnt - non_l2_sbs,
2196 RESC_NUM(p_hwfn,
2197 QED_L2_QUEUE) -
2198 FEAT_NUM(p_hwfn,
2199 QED_VF_L2_QUE));
2200 }
2202 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2203 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
2204 RESC_NUM(p_hwfn,
2205 QED_CMDQS_CQS));
2207 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2208 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2209 RESC_NUM(p_hwfn,
2210 QED_CMDQS_CQS));
2211 DP_VERBOSE(p_hwfn,
2212 NETIF_MSG_PROBE,
2213 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2214 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2215 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2216 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2217 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2218 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2219 (int)sb_cnt.cnt);
2220 }
2222 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2223 {
2224 switch (res_id) {
2225 case QED_L2_QUEUE:
2226 return "L2_QUEUE";
2227 case QED_VPORT:
2228 return "VPORT";
2229 case QED_RSS_ENG:
2230 return "RSS_ENG";
2231 case QED_PQ:
2232 return "PQ";
2233 case QED_RL:
2234 return "RL";
2235 case QED_MAC:
2236 return "MAC";
2237 case QED_VLAN:
2238 return "VLAN";
2239 case QED_RDMA_CNQ_RAM:
2240 return "RDMA_CNQ_RAM";
2241 case QED_ILT:
2242 return "ILT";
2243 case QED_LL2_QUEUE:
2244 return "LL2_QUEUE";
2245 case QED_CMDQS_CQS:
2246 return "CMDQS_CQS";
2247 case QED_RDMA_STATS_QUEUE:
2248 return "RDMA_STATS_QUEUE";
2249 case QED_BDQ:
2250 return "BDQ";
2251 case QED_SB:
2252 return "SB";
2253 default:
2254 return "UNKNOWN_RESOURCE";
2255 }
2256 }
2258 static int
2259 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2260 struct qed_ptt *p_ptt,
2261 enum qed_resources res_id,
2262 u32 resc_max_val, u32 *p_mcp_resp)
2263 {
2264 int rc;
2266 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2267 resc_max_val, p_mcp_resp);
2268 if (rc) {
2269 DP_NOTICE(p_hwfn,
2270 "MFW response failure for a max value setting of resource %d [%s]\n",
2271 res_id, qed_hw_get_resc_name(res_id));
2272 return rc;
2273 }
2275 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2276 DP_INFO(p_hwfn,
2277 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2278 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2280 return 0;
2281 }
2283 static int
2284 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2285 {
2286 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2287 u32 resc_max_val, mcp_resp;
2288 u8 res_id;
2289 int rc;
2291 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2292 switch (res_id) {
2293 case QED_LL2_QUEUE:
2294 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2295 break;
2296 case QED_RDMA_CNQ_RAM:
2297 /* No need for a case for QED_CMDQS_CQS since
2298 * CNQ/CMDQS are the same resource.
2299 */
2300 resc_max_val = NUM_OF_GLOBAL_QUEUES;
2301 break;
2302 case QED_RDMA_STATS_QUEUE:
2303 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2304 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2305 break;
2306 case QED_BDQ:
2307 resc_max_val = BDQ_NUM_RESOURCES;
2308 break;
2309 default:
2310 continue;
2311 }
2313 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2314 resc_max_val, &mcp_resp);
2315 if (rc)
2316 return rc;
2318 /* There's no point to continue to the next resource if the
2319 * command is not supported by the MFW.
2320 * We do continue if the command is supported but the resource
2321 * is unknown to the MFW. Such a resource will be later
2322 * configured with the default allocation values.
2323 */
2324 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2325 return -EINVAL;
2326 }
2328 return 0;
2329 }
2331 static
2332 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2333 enum qed_resources res_id,
2334 u32 *p_resc_num, u32 *p_resc_start)
2335 {
2336 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2337 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2339 switch (res_id) {
2340 case QED_L2_QUEUE:
2341 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2342 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2343 break;
2344 case QED_VPORT:
2345 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2346 MAX_NUM_VPORTS_BB) / num_funcs;
2347 break;
2348 case QED_RSS_ENG:
2349 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2350 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2351 break;
2352 case QED_PQ:
2353 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2354 MAX_QM_TX_QUEUES_BB) / num_funcs;
2355 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
2356 break;
2357 case QED_RL:
2358 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2359 break;
2360 case QED_MAC:
2361 case QED_VLAN:
2362 /* Each VFC resource can accommodate both a MAC and a VLAN */
2363 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2364 break;
2365 case QED_ILT:
2366 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2367 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2368 break;
2369 case QED_LL2_QUEUE:
2370 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2371 break;
2372 case QED_RDMA_CNQ_RAM:
2373 case QED_CMDQS_CQS:
2374 /* CNQ/CMDQS are the same resource */
2375 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2376 break;
2377 case QED_RDMA_STATS_QUEUE:
2378 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2379 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2380 break;
2381 case QED_BDQ:
2382 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2383 p_hwfn->hw_info.personality != QED_PCI_FCOE)
2384 *p_resc_num = 0;
2385 else
2386 *p_resc_num = 1;
2387 break;
2388 case QED_SB:
2389 /* Since we want its value to reflect whether MFW supports
2390 * the new scheme, have a default of 0.
2391 */
2392 *p_resc_num = 0;
2393 break;
2394 default:
2395 return -EINVAL;
2396 }
2398 switch (res_id) {
2399 case QED_BDQ:
2400 if (!*p_resc_num)
2401 *p_resc_start = 0;
2402 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2403 *p_resc_start = p_hwfn->port_id;
2404 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2405 *p_resc_start = p_hwfn->port_id;
2406 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2407 *p_resc_start = p_hwfn->port_id + 2;
2408 break;
2409 default:
2410 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2411 break;
2412 }
2414 return 0;
2415 }
2417 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2418 enum qed_resources res_id)
2419 {
2420 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2421 u32 mcp_resp, *p_resc_num, *p_resc_start;
2422 int rc;
2424 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2425 p_resc_start = &RESC_START(p_hwfn, res_id);
2427 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2428 &dflt_resc_start);
2429 if (rc) {
2430 DP_ERR(p_hwfn,
2431 "Failed to get default amount for resource %d [%s]\n",
2432 res_id, qed_hw_get_resc_name(res_id));
2433 return rc;
2434 }
2436 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2437 &mcp_resp, p_resc_num, p_resc_start);
2438 if (rc) {
2439 DP_NOTICE(p_hwfn,
2440 "MFW response failure for an allocation request for resource %d [%s]\n",
2441 res_id, qed_hw_get_resc_name(res_id));
2442 return rc;
2443 }
2445 /* Default driver values are applied in the following cases:
2446 * - The resource allocation MB command is not supported by the MFW
2447 * - There is an internal error in the MFW while processing the request
2448 * - The resource ID is unknown to the MFW
2449 */
2450 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2451 DP_INFO(p_hwfn,
2452 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2453 res_id,
2454 qed_hw_get_resc_name(res_id),
2455 mcp_resp, dflt_resc_num, dflt_resc_start);
2456 *p_resc_num = dflt_resc_num;
2457 *p_resc_start = dflt_resc_start;
2458 goto out;
2459 }
2461 out:
2462 /* PQs have to divide by 8 [that's the HW granularity].
2463 * Reduce number so it would fit.
2464 */
2465 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2466 DP_INFO(p_hwfn,
2467 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2468 *p_resc_num,
2469 (*p_resc_num) & ~0x7,
2470 *p_resc_start, (*p_resc_start) & ~0x7);
2471 *p_resc_num &= ~0x7;
2472 *p_resc_start &= ~0x7;
2473 }
2475 return 0;
2476 }
2478 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2479 {
2480 int rc;
2481 u8 res_id;
2483 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2484 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2485 if (rc)
2486 return rc;
2487 }
2489 return 0;
2490 }
2492 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2493 {
2494 struct qed_resc_unlock_params resc_unlock_params;
2495 struct qed_resc_lock_params resc_lock_params;
2496 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2497 u8 res_id;
2498 int rc;
2500 /* Setting the max values of the soft resources and the following
2501 * resources allocation queries should be atomic. Since several PFs can
2502 * run in parallel - a resource lock is needed.
2503 * If either the resource lock or resource set value commands are not
2504 * supported - skip the the max values setting, release the lock if
2505 * needed, and proceed to the queries. Other failures, including a
2506 * failure to acquire the lock, will cause this function to fail.
2507 */
2508 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2509 QED_RESC_LOCK_RESC_ALLOC, false);
2511 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2512 if (rc && rc != -EINVAL) {
2513 return rc;
2514 } else if (rc == -EINVAL) {
2515 DP_INFO(p_hwfn,
2516 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2517 } else if (!rc && !resc_lock_params.b_granted) {
2518 DP_NOTICE(p_hwfn,
2519 "Failed to acquire the resource lock for the resource allocation commands\n");
2520 return -EBUSY;
2521 } else {
2522 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2523 if (rc && rc != -EINVAL) {
2524 DP_NOTICE(p_hwfn,
2525 "Failed to set the max values of the soft resources\n");
2526 goto unlock_and_exit;
2527 } else if (rc == -EINVAL) {
2528 DP_INFO(p_hwfn,
2529 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2530 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2531 &resc_unlock_params);
2532 if (rc)
2533 DP_INFO(p_hwfn,
2534 "Failed to release the resource lock for the resource allocation commands\n");
2535 }
2536 }
2538 rc = qed_hw_set_resc_info(p_hwfn);
2539 if (rc)
2540 goto unlock_and_exit;
2542 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2543 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2544 if (rc)
2545 DP_INFO(p_hwfn,
2546 "Failed to release the resource lock for the resource allocation commands\n");
2547 }
2549 /* Sanity for ILT */
2550 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2551 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2552 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2553 RESC_START(p_hwfn, QED_ILT),
2554 RESC_END(p_hwfn, QED_ILT) - 1);
2555 return -EINVAL;
2556 }
2558 /* This will also learn the number of SBs from MFW */
2559 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2560 return -EINVAL;
2562 qed_hw_set_feat(p_hwfn);
2564 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2565 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2566 qed_hw_get_resc_name(res_id),
2567 RESC_NUM(p_hwfn, res_id),
2568 RESC_START(p_hwfn, res_id));
2570 return 0;
2572 unlock_and_exit:
2573 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2574 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2575 return rc;
2576 }
2578 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2579 {
2580 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2581 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2582 struct qed_mcp_link_capabilities *p_caps;
2583 struct qed_mcp_link_params *link;
2585 /* Read global nvm_cfg address */
2586 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2588 /* Verify MCP has initialized it */
2589 if (!nvm_cfg_addr) {
2590 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2591 return -EINVAL;
2592 }
2594 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2595 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2597 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2598 offsetof(struct nvm_cfg1, glob) +
2599 offsetof(struct nvm_cfg1_glob, core_cfg);
2601 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2603 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2604 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2605 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2606 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2607 break;
2608 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2609 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2610 break;
2611 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2612 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2613 break;
2614 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2615 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2616 break;
2617 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2618 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2619 break;
2620 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2621 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2622 break;
2623 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2624 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2625 break;
2626 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2627 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2628 break;
2629 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2630 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2631 break;
2632 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2633 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2634 break;
2635 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2636 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2637 break;
2638 default:
2639 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2640 break;
2641 }
2643 /* Read default link configuration */
2644 link = &p_hwfn->mcp_info->link_input;
2645 p_caps = &p_hwfn->mcp_info->link_capabilities;
2646 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2647 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2648 link_temp = qed_rd(p_hwfn, p_ptt,
2649 port_cfg_addr +
2650 offsetof(struct nvm_cfg1_port, speed_cap_mask));
2651 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2652 link->speed.advertised_speeds = link_temp;
2654 link_temp = link->speed.advertised_speeds;
2655 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2657 link_temp = qed_rd(p_hwfn, p_ptt,
2658 port_cfg_addr +
2659 offsetof(struct nvm_cfg1_port, link_settings));
2660 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2661 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2662 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2663 link->speed.autoneg = true;
2664 break;
2665 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2666 link->speed.forced_speed = 1000;
2667 break;
2668 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2669 link->speed.forced_speed = 10000;
2670 break;
2671 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2672 link->speed.forced_speed = 25000;
2673 break;
2674 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2675 link->speed.forced_speed = 40000;
2676 break;
2677 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2678 link->speed.forced_speed = 50000;
2679 break;
2680 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2681 link->speed.forced_speed = 100000;
2682 break;
2683 default:
2684 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2685 }
2687 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2688 link->speed.autoneg;
2690 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2691 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2692 link->pause.autoneg = !!(link_temp &
2693 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2694 link->pause.forced_rx = !!(link_temp &
2695 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2696 link->pause.forced_tx = !!(link_temp &
2697 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2698 link->loopback_mode = 0;
2700 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2701 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2702 offsetof(struct nvm_cfg1_port, ext_phy));
2703 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2704 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2705 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2706 link->eee.enable = true;
2707 switch (link_temp) {
2708 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2709 p_caps->default_eee = QED_MCP_EEE_DISABLED;
2710 link->eee.enable = false;
2711 break;
2712 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2713 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2714 break;
2715 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2716 p_caps->eee_lpi_timer =
2717 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2718 break;
2719 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2720 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2721 break;
2722 }
2724 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2725 link->eee.tx_lpi_enable = link->eee.enable;
2726 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2727 } else {
2728 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2729 }
2731 DP_VERBOSE(p_hwfn,
2732 NETIF_MSG_LINK,
2733 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2734 link->speed.forced_speed,
2735 link->speed.advertised_speeds,
2736 link->speed.autoneg,
2737 link->pause.autoneg,
2738 p_caps->default_eee, p_caps->eee_lpi_timer);
2740 if (IS_LEAD_HWFN(p_hwfn)) {
2741 struct qed_dev *cdev = p_hwfn->cdev;
2743 /* Read Multi-function information from shmem */
2744 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2745 offsetof(struct nvm_cfg1, glob) +
2746 offsetof(struct nvm_cfg1_glob, generic_cont0);
2748 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2750 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2751 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2753 switch (mf_mode) {
2754 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2755 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
2756 break;
2757 case NVM_CFG1_GLOB_MF_MODE_UFP:
2758 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2759 BIT(QED_MF_LLH_PROTO_CLSS) |
2760 BIT(QED_MF_UFP_SPECIFIC) |
2761 BIT(QED_MF_8021Q_TAGGING);
2762 break;
2763 case NVM_CFG1_GLOB_MF_MODE_BD:
2764 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2765 BIT(QED_MF_LLH_PROTO_CLSS) |
2766 BIT(QED_MF_8021AD_TAGGING);
2767 break;
2768 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2769 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2770 BIT(QED_MF_LLH_PROTO_CLSS) |
2771 BIT(QED_MF_LL2_NON_UNICAST) |
2772 BIT(QED_MF_INTER_PF_SWITCH);
2773 break;
2774 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2775 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2776 BIT(QED_MF_LLH_PROTO_CLSS) |
2777 BIT(QED_MF_LL2_NON_UNICAST);
2778 if (QED_IS_BB(p_hwfn->cdev))
2779 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
2780 break;
2781 }
2783 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2784 cdev->mf_bits);
2785 }
2787 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2788 p_hwfn->cdev->mf_bits);
2790 /* Read device capabilities information from shmem */
2791 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2792 offsetof(struct nvm_cfg1, glob) +
2793 offsetof(struct nvm_cfg1_glob, device_capabilities);
2795 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2796 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2797 __set_bit(QED_DEV_CAP_ETH,
2798 &p_hwfn->hw_info.device_capabilities);
2799 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2800 __set_bit(QED_DEV_CAP_FCOE,
2801 &p_hwfn->hw_info.device_capabilities);
2802 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2803 __set_bit(QED_DEV_CAP_ISCSI,
2804 &p_hwfn->hw_info.device_capabilities);
2805 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2806 __set_bit(QED_DEV_CAP_ROCE,
2807 &p_hwfn->hw_info.device_capabilities);
2809 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2810 }
2812 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2813 {
2814 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2815 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2816 struct qed_dev *cdev = p_hwfn->cdev;
2818 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2820 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2821 * in the other bits are selected.
2822 * Bits 1-15 are for functions 1-15, respectively, and their value is
2823 * '0' only for enabled functions (function 0 always exists and
2824 * enabled).
2825 * In case of CMT, only the "even" functions are enabled, and thus the
2826 * number of functions for both hwfns is learnt from the same bits.
2827 */
2828 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2830 if (reg_function_hide & 0x1) {
2831 if (QED_IS_BB(cdev)) {
2832 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2833 num_funcs = 0;
2834 eng_mask = 0xaaaa;
2835 } else {
2836 num_funcs = 1;
2837 eng_mask = 0x5554;
2838 }
2839 } else {
2840 num_funcs = 1;
2841 eng_mask = 0xfffe;
2842 }
2844 /* Get the number of the enabled functions on the engine */
2845 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2846 while (tmp) {
2847 if (tmp & 0x1)
2848 num_funcs++;
2849 tmp >>= 0x1;
2850 }
2852 /* Get the PF index within the enabled functions */
2853 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2854 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2855 while (tmp) {
2856 if (tmp & 0x1)
2857 enabled_func_idx--;
2858 tmp >>= 0x1;
2859 }
2860 }
2862 p_hwfn->num_funcs_on_engine = num_funcs;
2863 p_hwfn->enabled_func_idx = enabled_func_idx;
2865 DP_VERBOSE(p_hwfn,
2866 NETIF_MSG_PROBE,
2867 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2868 p_hwfn->rel_pf_id,
2869 p_hwfn->abs_pf_id,
2870 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2871 }
2873 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2874 struct qed_ptt *p_ptt)
2875 {
2876 u32 port_mode;
2878 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2880 if (port_mode < 3) {
2881 p_hwfn->cdev->num_ports_in_engine = 1;
2882 } else if (port_mode <= 5) {
2883 p_hwfn->cdev->num_ports_in_engine = 2;
2884 } else {
2885 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2886 p_hwfn->cdev->num_ports_in_engine);
2888 /* Default num_ports_in_engine to something */
2889 p_hwfn->cdev->num_ports_in_engine = 1;
2890 }
2891 }
2893 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2894 struct qed_ptt *p_ptt)
2895 {
2896 u32 port;
2897 int i;
2899 p_hwfn->cdev->num_ports_in_engine = 0;
2901 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2902 port = qed_rd(p_hwfn, p_ptt,
2903 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2904 if (port & 1)
2905 p_hwfn->cdev->num_ports_in_engine++;
2906 }
2908 if (!p_hwfn->cdev->num_ports_in_engine) {
2909 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2911 /* Default num_ports_in_engine to something */
2912 p_hwfn->cdev->num_ports_in_engine = 1;
2913 }
2914 }
2916 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2917 {
2918 if (QED_IS_BB(p_hwfn->cdev))
2919 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2920 else
2921 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2922 }
2924 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2925 {
2926 struct qed_mcp_link_capabilities *p_caps;
2927 u32 eee_status;
2929 p_caps = &p_hwfn->mcp_info->link_capabilities;
2930 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2931 return;
2933 p_caps->eee_speed_caps = 0;
2934 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2935 offsetof(struct public_port, eee_status));
2936 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2937 EEE_SUPPORTED_SPEED_OFFSET;
2939 if (eee_status & EEE_1G_SUPPORTED)
2940 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2941 if (eee_status & EEE_10G_ADV)
2942 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2943 }
2945 static int
2946 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2947 struct qed_ptt *p_ptt,
2948 enum qed_pci_personality personality)
2949 {
2950 int rc;
2952 /* Since all information is common, only first hwfns should do this */
2953 if (IS_LEAD_HWFN(p_hwfn)) {
2954 rc = qed_iov_hw_info(p_hwfn);
2955 if (rc)
2956 return rc;
2957 }
2959 qed_hw_info_port_num(p_hwfn, p_ptt);
2961 qed_mcp_get_capabilities(p_hwfn, p_ptt);
2963 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2965 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2966 if (rc)
2967 return rc;
2969 if (qed_mcp_is_init(p_hwfn))
2970 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2971 p_hwfn->mcp_info->func_info.mac);
2972 else
2973 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2975 if (qed_mcp_is_init(p_hwfn)) {
2976 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2977 p_hwfn->hw_info.ovlan =
2978 p_hwfn->mcp_info->func_info.ovlan;
2980 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2982 qed_get_eee_caps(p_hwfn, p_ptt);
2984 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
2985 }
2987 if (qed_mcp_is_init(p_hwfn)) {
2988 enum qed_pci_personality protocol;
2990 protocol = p_hwfn->mcp_info->func_info.protocol;
2991 p_hwfn->hw_info.personality = protocol;
2992 }
2994 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2995 p_hwfn->hw_info.multi_tc_roce_en = 1;
2997 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2998 p_hwfn->hw_info.num_active_tc = 1;
3000 qed_get_num_funcs(p_hwfn, p_ptt);
3002 if (qed_mcp_is_init(p_hwfn))
3003 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3005 return qed_hw_get_resc(p_hwfn, p_ptt);
3006 }
3008 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3009 {
3010 struct qed_dev *cdev = p_hwfn->cdev;
3011 u16 device_id_mask;
3012 u32 tmp;
3014 /* Read Vendor Id / Device Id */
3015 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
3016 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
3018 /* Determine type */
3019 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
3020 switch (device_id_mask) {
3021 case QED_DEV_ID_MASK_BB:
3022 cdev->type = QED_DEV_TYPE_BB;
3023 break;
3024 case QED_DEV_ID_MASK_AH:
3025 cdev->type = QED_DEV_TYPE_AH;
3026 break;
3027 default:
3028 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
3029 return -EBUSY;
3030 }
3032 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3033 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3035 MASK_FIELD(CHIP_REV, cdev->chip_rev);
3037 /* Learn number of HW-functions */
3038 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3040 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3041 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
3042 cdev->num_hwfns = 2;
3043 } else {
3044 cdev->num_hwfns = 1;
3045 }
3047 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
3048 MISCS_REG_CHIP_TEST_REG) >> 4;
3049 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
3050 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3051 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
3053 DP_INFO(cdev->hwfns,
3054 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3055 QED_IS_BB(cdev) ? "BB" : "AH",
3056 'A' + cdev->chip_rev,
3057 (int)cdev->chip_metal,
3058 cdev->chip_num, cdev->chip_rev,
3059 cdev->chip_bond_id, cdev->chip_metal);
3061 return 0;
3062 }
3064 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
3065 {
3066 kfree(p_hwfn->nvm_info.image_att);
3067 p_hwfn->nvm_info.image_att = NULL;
3068 }
3070 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
3071 void __iomem *p_regview,
3072 void __iomem *p_doorbells,
3073 enum qed_pci_personality personality)
3074 {
3075 int rc = 0;
3077 /* Split PCI bars evenly between hwfns */
3078 p_hwfn->regview = p_regview;
3079 p_hwfn->doorbells = p_doorbells;
3081 if (IS_VF(p_hwfn->cdev))
3082 return qed_vf_hw_prepare(p_hwfn);
3084 /* Validate that chip access is feasible */
3085 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3086 DP_ERR(p_hwfn,
3087 "Reading the ME register returns all Fs; Preventing further chip access\n");
3088 return -EINVAL;
3089 }
3091 get_function_id(p_hwfn);
3093 /* Allocate PTT pool */
3094 rc = qed_ptt_pool_alloc(p_hwfn);
3095 if (rc)
3096 goto err0;
3098 /* Allocate the main PTT */
3099 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3101 /* First hwfn learns basic information, e.g., number of hwfns */
3102 if (!p_hwfn->my_id) {
3103 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3104 if (rc)
3105 goto err1;
3106 }
3108 qed_hw_hwfn_prepare(p_hwfn);
3110 /* Initialize MCP structure */
3111 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3112 if (rc) {
3113 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3114 goto err1;
3115 }
3117 /* Read the device configuration information from the HW and SHMEM */
3118 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3119 if (rc) {
3120 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3121 goto err2;
3122 }
3124 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3125 * is called as it sets the ports number in an engine.
3126 */
3127 if (IS_LEAD_HWFN(p_hwfn)) {
3128 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3129 if (rc)
3130 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3131 }
3133 /* NVRAM info initialization and population */
3134 if (IS_LEAD_HWFN(p_hwfn)) {
3135 rc = qed_mcp_nvm_info_populate(p_hwfn);
3136 if (rc) {
3137 DP_NOTICE(p_hwfn,
3138 "Failed to populate nvm info shadow\n");
3139 goto err2;
3140 }
3141 }
3143 /* Allocate the init RT array and initialize the init-ops engine */
3144 rc = qed_init_alloc(p_hwfn);
3145 if (rc)
3146 goto err3;
3148 return rc;
3149 err3:
3150 if (IS_LEAD_HWFN(p_hwfn))
3151 qed_nvm_info_free(p_hwfn);
3152 err2:
3153 if (IS_LEAD_HWFN(p_hwfn))
3154 qed_iov_free_hw_info(p_hwfn->cdev);
3155 qed_mcp_free(p_hwfn);
3156 err1:
3157 qed_hw_hwfn_free(p_hwfn);
3158 err0:
3159 return rc;
3160 }
3162 int qed_hw_prepare(struct qed_dev *cdev,
3163 int personality)
3164 {
3165 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3166 int rc;
3168 /* Store the precompiled init data ptrs */
3169 if (IS_PF(cdev))
3170 qed_init_iro_array(cdev);
3172 /* Initialize the first hwfn - will learn number of hwfns */
3173 rc = qed_hw_prepare_single(p_hwfn,
3174 cdev->regview,
3175 cdev->doorbells, personality);
3176 if (rc)
3177 return rc;
3179 personality = p_hwfn->hw_info.personality;
3181 /* Initialize the rest of the hwfns */
3182 if (cdev->num_hwfns > 1) {
3183 void __iomem *p_regview, *p_doorbell;
3184 u8 __iomem *addr;
3186 /* adjust bar offset for second engine */
3187 addr = cdev->regview +
3188 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3189 BAR_ID_0) / 2;
3190 p_regview = addr;
3192 addr = cdev->doorbells +
3193 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3194 BAR_ID_1) / 2;
3195 p_doorbell = addr;
3197 /* prepare second hw function */
3198 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3199 p_doorbell, personality);
3201 /* in case of error, need to free the previously
3202 * initiliazed hwfn 0.
3203 */
3204 if (rc) {
3205 if (IS_PF(cdev)) {
3206 qed_init_free(p_hwfn);
3207 qed_nvm_info_free(p_hwfn);
3208 qed_mcp_free(p_hwfn);
3209 qed_hw_hwfn_free(p_hwfn);
3210 }
3211 }
3212 }
3214 return rc;
3215 }
3217 void qed_hw_remove(struct qed_dev *cdev)
3218 {
3219 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3220 int i;
3222 if (IS_PF(cdev))
3223 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3224 QED_OV_DRIVER_STATE_NOT_LOADED);
3226 for_each_hwfn(cdev, i) {
3227 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3229 if (IS_VF(cdev)) {
3230 qed_vf_pf_release(p_hwfn);
3231 continue;
3232 }
3234 qed_init_free(p_hwfn);
3235 qed_hw_hwfn_free(p_hwfn);
3236 qed_mcp_free(p_hwfn);
3237 }
3239 qed_iov_free_hw_info(cdev);
3241 qed_nvm_info_free(p_hwfn);
3242 }
3244 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3245 struct qed_chain *p_chain)
3246 {
3247 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3248 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3249 struct qed_chain_next *p_next;
3250 u32 size, i;
3252 if (!p_virt)
3253 return;
3255 size = p_chain->elem_size * p_chain->usable_per_page;
3257 for (i = 0; i < p_chain->page_cnt; i++) {
3258 if (!p_virt)
3259 break;
3261 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3262 p_virt_next = p_next->next_virt;
3263 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3265 dma_free_coherent(&cdev->pdev->dev,
3266 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3268 p_virt = p_virt_next;
3269 p_phys = p_phys_next;
3270 }
3271 }
3273 static void qed_chain_free_single(struct qed_dev *cdev,
3274 struct qed_chain *p_chain)
3275 {
3276 if (!p_chain->p_virt_addr)
3277 return;
3279 dma_free_coherent(&cdev->pdev->dev,
3280 QED_CHAIN_PAGE_SIZE,
3281 p_chain->p_virt_addr, p_chain->p_phys_addr);
3282 }
3284 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3285 {
3286 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3287 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3288 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3290 if (!pp_virt_addr_tbl)
3291 return;
3293 if (!p_pbl_virt)
3294 goto out;
3296 for (i = 0; i < page_cnt; i++) {
3297 if (!pp_virt_addr_tbl[i])
3298 break;
3300 dma_free_coherent(&cdev->pdev->dev,
3301 QED_CHAIN_PAGE_SIZE,
3302 pp_virt_addr_tbl[i],
3303 *(dma_addr_t *)p_pbl_virt);
3305 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3306 }
3308 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3310 if (!p_chain->b_external_pbl)
3311 dma_free_coherent(&cdev->pdev->dev,
3312 pbl_size,
3313 p_chain->pbl_sp.p_virt_table,
3314 p_chain->pbl_sp.p_phys_table);
3315 out:
3316 vfree(p_chain->pbl.pp_virt_addr_tbl);
3317 p_chain->pbl.pp_virt_addr_tbl = NULL;
3318 }
3320 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3321 {
3322 switch (p_chain->mode) {
3323 case QED_CHAIN_MODE_NEXT_PTR:
3324 qed_chain_free_next_ptr(cdev, p_chain);
3325 break;
3326 case QED_CHAIN_MODE_SINGLE:
3327 qed_chain_free_single(cdev, p_chain);
3328 break;
3329 case QED_CHAIN_MODE_PBL:
3330 qed_chain_free_pbl(cdev, p_chain);
3331 break;
3332 }
3333 }
3335 static int
3336 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3337 enum qed_chain_cnt_type cnt_type,
3338 size_t elem_size, u32 page_cnt)
3339 {
3340 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3342 /* The actual chain size can be larger than the maximal possible value
3343 * after rounding up the requested elements number to pages, and after
3344 * taking into acount the unusuable elements (next-ptr elements).
3345 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3346 * size/capacity fields are of a u32 type.
3347 */
3348 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3349 chain_size > ((u32)U16_MAX + 1)) ||
3350 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3351 DP_NOTICE(cdev,
3352 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3353 chain_size);
3354 return -EINVAL;
3355 }
3357 return 0;
3358 }
3360 static int
3361 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3362 {
3363 void *p_virt = NULL, *p_virt_prev = NULL;
3364 dma_addr_t p_phys = 0;
3365 u32 i;
3367 for (i = 0; i < p_chain->page_cnt; i++) {
3368 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3369 QED_CHAIN_PAGE_SIZE,
3370 &p_phys, GFP_KERNEL);
3371 if (!p_virt)
3372 return -ENOMEM;
3374 if (i == 0) {
3375 qed_chain_init_mem(p_chain, p_virt, p_phys);
3376 qed_chain_reset(p_chain);
3377 } else {
3378 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3379 p_virt, p_phys);
3380 }
3382 p_virt_prev = p_virt;
3383 }
3384 /* Last page's next element should point to the beginning of the
3385 * chain.
3386 */
3387 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3388 p_chain->p_virt_addr,
3389 p_chain->p_phys_addr);
3391 return 0;
3392 }
3394 static int
3395 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3396 {
3397 dma_addr_t p_phys = 0;
3398 void *p_virt = NULL;
3400 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3401 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3402 if (!p_virt)
3403 return -ENOMEM;
3405 qed_chain_init_mem(p_chain, p_virt, p_phys);
3406 qed_chain_reset(p_chain);
3408 return 0;
3409 }
3411 static int
3412 qed_chain_alloc_pbl(struct qed_dev *cdev,
3413 struct qed_chain *p_chain,
3414 struct qed_chain_ext_pbl *ext_pbl)
3415 {
3416 u32 page_cnt = p_chain->page_cnt, size, i;
3417 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3418 void **pp_virt_addr_tbl = NULL;
3419 u8 *p_pbl_virt = NULL;
3420 void *p_virt = NULL;
3422 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3423 pp_virt_addr_tbl = vzalloc(size);
3424 if (!pp_virt_addr_tbl)
3425 return -ENOMEM;
3427 /* The allocation of the PBL table is done with its full size, since it
3428 * is expected to be successive.
3429 * qed_chain_init_pbl_mem() is called even in a case of an allocation
3430 * failure, since pp_virt_addr_tbl was previously allocated, and it
3431 * should be saved to allow its freeing during the error flow.
3432 */
3433 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3435 if (!ext_pbl) {
3436 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3437 size, &p_pbl_phys, GFP_KERNEL);
3438 } else {
3439 p_pbl_virt = ext_pbl->p_pbl_virt;
3440 p_pbl_phys = ext_pbl->p_pbl_phys;
3441 p_chain->b_external_pbl = true;
3442 }
3444 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3445 pp_virt_addr_tbl);
3446 if (!p_pbl_virt)
3447 return -ENOMEM;
3449 for (i = 0; i < page_cnt; i++) {
3450 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3451 QED_CHAIN_PAGE_SIZE,
3452 &p_phys, GFP_KERNEL);
3453 if (!p_virt)
3454 return -ENOMEM;
3456 if (i == 0) {
3457 qed_chain_init_mem(p_chain, p_virt, p_phys);
3458 qed_chain_reset(p_chain);
3459 }
3461 /* Fill the PBL table with the physical address of the page */
3462 *(dma_addr_t *)p_pbl_virt = p_phys;
3463 /* Keep the virtual address of the page */
3464 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3466 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3467 }
3469 return 0;
3470 }
3472 int qed_chain_alloc(struct qed_dev *cdev,
3473 enum qed_chain_use_mode intended_use,
3474 enum qed_chain_mode mode,
3475 enum qed_chain_cnt_type cnt_type,
3476 u32 num_elems,
3477 size_t elem_size,
3478 struct qed_chain *p_chain,
3479 struct qed_chain_ext_pbl *ext_pbl)
3480 {
3481 u32 page_cnt;
3482 int rc = 0;
3484 if (mode == QED_CHAIN_MODE_SINGLE)
3485 page_cnt = 1;
3486 else
3487 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3489 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3490 if (rc) {
3491 DP_NOTICE(cdev,
3492 "Cannot allocate a chain with the given arguments:\n");
3493 DP_NOTICE(cdev,
3494 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3495 intended_use, mode, cnt_type, num_elems, elem_size);
3496 return rc;
3497 }
3499 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3500 mode, cnt_type);
3502 switch (mode) {
3503 case QED_CHAIN_MODE_NEXT_PTR:
3504 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3505 break;
3506 case QED_CHAIN_MODE_SINGLE:
3507 rc = qed_chain_alloc_single(cdev, p_chain);
3508 break;
3509 case QED_CHAIN_MODE_PBL:
3510 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3511 break;
3512 }
3513 if (rc)
3514 goto nomem;
3516 return 0;
3518 nomem:
3519 qed_chain_free(cdev, p_chain);
3520 return rc;
3521 }
3523 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3524 {
3525 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3526 u16 min, max;
3528 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3529 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3530 DP_NOTICE(p_hwfn,
3531 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3532 src_id, min, max);
3534 return -EINVAL;
3535 }
3537 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3539 return 0;
3540 }
3542 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3543 {
3544 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3545 u8 min, max;
3547 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3548 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3549 DP_NOTICE(p_hwfn,
3550 "vport id [%d] is not valid, available indices [%d - %d]\n",
3551 src_id, min, max);
3553 return -EINVAL;
3554 }
3556 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3558 return 0;
3559 }
3561 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3562 {
3563 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3564 u8 min, max;
3566 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3567 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3568 DP_NOTICE(p_hwfn,
3569 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3570 src_id, min, max);
3572 return -EINVAL;
3573 }
3575 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3577 return 0;
3578 }
3580 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3581 u8 *p_filter)
3582 {
3583 *p_high = p_filter[1] | (p_filter[0] << 8);
3584 *p_low = p_filter[5] | (p_filter[4] << 8) |
3585 (p_filter[3] << 16) | (p_filter[2] << 24);
3586 }
3588 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3589 struct qed_ptt *p_ptt, u8 *p_filter)
3590 {
3591 u32 high = 0, low = 0, en;
3592 int i;
3594 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3595 return 0;
3597 qed_llh_mac_to_filter(&high, &low, p_filter);
3599 /* Find a free entry and utilize it */
3600 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3601 en = qed_rd(p_hwfn, p_ptt,
3602 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3603 if (en)
3604 continue;
3605 qed_wr(p_hwfn, p_ptt,
3606 NIG_REG_LLH_FUNC_FILTER_VALUE +
3607 2 * i * sizeof(u32), low);
3608 qed_wr(p_hwfn, p_ptt,
3609 NIG_REG_LLH_FUNC_FILTER_VALUE +
3610 (2 * i + 1) * sizeof(u32), high);
3611 qed_wr(p_hwfn, p_ptt,
3612 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3613 qed_wr(p_hwfn, p_ptt,
3614 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3615 i * sizeof(u32), 0);
3616 qed_wr(p_hwfn, p_ptt,
3617 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3618 break;
3619 }
3620 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3621 DP_NOTICE(p_hwfn,
3622 "Failed to find an empty LLH filter to utilize\n");
3623 return -EINVAL;
3624 }
3626 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3627 "mac: %pM is added at %d\n",
3628 p_filter, i);
3630 return 0;
3631 }
3633 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3634 struct qed_ptt *p_ptt, u8 *p_filter)
3635 {
3636 u32 high = 0, low = 0;
3637 int i;
3639 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3640 return;
3642 qed_llh_mac_to_filter(&high, &low, p_filter);
3644 /* Find the entry and clean it */
3645 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3646 if (qed_rd(p_hwfn, p_ptt,
3647 NIG_REG_LLH_FUNC_FILTER_VALUE +
3648 2 * i * sizeof(u32)) != low)
3649 continue;
3650 if (qed_rd(p_hwfn, p_ptt,
3651 NIG_REG_LLH_FUNC_FILTER_VALUE +
3652 (2 * i + 1) * sizeof(u32)) != high)
3653 continue;
3655 qed_wr(p_hwfn, p_ptt,
3656 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3657 qed_wr(p_hwfn, p_ptt,
3658 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3659 qed_wr(p_hwfn, p_ptt,
3660 NIG_REG_LLH_FUNC_FILTER_VALUE +
3661 (2 * i + 1) * sizeof(u32), 0);
3663 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3664 "mac: %pM is removed from %d\n",
3665 p_filter, i);
3666 break;
3667 }
3668 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3669 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3670 }
3672 int
3673 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3674 struct qed_ptt *p_ptt,
3675 u16 source_port_or_eth_type,
3676 u16 dest_port, enum qed_llh_port_filter_type_t type)
3677 {
3678 u32 high = 0, low = 0, en;
3679 int i;
3681 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3682 return 0;
3684 switch (type) {
3685 case QED_LLH_FILTER_ETHERTYPE:
3686 high = source_port_or_eth_type;
3687 break;
3688 case QED_LLH_FILTER_TCP_SRC_PORT:
3689 case QED_LLH_FILTER_UDP_SRC_PORT:
3690 low = source_port_or_eth_type << 16;
3691 break;
3692 case QED_LLH_FILTER_TCP_DEST_PORT:
3693 case QED_LLH_FILTER_UDP_DEST_PORT:
3694 low = dest_port;
3695 break;
3696 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3697 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3698 low = (source_port_or_eth_type << 16) | dest_port;
3699 break;
3700 default:
3701 DP_NOTICE(p_hwfn,
3702 "Non valid LLH protocol filter type %d\n", type);
3703 return -EINVAL;
3704 }
3705 /* Find a free entry and utilize it */
3706 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3707 en = qed_rd(p_hwfn, p_ptt,
3708 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3709 if (en)
3710 continue;
3711 qed_wr(p_hwfn, p_ptt,
3712 NIG_REG_LLH_FUNC_FILTER_VALUE +
3713 2 * i * sizeof(u32), low);
3714 qed_wr(p_hwfn, p_ptt,
3715 NIG_REG_LLH_FUNC_FILTER_VALUE +
3716 (2 * i + 1) * sizeof(u32), high);
3717 qed_wr(p_hwfn, p_ptt,
3718 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3719 qed_wr(p_hwfn, p_ptt,
3720 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3721 i * sizeof(u32), 1 << type);
3722 qed_wr(p_hwfn, p_ptt,
3723 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3724 break;
3725 }
3726 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3727 DP_NOTICE(p_hwfn,
3728 "Failed to find an empty LLH filter to utilize\n");
3729 return -EINVAL;
3730 }
3731 switch (type) {
3732 case QED_LLH_FILTER_ETHERTYPE:
3733 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3734 "ETH type %x is added at %d\n",
3735 source_port_or_eth_type, i);
3736 break;
3737 case QED_LLH_FILTER_TCP_SRC_PORT:
3738 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3739 "TCP src port %x is added at %d\n",
3740 source_port_or_eth_type, i);
3741 break;
3742 case QED_LLH_FILTER_UDP_SRC_PORT:
3743 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3744 "UDP src port %x is added at %d\n",
3745 source_port_or_eth_type, i);
3746 break;
3747 case QED_LLH_FILTER_TCP_DEST_PORT:
3748 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3749 "TCP dst port %x is added at %d\n", dest_port, i);
3750 break;
3751 case QED_LLH_FILTER_UDP_DEST_PORT:
3752 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3753 "UDP dst port %x is added at %d\n", dest_port, i);
3754 break;
3755 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3756 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3757 "TCP src/dst ports %x/%x are added at %d\n",
3758 source_port_or_eth_type, dest_port, i);
3759 break;
3760 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3761 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3762 "UDP src/dst ports %x/%x are added at %d\n",
3763 source_port_or_eth_type, dest_port, i);
3764 break;
3765 }
3766 return 0;
3767 }
3769 void
3770 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3771 struct qed_ptt *p_ptt,
3772 u16 source_port_or_eth_type,
3773 u16 dest_port,
3774 enum qed_llh_port_filter_type_t type)
3775 {
3776 u32 high = 0, low = 0;
3777 int i;
3779 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3780 return;
3782 switch (type) {
3783 case QED_LLH_FILTER_ETHERTYPE:
3784 high = source_port_or_eth_type;
3785 break;
3786 case QED_LLH_FILTER_TCP_SRC_PORT:
3787 case QED_LLH_FILTER_UDP_SRC_PORT:
3788 low = source_port_or_eth_type << 16;
3789 break;
3790 case QED_LLH_FILTER_TCP_DEST_PORT:
3791 case QED_LLH_FILTER_UDP_DEST_PORT:
3792 low = dest_port;
3793 break;
3794 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3795 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3796 low = (source_port_or_eth_type << 16) | dest_port;
3797 break;
3798 default:
3799 DP_NOTICE(p_hwfn,
3800 "Non valid LLH protocol filter type %d\n", type);
3801 return;
3802 }
3804 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3805 if (!qed_rd(p_hwfn, p_ptt,
3806 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3807 continue;
3808 if (!qed_rd(p_hwfn, p_ptt,
3809 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3810 continue;
3811 if (!(qed_rd(p_hwfn, p_ptt,
3812 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3813 i * sizeof(u32)) & BIT(type)))
3814 continue;
3815 if (qed_rd(p_hwfn, p_ptt,
3816 NIG_REG_LLH_FUNC_FILTER_VALUE +
3817 2 * i * sizeof(u32)) != low)
3818 continue;
3819 if (qed_rd(p_hwfn, p_ptt,
3820 NIG_REG_LLH_FUNC_FILTER_VALUE +
3821 (2 * i + 1) * sizeof(u32)) != high)
3822 continue;
3824 qed_wr(p_hwfn, p_ptt,
3825 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3826 qed_wr(p_hwfn, p_ptt,
3827 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3828 qed_wr(p_hwfn, p_ptt,
3829 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3830 i * sizeof(u32), 0);
3831 qed_wr(p_hwfn, p_ptt,
3832 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3833 qed_wr(p_hwfn, p_ptt,
3834 NIG_REG_LLH_FUNC_FILTER_VALUE +
3835 (2 * i + 1) * sizeof(u32), 0);
3836 break;
3837 }
3839 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3840 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3841 }
3843 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3844 u32 hw_addr, void *p_eth_qzone,
3845 size_t eth_qzone_size, u8 timeset)
3846 {
3847 struct coalescing_timeset *p_coal_timeset;
3849 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3850 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3851 return -EINVAL;
3852 }
3854 p_coal_timeset = p_eth_qzone;
3855 memset(p_eth_qzone, 0, eth_qzone_size);
3856 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3857 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3858 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3860 return 0;
3861 }
3863 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3864 {
3865 struct qed_queue_cid *p_cid = p_handle;
3866 struct qed_hwfn *p_hwfn;
3867 struct qed_ptt *p_ptt;
3868 int rc = 0;
3870 p_hwfn = p_cid->p_owner;
3872 if (IS_VF(p_hwfn->cdev))
3873 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3875 p_ptt = qed_ptt_acquire(p_hwfn);
3876 if (!p_ptt)
3877 return -EAGAIN;
3879 if (rx_coal) {
3880 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3881 if (rc)
3882 goto out;
3883 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3884 }
3886 if (tx_coal) {
3887 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3888 if (rc)
3889 goto out;
3890 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3891 }
3892 out:
3893 qed_ptt_release(p_hwfn, p_ptt);
3894 return rc;
3895 }
3897 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3898 struct qed_ptt *p_ptt,
3899 u16 coalesce, struct qed_queue_cid *p_cid)
3900 {
3901 struct ustorm_eth_queue_zone eth_qzone;
3902 u8 timeset, timer_res;
3903 u32 address;
3904 int rc;
3906 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3907 if (coalesce <= 0x7F) {
3908 timer_res = 0;
3909 } else if (coalesce <= 0xFF) {
3910 timer_res = 1;
3911 } else if (coalesce <= 0x1FF) {
3912 timer_res = 2;
3913 } else {
3914 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3915 return -EINVAL;
3916 }
3917 timeset = (u8)(coalesce >> timer_res);
3919 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3920 p_cid->sb_igu_id, false);
3921 if (rc)
3922 goto out;
3924 address = BAR0_MAP_REG_USDM_RAM +
3925 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3927 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3928 sizeof(struct ustorm_eth_queue_zone), timeset);
3929 if (rc)
3930 goto out;
3932 out:
3933 return rc;
3934 }
3936 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3937 struct qed_ptt *p_ptt,
3938 u16 coalesce, struct qed_queue_cid *p_cid)
3939 {
3940 struct xstorm_eth_queue_zone eth_qzone;
3941 u8 timeset, timer_res;
3942 u32 address;
3943 int rc;
3945 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3946 if (coalesce <= 0x7F) {
3947 timer_res = 0;
3948 } else if (coalesce <= 0xFF) {
3949 timer_res = 1;
3950 } else if (coalesce <= 0x1FF) {
3951 timer_res = 2;
3952 } else {
3953 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3954 return -EINVAL;
3955 }
3956 timeset = (u8)(coalesce >> timer_res);
3958 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3959 p_cid->sb_igu_id, true);
3960 if (rc)
3961 goto out;
3963 address = BAR0_MAP_REG_XSDM_RAM +
3964 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3966 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3967 sizeof(struct xstorm_eth_queue_zone), timeset);
3968 out:
3969 return rc;
3970 }
3972 /* Calculate final WFQ values for all vports and configure them.
3973 * After this configuration each vport will have
3974 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3975 */
3976 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3977 struct qed_ptt *p_ptt,
3978 u32 min_pf_rate)
3979 {
3980 struct init_qm_vport_params *vport_params;
3981 int i;
3983 vport_params = p_hwfn->qm_info.qm_vport_params;
3985 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3986 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3988 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3989 min_pf_rate;
3990 qed_init_vport_wfq(p_hwfn, p_ptt,
3991 vport_params[i].first_tx_pq_id,
3992 vport_params[i].vport_wfq);
3993 }
3994 }
3996 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3997 u32 min_pf_rate)
3999 {
4000 int i;
4002 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4003 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4004 }
4006 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4007 struct qed_ptt *p_ptt,
4008 u32 min_pf_rate)
4009 {
4010 struct init_qm_vport_params *vport_params;
4011 int i;
4013 vport_params = p_hwfn->qm_info.qm_vport_params;
4015 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4016 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4017 qed_init_vport_wfq(p_hwfn, p_ptt,
4018 vport_params[i].first_tx_pq_id,
4019 vport_params[i].vport_wfq);
4020 }
4021 }
4023 /* This function performs several validations for WFQ
4024 * configuration and required min rate for a given vport
4025 * 1. req_rate must be greater than one percent of min_pf_rate.
4026 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4027 * rates to get less than one percent of min_pf_rate.
4028 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4029 */
4030 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4031 u16 vport_id, u32 req_rate, u32 min_pf_rate)
4032 {
4033 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4034 int non_requested_count = 0, req_count = 0, i, num_vports;
4036 num_vports = p_hwfn->qm_info.num_vports;
4038 /* Accounting for the vports which are configured for WFQ explicitly */
4039 for (i = 0; i < num_vports; i++) {
4040 u32 tmp_speed;
4042 if ((i != vport_id) &&
4043 p_hwfn->qm_info.wfq_data[i].configured) {
4044 req_count++;
4045 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4046 total_req_min_rate += tmp_speed;
4047 }
4048 }
4050 /* Include current vport data as well */
4051 req_count++;
4052 total_req_min_rate += req_rate;
4053 non_requested_count = num_vports - req_count;
4055 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
4056 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4057 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4058 vport_id, req_rate, min_pf_rate);
4059 return -EINVAL;
4060 }
4062 if (num_vports > QED_WFQ_UNIT) {
4063 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4064 "Number of vports is greater than %d\n",
4065 QED_WFQ_UNIT);
4066 return -EINVAL;
4067 }
4069 if (total_req_min_rate > min_pf_rate) {
4070 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4071 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4072 total_req_min_rate, min_pf_rate);
4073 return -EINVAL;
4074 }
4076 total_left_rate = min_pf_rate - total_req_min_rate;
4078 left_rate_per_vp = total_left_rate / non_requested_count;
4079 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
4080 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4081 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4082 left_rate_per_vp, min_pf_rate);
4083 return -EINVAL;
4084 }
4086 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4087 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4089 for (i = 0; i < num_vports; i++) {
4090 if (p_hwfn->qm_info.wfq_data[i].configured)
4091 continue;
4093 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4094 }
4096 return 0;
4097 }
4099 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4100 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4101 {
4102 struct qed_mcp_link_state *p_link;
4103 int rc = 0;
4105 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4107 if (!p_link->min_pf_rate) {
4108 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4109 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4110 return rc;
4111 }
4113 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4115 if (!rc)
4116 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4117 p_link->min_pf_rate);
4118 else
4119 DP_NOTICE(p_hwfn,
4120 "Validation failed while configuring min rate\n");
4122 return rc;
4123 }
4125 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4126 struct qed_ptt *p_ptt,
4127 u32 min_pf_rate)
4128 {
4129 bool use_wfq = false;
4130 int rc = 0;
4131 u16 i;
4133 /* Validate all pre configured vports for wfq */
4134 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4135 u32 rate;
4137 if (!p_hwfn->qm_info.wfq_data[i].configured)
4138 continue;
4140 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4141 use_wfq = true;
4143 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4144 if (rc) {
4145 DP_NOTICE(p_hwfn,
4146 "WFQ validation failed while configuring min rate\n");
4147 break;
4148 }
4149 }
4151 if (!rc && use_wfq)
4152 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4153 else
4154 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4156 return rc;
4157 }
4159 /* Main API for qed clients to configure vport min rate.
4160 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4161 * rate - Speed in Mbps needs to be assigned to a given vport.
4162 */
4163 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4164 {
4165 int i, rc = -EINVAL;
4167 /* Currently not supported; Might change in future */
4168 if (cdev->num_hwfns > 1) {
4169 DP_NOTICE(cdev,
4170 "WFQ configuration is not supported for this device\n");
4171 return rc;
4172 }
4174 for_each_hwfn(cdev, i) {
4175 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4176 struct qed_ptt *p_ptt;
4178 p_ptt = qed_ptt_acquire(p_hwfn);
4179 if (!p_ptt)
4180 return -EBUSY;
4182 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4184 if (rc) {
4185 qed_ptt_release(p_hwfn, p_ptt);
4186 return rc;
4187 }
4189 qed_ptt_release(p_hwfn, p_ptt);
4190 }
4192 return rc;
4193 }
4195 /* API to configure WFQ from mcp link change */
4196 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4197 struct qed_ptt *p_ptt, u32 min_pf_rate)
4198 {
4199 int i;
4201 if (cdev->num_hwfns > 1) {
4202 DP_VERBOSE(cdev,
4203 NETIF_MSG_LINK,
4204 "WFQ configuration is not supported for this device\n");
4205 return;
4206 }
4208 for_each_hwfn(cdev, i) {
4209 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4211 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4212 min_pf_rate);
4213 }
4214 }
4216 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4217 struct qed_ptt *p_ptt,
4218 struct qed_mcp_link_state *p_link,
4219 u8 max_bw)
4220 {
4221 int rc = 0;
4223 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4225 if (!p_link->line_speed && (max_bw != 100))
4226 return rc;
4228 p_link->speed = (p_link->line_speed * max_bw) / 100;
4229 p_hwfn->qm_info.pf_rl = p_link->speed;
4231 /* Since the limiter also affects Tx-switched traffic, we don't want it
4232 * to limit such traffic in case there's no actual limit.
4233 * In that case, set limit to imaginary high boundary.
4234 */
4235 if (max_bw == 100)
4236 p_hwfn->qm_info.pf_rl = 100000;
4238 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4239 p_hwfn->qm_info.pf_rl);
4241 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4242 "Configured MAX bandwidth to be %08x Mb/sec\n",
4243 p_link->speed);
4245 return rc;
4246 }
4248 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4249 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4250 {
4251 int i, rc = -EINVAL;
4253 if (max_bw < 1 || max_bw > 100) {
4254 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4255 return rc;
4256 }
4258 for_each_hwfn(cdev, i) {
4259 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4260 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4261 struct qed_mcp_link_state *p_link;
4262 struct qed_ptt *p_ptt;
4264 p_link = &p_lead->mcp_info->link_output;
4266 p_ptt = qed_ptt_acquire(p_hwfn);
4267 if (!p_ptt)
4268 return -EBUSY;
4270 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4271 p_link, max_bw);
4273 qed_ptt_release(p_hwfn, p_ptt);
4275 if (rc)
4276 break;
4277 }
4279 return rc;
4280 }
4282 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4283 struct qed_ptt *p_ptt,
4284 struct qed_mcp_link_state *p_link,
4285 u8 min_bw)
4286 {
4287 int rc = 0;
4289 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4290 p_hwfn->qm_info.pf_wfq = min_bw;
4292 if (!p_link->line_speed)
4293 return rc;
4295 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4297 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4299 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4300 "Configured MIN bandwidth to be %d Mb/sec\n",
4301 p_link->min_pf_rate);
4303 return rc;
4304 }
4306 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4307 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4308 {
4309 int i, rc = -EINVAL;
4311 if (min_bw < 1 || min_bw > 100) {
4312 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4313 return rc;
4314 }
4316 for_each_hwfn(cdev, i) {
4317 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4318 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4319 struct qed_mcp_link_state *p_link;
4320 struct qed_ptt *p_ptt;
4322 p_link = &p_lead->mcp_info->link_output;
4324 p_ptt = qed_ptt_acquire(p_hwfn);
4325 if (!p_ptt)
4326 return -EBUSY;
4328 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4329 p_link, min_bw);
4330 if (rc) {
4331 qed_ptt_release(p_hwfn, p_ptt);
4332 return rc;
4333 }
4335 if (p_link->min_pf_rate) {
4336 u32 min_rate = p_link->min_pf_rate;
4338 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4339 p_ptt,
4340 min_rate);
4341 }
4343 qed_ptt_release(p_hwfn, p_ptt);
4344 }
4346 return rc;
4347 }
4349 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4350 {
4351 struct qed_mcp_link_state *p_link;
4353 p_link = &p_hwfn->mcp_info->link_output;
4355 if (p_link->min_pf_rate)
4356 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4357 p_link->min_pf_rate);
4359 memset(p_hwfn->qm_info.wfq_data, 0,
4360 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4361 }
4363 int qed_device_num_engines(struct qed_dev *cdev)
4364 {
4365 return QED_IS_BB(cdev) ? 2 : 1;
4366 }
4368 static int qed_device_num_ports(struct qed_dev *cdev)
4369 {
4370 /* in CMT always only one port */
4371 if (cdev->num_hwfns > 1)
4372 return 1;
4374 return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4375 }
4377 int qed_device_get_port_id(struct qed_dev *cdev)
4378 {
4379 return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4380 }
4382 void qed_set_fw_mac_addr(__le16 *fw_msb,
4383 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4384 {
4385 ((u8 *)fw_msb)[0] = mac[1];
4386 ((u8 *)fw_msb)[1] = mac[0];
4387 ((u8 *)fw_mid)[0] = mac[3];
4388 ((u8 *)fw_mid)[1] = mac[2];
4389 ((u8 *)fw_lsb)[0] = mac[5];
4390 ((u8 *)fw_lsb)[1] = mac[4];
4391 }