author | Lokesh Vutla <lokeshvutla@ti.com> | |
Tue, 20 Apr 2021 07:47:31 +0000 (13:17 +0530) | ||
committer | Vignesh Raghavendra <vigneshr@ti.com> | |
Mon, 26 Apr 2021 05:07:50 +0000 (10:37 +0530) | ||
commit | 0fd28a32da47f62c5ca6a6aa0770e6296c26bc94 | |
tree | 5a3d4156f11bd882a7b5941eb6fb585689825773 | tree | snapshot (tar.xz tar.gz zip) |
parent | d3bf5a58c356a90fe14d34f213d6195b9a946dc5 | commit | diff |
HACK: net: ethernet: ti: icss-iep: Fix sync0 generation on a compare event
commit 41e5c46849b5 ("net: ethernet: ti: icss-iep: Add support for generating
perout/PPS signal for am57xx variant") introduced support for generating
PPS signal using the following method:
- Configure sync0 in single shot mode with 100ms as pulse length.
- This allows to generate a pulse on first compare event after
sync0 is enabled.
- Adjust CMP[1] register to next second boundary on every compare event.
With this setup only one pulse is created after enabling the pps as
sync0 is configured in single shot mode. In order to create a pulse on
every compare event, sync0 has to be disabled and enabled after the
pulse is completed. There are 2 ways to do it:
- Create a hrtimer task which gets scheduled after completed the pulse. With
this there is a possibility that pulse can be missed, but in current
situation there is not other better way. $patch is implementing this.
- Trigger an interrupt on falling edge of the pulse. But hardware does
not support for this interrupt.
There are other ways on how sync0 can be configured. Below gives details
on why other approaches are not taken:
- Cyclic generation: Where cycle time & pulse length is configured upfront.
Configuring cycle time upfront is a problem, as
cycle time is in IEP clock cycles and cmp event is
based on the IEP counter with compensation. This
way cmp event and sync0 signal goes out of sync.
- Single shot mode: This is the current implementation.
- Cyclic with Ack mode: Where cycle time is configured upfront. Pulse
width is based on the Ack from software. In case
if this is used, ack should happen in cmp
interrupt handler. In this case, the interrupt
handling and ack is fast enough that most of the
times the pulse is not observed on the scope.
- Single shot with Ack mode: Where cycle length and pulse length is not
fixed. Pulse gets started with first compare
event. Pulse gets low with the ack from
software. This will have the same problem
as single shot mode and cyclic with ack
mode.
After these experiments, the possible approach is to use Single shot
mode and re-enable sync after every pulse. This patch is using a hrtimer
task for re-enabling sync and that is why it is marked as HACK.
TODO: Explore if the task can be offloaded to firmware and then revert
this HACK
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
commit 41e5c46849b5 ("net: ethernet: ti: icss-iep: Add support for generating
perout/PPS signal for am57xx variant") introduced support for generating
PPS signal using the following method:
- Configure sync0 in single shot mode with 100ms as pulse length.
- This allows to generate a pulse on first compare event after
sync0 is enabled.
- Adjust CMP[1] register to next second boundary on every compare event.
With this setup only one pulse is created after enabling the pps as
sync0 is configured in single shot mode. In order to create a pulse on
every compare event, sync0 has to be disabled and enabled after the
pulse is completed. There are 2 ways to do it:
- Create a hrtimer task which gets scheduled after completed the pulse. With
this there is a possibility that pulse can be missed, but in current
situation there is not other better way. $patch is implementing this.
- Trigger an interrupt on falling edge of the pulse. But hardware does
not support for this interrupt.
There are other ways on how sync0 can be configured. Below gives details
on why other approaches are not taken:
- Cyclic generation: Where cycle time & pulse length is configured upfront.
Configuring cycle time upfront is a problem, as
cycle time is in IEP clock cycles and cmp event is
based on the IEP counter with compensation. This
way cmp event and sync0 signal goes out of sync.
- Single shot mode: This is the current implementation.
- Cyclic with Ack mode: Where cycle time is configured upfront. Pulse
width is based on the Ack from software. In case
if this is used, ack should happen in cmp
interrupt handler. In this case, the interrupt
handling and ack is fast enough that most of the
times the pulse is not observed on the scope.
- Single shot with Ack mode: Where cycle length and pulse length is not
fixed. Pulse gets started with first compare
event. Pulse gets low with the ack from
software. This will have the same problem
as single shot mode and cyclic with ack
mode.
After these experiments, the possible approach is to use Single shot
mode and re-enable sync after every pulse. This patch is using a hrtimer
task for re-enabling sync and that is why it is marked as HACK.
TODO: Explore if the task can be offloaded to firmware and then revert
this HACK
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
drivers/net/ethernet/ti/icss_iep.c | diff | blob | history |