| author | Suman Anna <s-anna@ti.com> | |
| Fri, 15 Feb 2019 18:28:35 +0000 (12:28 -0600) | ||
| committer | Suman Anna <s-anna@ti.com> | |
| Sun, 24 Feb 2019 01:20:48 +0000 (19:20 -0600) | ||
| commit | 39bc0b0bb27563c00003b8a46a77a51776a40afa | |
| tree | 058c3a260871e8bb2e7522f2be28b9b0c795c3e6 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 08f9362d3d428d39d41f4c224d6feb3e8164676a | commit | diff |
soc: ti: pruss: Add support for PRU-ICSS subsystems on AM57xx SoCs
The AM57xx family of SoCs supports two PRU-ICSS instances, each of
which has two PRU processor cores. The two PRU-ICSS instances are
identical to each other, and are very similar to the PRU-ICSS1 of
AM33xx/AM43xx except for a few minor differences like the RAM sizes
and the number of interrupts coming into the MPU INTC. They do
not have a programmable module reset line unlike those present on
AM33xx/AM43xx SoCs. The modules are reset just like any other IP
with the SoC's global cold/warm resets. Each PRU-ICSS's INTC is also
preceded by a Crossbar that enables multiple external events to be
routed to a specific number of input interrupt events. Any interrupt
event directed towards PRUSS needs this crossbar to be setup properly
on the firmware side.
The existing PRUSS platform drivers have been enhanced to support
these AM57xx PRU-ICSS instances through new AM57xx specific
compatibles for properly probing and booting all the different PRU
cores in each PRU-ICSS processor subsystem. The SoC-level integration
differences are dealt with using match data within the PRUSS SoC bus
driver. A build dependency with SOC_DRA7XX is also added to enable
the driver to be built in AM57xx-only configuration (there is no
separate Kconfig option for AM57xx vs DRA7xx). The initial names
for the firmware images for each PRU core are retrieved from DT
nodes, and can be adjusted through sysfs if required.
Signed-off-by: Suman Anna <s-anna@ti.com>
The AM57xx family of SoCs supports two PRU-ICSS instances, each of
which has two PRU processor cores. The two PRU-ICSS instances are
identical to each other, and are very similar to the PRU-ICSS1 of
AM33xx/AM43xx except for a few minor differences like the RAM sizes
and the number of interrupts coming into the MPU INTC. They do
not have a programmable module reset line unlike those present on
AM33xx/AM43xx SoCs. The modules are reset just like any other IP
with the SoC's global cold/warm resets. Each PRU-ICSS's INTC is also
preceded by a Crossbar that enables multiple external events to be
routed to a specific number of input interrupt events. Any interrupt
event directed towards PRUSS needs this crossbar to be setup properly
on the firmware side.
The existing PRUSS platform drivers have been enhanced to support
these AM57xx PRU-ICSS instances through new AM57xx specific
compatibles for properly probing and booting all the different PRU
cores in each PRU-ICSS processor subsystem. The SoC-level integration
differences are dealt with using match data within the PRUSS SoC bus
driver. A build dependency with SOC_DRA7XX is also added to enable
the driver to be built in AM57xx-only configuration (there is no
separate Kconfig option for AM57xx vs DRA7xx). The initial names
for the firmware images for each PRU core are retrieved from DT
nodes, and can be adjusted through sysfs if required.
Signed-off-by: Suman Anna <s-anna@ti.com>