| author | Suman Anna <s-anna@ti.com> | |
| Sat, 29 Jun 2019 01:52:09 +0000 (01:52 +0000) | ||
| committer | Suman Anna <s-anna@ti.com> | |
| Mon, 1 Jul 2019 16:48:05 +0000 (11:48 -0500) | ||
| commit | 4022d1222efe82fb17ccf271af352b1206b012e0 | |
| tree | ee94c5ad0efda2f8a7d06bd7a5c60192d8681fe0 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 57c76b3f28042138bf92c203a3db576a66aab5cc | commit | diff |
irqchip/irq-pruss-intc: Fix erroneous channel/host mapping logic
The PRUSS INTC uses two-levels of many-to-one mappings to route various
PRU System Events to a limited number of output interrupt lines connected
to various processors on the SoC. This event mapping configuration logic
is optimized to program the associated Channel Map Registers (CMRx) and
Host Interrupt Map Registers (HMRx) only when a new program is being
loaded/started and simply disables the same events and interrupt channels
without zeroing out the corresponding map registers when stopping a PRU.
The map logic currently does not zero out the previous field value before
programming the new value, and thereby potentially mapping a completely
different value in the CMR and HMR registers (if previous values are not
zero) and resulting in non-functional interrupts. Fix this erroneous
bitwise logic.
Reported-by: Nick Saulnier <nsaulnier@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
The PRUSS INTC uses two-levels of many-to-one mappings to route various
PRU System Events to a limited number of output interrupt lines connected
to various processors on the SoC. This event mapping configuration logic
is optimized to program the associated Channel Map Registers (CMRx) and
Host Interrupt Map Registers (HMRx) only when a new program is being
loaded/started and simply disables the same events and interrupt channels
without zeroing out the corresponding map registers when stopping a PRU.
The map logic currently does not zero out the previous field value before
programming the new value, and thereby potentially mapping a completely
different value in the CMR and HMR registers (if previous values are not
zero) and resulting in non-functional interrupts. Fix this erroneous
bitwise logic.
Reported-by: Nick Saulnier <nsaulnier@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
| drivers/irqchip/irq-pruss-intc.c | diff | blob | history |