| author | Suman Anna <s-anna@ti.com> | |
| Thu, 21 Feb 2019 03:09:32 +0000 (21:09 -0600) | ||
| committer | Suman Anna <s-anna@ti.com> | |
| Mon, 25 Feb 2019 19:31:39 +0000 (13:31 -0600) | ||
| commit | 636b6be0838934a120db5849690d90c231cc1c84 | |
| tree | 556f40ecc13eb29f5efd6cc6861e985a3ef22d92 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 427241acbe266a9c0f0309b2b4809faf98d1d528 | commit | diff |
arm64: dts: ti: k3-am65-main: Add ICSSG nodes
Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
that are present on the K3 AM65x SoCs. The three ICSSGs are identical
to each other for the most part, with the ICSSG2 supporting slightly
enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
is represented by a pruss-soc-bus node and a child PRUSS subsystem node.
These nodes are enabled by default.
The ICSSGs on K3 AM65x SoCs are super-sets of the PRUSS on the AM57xx/
6AK2G SoCs except for larger Shared Data RAM and the lack of a PRU-ICSS
crossbar. They include two auxiliary PRU cores called RTUs and few other
additional sub-modules. The interrupt integration is also different on
the K3 AM65x SoCs and are propagated through various SoC-level Interrupt
Router and Interrupt Aggregator blocks.
The ICSSG subsystem node contains the entire address space and the
various interrupts generated towards the main MPU. The various
sub-modules of the ICSSG are represented as individual child
nodes (so platform devices themselves) of the PRUSS subsystem node.
These include the two PRU cores and the interrupt controller. The
Industrial Ethernet Peripheral (IEP), the Real Time Media Independent
Interface controller (MII_RT), and the CFG sub-module are represented
as syscon nodes. All the Data RAMs are represented within a child
node of its own named 'memories' without any compatible.
The DT nodes use all standard properties. The regs property in the
PRU/RTU nodes define the addresses for the Instruction RAM, the Debug
and Control sub-modules for that PRU core. The firmware for each
PRU/RTU core is defined through a 'firmware-name' property.
The default names for the firmware images for each PRU and RTU core
are defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
ICSSG0 PRU0 Core: am65x-pru0_0-fw ; ICSSG0 RTU0 Core: am65x-rtu0_0-fw
ICSSG0 PRU1 Core: am65x-pru0_1-fw ; ICSSG0 RTU1 Core: am65x-rtu0_1-fw
ICSSG1 PRU0 Core: am65x-pru1_0-fw ; ICSSG1 RTU0 Core: am65x-rtu1_0-fw
ICSSG1 PRU1 Core: am65x-pru1_1-fw ; ICSSG1 RTU1 Core: am65x-rtu1_1-fw
ICSSG2 PRU0 Core: am65x-pru2_0-fw ; ICSSG2 RTU0 Core: am65x-rtu2_0-fw
ICSSG2 PRU1 Core: am65x-pru2_1-fw ; ICSSG2 RTU1 Core: am65x-rtu2_1-fw
TODO:
Add sub-nodes for new additional sub-modules like IEP2, MII_RT2 etc.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
that are present on the K3 AM65x SoCs. The three ICSSGs are identical
to each other for the most part, with the ICSSG2 supporting slightly
enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
is represented by a pruss-soc-bus node and a child PRUSS subsystem node.
These nodes are enabled by default.
The ICSSGs on K3 AM65x SoCs are super-sets of the PRUSS on the AM57xx/
6AK2G SoCs except for larger Shared Data RAM and the lack of a PRU-ICSS
crossbar. They include two auxiliary PRU cores called RTUs and few other
additional sub-modules. The interrupt integration is also different on
the K3 AM65x SoCs and are propagated through various SoC-level Interrupt
Router and Interrupt Aggregator blocks.
The ICSSG subsystem node contains the entire address space and the
various interrupts generated towards the main MPU. The various
sub-modules of the ICSSG are represented as individual child
nodes (so platform devices themselves) of the PRUSS subsystem node.
These include the two PRU cores and the interrupt controller. The
Industrial Ethernet Peripheral (IEP), the Real Time Media Independent
Interface controller (MII_RT), and the CFG sub-module are represented
as syscon nodes. All the Data RAMs are represented within a child
node of its own named 'memories' without any compatible.
The DT nodes use all standard properties. The regs property in the
PRU/RTU nodes define the addresses for the Instruction RAM, the Debug
and Control sub-modules for that PRU core. The firmware for each
PRU/RTU core is defined through a 'firmware-name' property.
The default names for the firmware images for each PRU and RTU core
are defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
ICSSG0 PRU0 Core: am65x-pru0_0-fw ; ICSSG0 RTU0 Core: am65x-rtu0_0-fw
ICSSG0 PRU1 Core: am65x-pru0_1-fw ; ICSSG0 RTU1 Core: am65x-rtu0_1-fw
ICSSG1 PRU0 Core: am65x-pru1_0-fw ; ICSSG1 RTU0 Core: am65x-rtu1_0-fw
ICSSG1 PRU1 Core: am65x-pru1_1-fw ; ICSSG1 RTU1 Core: am65x-rtu1_1-fw
ICSSG2 PRU0 Core: am65x-pru2_0-fw ; ICSSG2 RTU0 Core: am65x-rtu2_0-fw
ICSSG2 PRU1 Core: am65x-pru2_1-fw ; ICSSG2 RTU1 Core: am65x-rtu2_1-fw
TODO:
Add sub-nodes for new additional sub-modules like IEP2, MII_RT2 etc.
Signed-off-by: Suman Anna <s-anna@ti.com>
| arch/arm64/boot/dts/ti/k3-am65-main.dtsi | diff | blob | history |