| author | Suman Anna <s-anna@ti.com> | |
| Fri, 15 Feb 2019 16:54:19 +0000 (10:54 -0600) | ||
| committer | Suman Anna <s-anna@ti.com> | |
| Sat, 23 Feb 2019 17:21:11 +0000 (11:21 -0600) | ||
| commit | 9d98b91e4296798c9a77bbca1c7954f4ef46e50c | |
| tree | f552d4f3b0fb5539c8c25d7179a8003926c45461 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 62160db6fc07003f15e77c776314ba8d37b5adc0 | commit | diff |
dt-bindings: irqchip: Add PRUSS interrupt controller bindings
The Programmable Real-Time Unit Subsystem (PRUSS) contains an
interrupt controller (INTC) that can handle various system input
events and post interrupts back to the device-level initiators.
The INTC can support upto 64 input events with individual control
configuration and hardware prioritization. These events are mapped
onto 10 interrupt signals through two levels of many-to-one mapping
support. Different interrupt signals are routed to the individual
PRU cores or to the host CPU.
Add the bindings document for this interrupt controller. The binding
currently covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx;
and a Keystone 2 architecture based 66AK2G SoC. The Davinci based
OMAPL138 SoCs and K3 architecture based AM65x SoCs will be covered
in a subsequent patch.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
The Programmable Real-Time Unit Subsystem (PRUSS) contains an
interrupt controller (INTC) that can handle various system input
events and post interrupts back to the device-level initiators.
The INTC can support upto 64 input events with individual control
configuration and hardware prioritization. These events are mapped
onto 10 interrupt signals through two levels of many-to-one mapping
support. Different interrupt signals are routed to the individual
PRU cores or to the host CPU.
Add the bindings document for this interrupt controller. The binding
currently covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx;
and a Keystone 2 architecture based 66AK2G SoC. The Davinci based
OMAPL138 SoCs and K3 architecture based AM65x SoCs will be covered
in a subsequent patch.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
| Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt | [new file with mode: 0644] | blob |